Power Transistor Switch

Where load requirements dictate the switching of high-amperage, direct-current (such as in welding operations, etc.) prior art methods have been found to be either extremely expensive or generally unsatisfatory. The utilization of extremely high-current transistors is, of course, expensive and prior art paralleling techniques heretofore have resorted to individual discrete emitter or base resistances with the power losses inherent in their utilization. The general problem involved in paralleling transistors is the result of the broad parametric range of junction characteristics, which in turn, results in failure to share load current during turn-on, on-state (saturation), and turn-off, which in turn, causes destruction of the junction.

Another scheme in limited use lies in the selection of power transistors with matched parameters. The problems encountered here lie in replacement situations, parameter variations because of aging, and relatively high initial costs.

The present invention relates to a power transistor switch, and, more particularly, to a power transistor switch utilizing transistor paralleling.

According to the invention, a power transistor switch is provided in which a plurality of transistors are paralleled without resort to individual discrete emitter or base resistances and their attendant power loss. A hybrid saturable core transformer is utilized for coupling, switching signals to the bases of the paralleled transistors. The transformer has a reset and turn-on primary winding, a turn-off primary winding, and a plurality of separate secondary windings, each coupled between a separate transistor's base and emitters together with a regenerative secondary winding for current feedback, in series with the transistor collectors and the load. The plurality of secondary windings are multifilar wound to insure identical switching drive to each transistor.

The utilization of transistors in parallel has several advantages. There is inherently a low forward impedance together with low transition time in multiple junction transistor geometry. These types of transistors are, of course, very inexpensive compared to the heavy current-handling, high-junction area transistors that the instant technique is designed to replace.

The paralleling technique employed results in a much less expensive, high-amperage current switch together with economies in space and weight as will be appreciated by those skilled in the art with reference to the detailed discussion below.

An object of the present invention is the provision of a high-amperage, direct-current transistor switch.

A further object of the invention is the provision of a high-amperage, direct-current switch having a low forward impedance.

Another object of the invention is the provision of a high-amperage, direct-current switch having a rapid transition time.

Still another object of the invention is the provision of a high-amperage, direct-current switch utilizing low-loss paralleling of transistors.

Yet another object of the invention is the provision of a high-amperage, direct-current switch which is extremely efficient.

A still further object of the invention is the provision of a high-amperage, direct-current switch which is extremely inexpensive.

Other objects and many of the attendant advantages of the present invention will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings in which like reference numerals designate like parts throughout the Figures thereon and wherein:

FIG. 1 is a schematic diagram of the preferred embodiment of the present invention;

FIG. 2 is a series of wave forms taken at various points throughout the embodiment of FIG. 1; and

FIG. 3 is a schematic diagram of the equivalent circuit of the embodiment of FIG. 1.

Referring to FIG. 1, an input voltage is applied across terminals 11 and 12 (12 being the common terminal) and a control signal is applied at input terminal 13 which is connected to the base element B of transistor Q.sub.1. Common terminal 12 is coupled to emitter E of transistor Q.sub.1 and to one end of winding W2 of transformer T1. Common terminal 12 is also coupled to one end of windings W3 (n + 1) and W3 (n) and to emitters E of transistors Q.sub.(n) and Q.sub.(n + 1). Incoming voltage terminal 11 is coupled through R.sub.reset to one end of winding W1 of transformer T1 and collector C of transistor Q.sub.1 and the cathode of diode CR1. The anode of diode CR1 is coupled to another end of winding W2 of transformer T1. Incoming voltage terminal 11 is also coupled through resistance R.sub.load and winding W4 of transformer T1 in series to collectors C of transistors Q.sub.(n .sub.+ 1) and Q.sub.(n).

Referring to FIG. 2, four square waves are illustrated in timed relationship, which are labeled control, Q.sub.1-C, Q.sub.(n), Q.sub.(n .sub.+ 1), and -B; Q.sub.(n), Q.sub.(n .sub.+ 1), -C with times T1 and T2 indicated at 1/f.

Referring to FIG. 3, an equivalent circuit is shown with incoming voltage terminals 11 and 12, 12 being common terminal. Voltage at terminal 11 is coupled through lumped constant resistance 14 and lumped constant inductance 16 to inductances L.sub.L, W.sub.3n .sub.+ 1 and L.sub.L for W3N resistance R.sub.W3n .sub.+ 1 to one side of R.sub.L Q.sub.(n) the other side of which is connected to terminal 12. Lumped inductance 16 is also coupled through inductance L.sub.LW3n and resistance R.sub.W3n to one side of R.sub.L Q.sub.(n), the other side of which is coupled to common terminal 12. Lumped capacitance 17 is shown connected to the junction of lumped resistance 14 and lumped conductance 16 to common terminal 12 and lumped inductance 18 is shown coupled between the junction of lumped inductance 16 and L.sub.LW3(n) to common terminal 12. Lumped capacitances 19 and 20 are shown coupled across R.sub.L Q.sub.(n+1) and R.sub.LQN, respectively.

Referring to FIG. 1, quiescently with transistor Q1 cut off at zero base current, transistors Q.sub.(n) and Q.sub.(n .sub.+ 1) are in a cut off condition. When a forward bias is applied at terminal 13 to the base of transistor Q1, transistor Q1 turns on and the core of the transformer is saturated due to the current through winding W1. The phasing of the primary and secondary windings of the transformer result in an initial negative charge being inductably coupled to the bases of transistors Q.sub.(n) and Q.sub.(n .sub.+ 1), which hold transistors Q.sub.(n) and Q.sub.(n .sub.+ 1) cut off. When at time T1 (FIG. 2) the voltage at control point 13 is dropped to zero cutting off collector current in transistor Q1 and current through primary winding W1.

At this time, the core of transformer T1 reverts to an unsaturated condition and a positive square wave is applied to the bases of transistors Q.sub.(n) and Q.sub.(n .sub.+ 1) turning them on.

Current then flows from common terminal 12 through the emitter base of transistors Q.sub.(n) and Q.sub.(n .sub.+ 1) parallel and through secondary winding W4 of transformer T1 and resistance R.sub.load to positive terminal 11. The phasing of secondary winding W4 as indicated maintains a positive voltage through inductive coupling to multifilar windings W3.sub.(n) and W3.sub.(n .sub.+ 1) to the bases of transistors Q.sub.(n) and Q.sub.(n .sub.+ 1), which in turn, maintains collector current through resistance R.sub.load. When control point 13 is driven positive, collector current again flows in transistor Q.sub.1 through primary winding W1 of transformer T1, the transformer again returns the bases of transistors Q.sub.(n) and Q.sub.(n .sub.+ 1) to zero, cutting off their collector currents.

Energy stored in the base emitter junctions of transistors Q.sub.N and Q.sub.N .sub.+ 1 then drives reverse current through these junctions resulting in a positive potential at the top of primary winding W2 and since Q.sub.1 is conducting, primary winding W2 is effectively short-circuited through diode CR1. This removes all base current from transistors Q.sub.(n) and Q.sub.(n .sub.+ 1) and effects an extremely positive control in switching their collector currents to an off position. Hence, primary winding W1 can be considered a turn-on winding, and secondary winding W4 can be considered a sustaining winding being polarized for regenerative feedback to secondary windings W3(n ) and W3(n + 1).

Winding W2 can be considered a switch-off winding. Winding W3N and W3N + 1 indicate that any practical number of transistors can be paralleled, each having their own separate control winding with all of the control windings fabricated in a multifilar fashion. This is to insure that the parameters of transformer T1 as seen by the secondary switching windings will be as identical as possible and all of the paralleled transistors will be turned on and off simultaneously.

It can also be appreciated that redundancy is achieved by the very nature of paralleling techniques, i.e., should one of the parallel power transistors fail, a proportional drop in load current will be the only result instead of further component failures that can happen in other paralleling techniques.

The design equations for transformer T1 are as follows: ##EQU1##

Where: A.sub.C = cross-sectional area T1 (in.sup.2) ##EQU3##

t.sub.1 = t.sub.on = t.sub.2 = t.sub.off ##EQU4##

L.sub.LW3 < L.sub.W3 .times. 10.sup..sup.-3

A typical design is as follows:

Assume that transistor Q1 is a commercial-type 2N3055, transistors Q.sub.(n) and Q.sub.(n .sub.+ 1) are commercial-type 2N3771, and the result at terminal 11 is 24 volts DC, R.sub.reset is 250 ohms and R.sub.load is 2.4 ohms. The transformer windings have the following parameters:

Winding W2--12.5 volts with 255.5 turns; Winding W1--15 volts with 300.5 turns; Winding W3--1.25 volts with 25.5 turns; Winding W4--0.125 volts with 2.5 turns.

This will result in a collector current of 10 amps in each of the paralleled transistors, i.e., in the case of 10 parallel transistors, the current through resistance R.sub.load would be 100 amps.

The above data is further assuming that the on-time is equal to or less than 0.85 of the off-time, i.e., t.sub.on is equal to or less than 0.85 t.sub.off.

It should be noted that the parallel technique described above is typically operated in a saturated mode but it can operate in an unsaturated switching mode as will be appreciated by those skilled in the art.

Referring to FIG. 3, the functional understanding of this parallel transistor drive depends on examination of transformer equivalent circuit geometry, particularly in the high-frequency mode. Since relatively brief time intervals are desired properties for transition mode parameters (typically in the sub-microsecond region), it can be seen that the leakage reactance components (L.sub.1) will be effective in equal distribution of energy to R.sub.L.sbsb.1, in this case the emitter-base junctions of the transistors. Insofar as the transformer may be considered a bilateral device, it is evident that these leakage reactance components will be effective in both source and sink modes, i.e., during turn-on or turn-off transition modes. Initial selection of the absolute value of L.sub.L is determined by transistor parameters, and is subsequently attained by resort to ordinary transformer design practice (see Fortesque). Multifilar winding techniques insure close matching of both L.sub.L and R values (typically .+-. 10%), thus maintaining shared parameters within this range. During static on-state conditions, the R values are instrumental in the sharing process, in combination with the characteristic load-line properties of major junction area silicon transistors. Fundamental transformer characteristics, i.e., E.sub.1 = E.sub.2 if N.sub.1 = N.sub.2, contribute substantially.

It is worth noting that true redundancy is achieved, in that no possible failure mode of Q.sub.(n) will, in and of itself, result in Q.sub.(n .sub.+ 1) malfunction, provided that "out-of-saturation" operation is a precluded mode.

It should be understood, of course, that the foregoing disclosure relates to only a preferred embodiment of the invention, and that it is intended to cover all changes and modifications of the example of the invention herein chosen, for the purposes of the disclosure, which do not constitute departures from the spirit and scope of the invention.