US 4,041,296 AGrant
High-Speed Digital Multiply-by-Device
Issue Date:1977-08-09
•3 Claims
•5 Drawing Sheets
Abstract
High speed digital multiply-by-three device comprising a sum generation unit associated with a carry look-ahead unit, the latter comprising means for generating the carry bit C.sub.k.sub.+1 to be fed to the (k+1).sup.th stage of said sum generation unit by performing the logic function
Metadata
Assignee
- International Business Machines Incorp.
Inventors
- Alain Dauby
- Vladimir Riso
- Daniel Roger-Rodes
Application Information
Application Number:US 6373593
Filing Date:1975-12-03
Priority Date:1975-12-03
Art Unit:236
Classifications
IPC:
G06F 752
Field of Search:
235164;175
Patent Drawings (5 sheets)
Description
Background of the Invention
This invention relates to a high-speed digital device for multiplying any binary number by three.
In many computing devices, and particularly in digital multiplier devices, it is often necessary to multiply a given number x by three. One of the more attractive prior art methods of performing multiplications consists in dividing the multiplier term into groups of bits of constant length and in analyzing such groups to determine a multiple of the multiplicand to be used in order to carry out the desired multiplication as a sequence of accumulations. Once this multiple has been determined, means for generating same must of course be provided.
More specifically, let us assume that, in a multiplication XY to be performed, the multiplier Y is divided into several groups of three bits each, beginning with the lowest-order bit, plus one of the bits of the preceding group. For example, if ##EQU1## Groups g1, g2, g3 and g4 are successively analyzed. To each configuration of a group g corresponds a contribution which is a multiple of X to be added to the contributions of the previous groups to finally provide, after group g4 has been processed, the desired product of XY. The following table summarizes the contributions associated with the various configurations of g.
The above method makes it possible to find a compromise between the number of adders required to build the multiplier device and the speed of the latter. However, it will be seen that the speed of the device is dependent, in particular, upon the time required to determine the multiples of X. This is especially troublesome where the device must perform successive multiplications XY, X'Y', X"Y", etc., at a rate which should be as fast as possible and in any event faster than that at which the operands X, Y, X', Y', etc., are received. In such cases, the so-called pipelining technique is sometimes used. That is, as soon as group g1 of Y has been processed, the associated circuits start processing group g1 of Y', thereby initiating the computation of X'Y', then of X"Y", etc., before the computation of XY is completed. It is clear, therefore, that a device capable of generating the multiples of terms X, X',X", etc., as quickly as possible would be quite useful. Multiples such as X, 2X, 4X, that is, multiples belonging to the family 2.sup.N X, can readily be generated from X. All that is required to do so is to shift X N bit positions toward the higher-order positions. However, this does not apply when 3X or one of its multiples is required.
In a prior art device designed to multiply binary numbers by means of analyses of the groups of bits g that comprise the multiplier, 3X is obtained by adding X to 2X in two successive operations. Two basic cycles of operation instead of one are therefore required. Such a process is too slow and does not permit maintaining an operating cycle of constant duration regardless of the configuration of the groups of bits.
Alternatively, 3X can be generated using an additional device. In that case, the additional device should be inexpensive and capable of operating at high speed.
Accordingly, it is an object of the present invention to provide a high-speed device for multiplying any binary number X by three.
Another object of the invention is to implement such a device using a limited number of circuits, thereby reducing the size of the device.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.
The Drawings
FIGS. 1 and 1A represent an implementation of the carry look-ahead unit of the present invention.
FIG. 2 illustrates an implementation of the multiplier device of the invention.
FIG. 3 is an implementation of another multiplier device realized in accordance with the invention.
FIGS. 4 and 5 show circuits associated with the device of FIG. 3. These features show the circuitry for providing an adder that performs the operation X + 2X, the adder being divided into a number of sub-adders.
Detailed Description of the Invention
The multiplier device of the present invention provides 3X by adding X to 2X in accordance with the well-known carry look-ahead technique, but is characterized in that it includes a carry look-ahead unit that feeds the inputs of a sum generation unit, with the carry look-ahead unit providing the carry bit intended for the stage of order (k+1) of the sum generation unit by means of the following logic combinations of the bits of X:
an adder comprising a basic carry look-ahead unit and a basic sum generation unit is described in an article entitled "High-Speed Arithmetic in Binary Computers" by O. L. McSorley in "Proceedings of the IRE, " January 1961. The carry look-ahead unit, by logically combining the bits of the words to be added together, supplies a carry bit to each stage of the sum generation unit. This arrangement could be used to generate the multiple of X being sought here, but would require the provision of an excessive number of circuits for the carry look-ahead unit.
The present invention enables a simple carry generator to be realized. If the bits of X are designated X.sub.0, X.sub.1, . . . , X.sub.k, the carry bits, C.sub.0, C.sub.1, . . . , C.sub.k, and the sum bits, S.sub.0, . . . , S.sub.k, and if the so-called two's complement code is used and if X.sub.n is assumed to be the sign bit order, the addition X+2X can be written:
The only possible combinations of X.sub.k and X.sub.k.sub.-1 are:
In the first case, no carry bit C.sub.k-1 intended for column "k+1" of the above table can be generated in column "k" regardless of the value of C.sub.k since X.sub.k = 0 and X.sub.k.sub.-1 = 0.
In the second case (X.sub.k = 0 and X.sub.k.sub.-1 = 1), the generation of a carry bit depends on the value of C.sub.k. Thus, C.sub.k.sub.+1 = 1 where a carry bit is generated in column "k-1" or any of the preceding columns. This is summarized by the formula
in the third case (X.sub.k = 1 and X.sub.k.sub.-1 = 0), a carry bit for column "k+1" is generated if a carry bit has been generated in columns "k-2" and "k-3" or any of the preceding columns. Thus,
lastly, in the fourth case (X.sub.k = 1 and X.sub.k.sub.-1 = 1), a carry bit is always generated, so that
Formulas (1), (2) and (3) show that all cases where a carry bit intended for column "k+1" is generated are derived from the general logic formula
the carry generator of the multiplier device of the present invention can be implemented in various manners depending upon the technology the designer proposes to utilize, but is in no way restricted to the use of a particular technology. It must only be such as to satisfy formula (4) or any equivalent logic formula while allowing the size of the multiplier device and the power consumption to be minimized.
FIGS. 1 and 1A illustrate a carry generator implemented, in accordance with the invention, with NOR circuits for an 8-bit work X written X.sub.7 . . . X.sub.3 X.sub.2 X.sub.1 X.sub.0. The generator includes a first stage comprising 16 NOR circuits N1-N16, and a second stage comprising six NOR circuits N17-N22. The inputs of these NOR circuits are connected to the points shown in the following table:
The outputs from the NOR circuits of the second stage provide the inverted values of the desired carry bits, i.e. C3, C4, C5, C6, C7 and C8. The other bits are obtained more simply since co=., c1= 0 and C2=X1.X0.
Accordingly, the multiplier device of the invention can be implemented in accordance with the diagram of FIG. 2. This device includes a carry generator (GR) which is similar to that of FIG. 1 and provides carry bits C3-C8 to a sum generator (GS). Where the arrangement of FIG. 1 is used to determine the carry bits, bit inverters are required for the inputs and the outputs of generator GR. The sum generator supplies S0=X0 directly. Bit S1 is obtained by means of an Exclusive OR Invert circuit XOR1 the inputs of which receive X1 and X0. Bit S2 is supplied by an Exclusive OR Invert circuit XOR2 which receives X2 and the output of an AND circuit A1, which itself receives X0, as inverted by an inverter 1, and X1. Bits S3-S7 are respectively provided by a pair of Exclusive OR Invert circuits XOR3, XOR3' - XOR7, XOR7'. If we call XORp and XORp' the pair of order p, we may say that the inputs of XORp receive Xp and X.sub.p.sub.-1 while the inputs of XORp' receive the carry bit Cp and output from XORp. The bit Sp is obtained at the output of XORp'. If X7 is the sign bit S8 is directly obtained from C8 and bit S9 is directly provided by X7. It will be appreciated that if X7 were not the sign bit S8 would be obtained from X7 exclusive OR C8 and S9 would be X7.C8.
The outputs from the NOR circuits of the second stage provide the inverted values of the desired carry bits, i.e. C3, C4, C5, C6, C7 and C8. The other bits are obtained more simply since CO=0, C1=0 and C2=X1.X0.
Accordingly, the multiplier device of the invention can be implemented in accordance with the diagram of FIG. 2. This device includes a carry generator (GR) which is similar to that of FIG. 1 and provides carry bits C3-C8 to a sum generator (GS). Where the arrangement of FIG. 1 is used to determine the carry bits, bit inverters are required for the inputs and the outputs of generator GR. The sum generator supplies S0=X0 directly. Bit S1 is obtained by means of an Exclusive OR Invert circuit XOR1 the inputs of which receive X1 and X0. Bit S2 is supplied by an Exclusive OR Invert circuit XOR2 which receives X2 and the output of an AND circuit A1, which itself receives X0, as inverted by an inverter 1, and X1. Bits S3-S7 are respectively provided by a pair of Exclusive OR Invert circuits XOR3, XOR3' - XOR7, XOR7'. If we call XORp and XORp' the pair of order p, we may say that the inputs of XORp receive Xp and X.sub.p.sub.-1 while the inputs of XORp' receive the carry bit Cp and output from XORp. The bit Sp is obtained at the output of XORp'. If X7 is the sign bit S8 is directly obtained from C8 and bit S9 is directly provided by X7. It will be appreciated that if X7 were not the sign bit S8 would be obtained from X7 exclusive OR C8 and S9 would be X7.C8.
This architecture of the proposed multiplier device is valid regardless of the number of bits of X but does not necessarily represent the best solution considering the size of the integrated circuit that would be required to implement it. An alternative solution would consist in dividing the adder that performs the operation X+2X into a number of sub-adders. FIG. 3 illustrates a means for processing a 16-bit word X as two words of eight bits each. The lower-order bits (2.sup.0 to 2.sup.7) are processed in a first adder ADD1 and the higher-order bits (2.sup.8 to 2.sup.15) in a second adder ADD2. Both of these adders use the technique described earlier and are identical with the adder of FIG. 2 except that in ADD1 X7 is not the sign bit so that, as mentioned previously, S8 would be provided by X7 exclusive OR C8 and S9 would be X7.C8. ADD1 provides bits S0-S7 of the result as well as two bits of weights 2.sup.8 and 2.sup.9 which will be added to the two lowest-order bits supplied by ADD2. Bits 2.sup.8 and 2.sup.9 may be regarded as carries which must be allowed to propagate through the bits of ADD2. A circuit designated PROPAG is provided for this purpose. Assuming that the sum bits supplied by ADD2 are designated A0-A9, the PROPAG circuit must in effect add bits S8'-S9' of ADD1 to the word comprised of bits A0-A9 to finally provide bits S8-S17 of 3X.
Referring now to FIG. 4, bit S8 is obtained by means of a simple Exclusive OR Invert circuit 0 which receives as inputs S8' and A0. However, the combination of these inputs will also yield a carry bit if they both have a logical 1 value. This carry bit is therefore obtained by means of an AND circuit, the output of which is fed to the carry input of a full-adder stage FA. The latter, which also receives as input S9' and A1, provides bit S9 and a carry bit C02 which must be allowed to propagate through bits A2-A9. This is done using the carry lookahead technique. A carry generator such as that shown in FIG. 5 is therefore required. This generator is comprised of seven NOR circuits designated N23-N29 which generate carry bits C'3-C'9. The bits shown in the right-hand column of the following table are applied to the respective inputs of N23-N29.
bits S10-S17 are obtained by Exclusive OR'ing bits C02, C'3, C'4, . . . , C'9 and A2, A3, A4, . . . , A9, respectively. Bit S18 is obtained by AND'ing C'9 and A9.
While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims
What is claimed is:
1. Apparatus for generating a three times multiple of a binary number X having orders X.sub.0, X.sub.1, X.sub.2, X.sub.3, X.sub.4 . . . et sequence comprising, in combination, a. a multi-order sum generator which receives as one input signals representative of the orders of said X number X.sub.0, X.sub.1, X.sub.2, X.sub.3, . . . et sequence in corresonding orders of said sum generator to obtain in effect an entry of one times said X number into said sum generator; b. circuit routing means arranged in said sum generator for inputting the signals representative of each order X.sub.0, X.sub.1, X.sub.2, X.sub.3 . . . et sequence of said X number also to the succeeding higher order of said sum generator to obtain in effect an entry of two times said X number into said sum generator; c. a multi-order carry circuit for generating the carry bit for each stage of order k+1 of said sum generator by means of logic circuits providing . . . + X.sub.k.sub.-1. X.sub.k.sub.-3. X.sub.k.sub.-5 . . . X.sub.1) + (X.sub.k. X.sub.K.sub.-2. X.sub.k.sub.-3 + . . . + X.sub.k. X.sub.k.sub.-2. X.sub.k.sub.-4 . . . X.sub.0) where k is any integer n taking on a value from two et sequence, said orders X.sub.0, X.sub.1, X.sub.2, X.sub.3, X.sub.4, . . . et sequence of said input number X also being applied to said carry generator, and wherein for said binary number X a carry signal bit is generated for each order starting at order three et sequence; d. a separate carry generating means included within said sum generator and responsive also to the second order of said X value and the first order of said routed X-Valve to separately generate a carry digit for entry to the third order of said sum generator; e. and means applying each carry signal generated by said multi-order carry circuit as an input to the related order of said sum generator, and any carry signal generated by said separate carry generator for input to said third order of the sum generator, said inputs of said one times said X-value, two times said X-value and the carry signals generating on multi-order outputs of said sum generator, a three times multiple of said binary number X.
2. Apparatus in accordance with claim 1 further characterized in that said multi-order carry circuit utilizes in part NOR logic circuitry comprising, a. a first series of NOR circuits fed by combinatorial orders of said input X-number, and b. a second series of NOR circuits fed by combinatorial outputs of said first series to generate carry digit outputs for input to each successive order of said sum generator starting with the possible carry generated for input to the fourth order.
3. Apparatus in accordance with claim 2 further characterized in that said first series of NOR circuits comprises individual NOR circuit elements having inputs of said order of the number X as follows: NOR Circuit N1 Inputs of ##STR24## N2 ##STR25## N3 ##STR26## N4 ##STR27## N5 ##STR28## N6 ##STR29## N7 ##STR30## N8 ##STR31## N9 ##STR32## N10 ##STR33## N11 ##STR34## N12 ##STR35## N13 ##STR36## N14 ##STR37## N15 ##STR38## N16 ##STR39## ______________________________________ and similarly to a number of NOR circuits equal to twice the number of finite orders of said sum generator and said second series of NOR circuits comprising individual NOR circuit elements having inputs from the outputs of NOR elements of said first series as follows: N1, n2 outputs inputted to a NOR circuit 1' to generate the carry digit C3 for input to the 4th order of said sum generator, N2, n3, n4 outputs inputted to NOR circuit 2' to generate carry digit C4 for input to the 5th order of said sum generator, N3, n4, n5, n6 outputs inputted to NOR circuit 3' to generate the carry digit C5 for input to the 6th order of said sum generator, and so forth for a number of NOR circuits of said second series to generate a final carry sign digit corresponding to the X-factors entered into the highest finite order of said sum generator.
Patent Citations (5)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US2879001 | 1959-03-01 | Weinberger et al. | |
| US2966305 | 1960-12-01 | Rosenberger | |
| US3437801 | 1969-04-01 | Wilhelm, Jr. | |
| US3691359 | 1972-09-01 | Dell et al. | |
| US3919535 | 1975-11-01 | Vattuone |
Non-Patent Literature (2)
- R. K. Richards, Arithmetic Operations in Digital Computers D. Van Nostrand Co., Inc. 1955 pp. 113-114.
- R. L. Haven "Multiplying Circuit" Western Electric Technical Digest No. 26, Apr. 1972 pp. 37-38.