Control Circuit for Controlling the Shaft Speed of a Motor Having Clutch and Brake Devices

1. Field of the Invention

The present invention relates to a control circuit for a motor wherein clutch to brake devices are electromagentically actuated to intermittently connect the motor and a load, thereby controlling the rotating speed of a shaft.

2. Description of the Prior Art

One system for controlling the shaft speed of a clutch motor having clutch and brake devices is disclosed in U.S. Pat. No. 3,599,764. In the shaft speed control system, the operation speed of the drive shaft of a utilization device is maintained at a preselected value by generating a rectified DC signal and a superimposed AC signal when it falls below a reference value, indicating a low shaft speed and causing energization of the clutch for increasing the shaft speed. When the shaft speed becomes greater than selected value, the generated signal exceeds the reference value and is detected by a second solid state switch causing action of the brake until the shaft speed decreases. Alternating pulse-like nonoverlapping actuation of the clutch and brake devices maintains the utilization device drive shaft at the selected speed. The control system, however, forms an AC signal of the shaft speed measuring means into the superimposed AC signal by a rectifier and an R-C element having a predetermined time constant, and therefore involves the disadvantage that the shaft speed cannot be precisely controlled over a wide range from low speeds to high speeds.

An object of this invention is to provide a control circuit for controlling the shaft speed of a motor having clutch and brake devices to control the shaft speed accurately and highly reliably over a wide range of rotating speeds.

In order to accomplish the above object, one preferred embodiment of the invention comprises means to detect the ratio between the actual speed and the desired-speed of a shaft, and means to control the operations of clutch and brake devices in response to the ratio. By controlling the shaft speed in response to the ratio between the actual speed and the desired-speed of the shaft, a precise control circuit can be constructed with comparatively simple logical circuitry.

FIG. 1 is a block diagram of a clutch motor to which a control circuit according to the invention is applied.

FIG. 2 is a circuit diagram of a preferred embodiment of the control circuit according to the invention.

FIGS. 3a-3h are waveforms of input and output signals in various elements of the control circuit according to the invention.

FIGS. 4a-4d are output waveforms for explaining the operation of the control circuit according to the invention.

Shown in FIG. 1 is a block diagram of a clutch motor to which a control circuit according to the invention for controlling a shaft speed of a motor having clutch and brake devices is applied. In general, a clutch motor having clutch and brake devices has a motor 9 for supplying rotating power to a shaft 7, a friction clutch 61, and a friction brake 51. The rotating power of the shaft 7 is transmitted to and is utilized for a utilization device 8, such as machine.

A control circuit 1 for controlling the actuations of the clutch and brake devices receives the outputs of a speed selector 3 for setting a desired-speed, a pulse signal generator 4 which provides a desired-speed pulse signal "a" with a period inversely proportional to the desired-speed of the speed selector, and a speed detector 2 which provides an actual speed pulse signal "b" with a period inversely proportional to the actual rotating speed of the shaft 7.

As apparent from a circuit diagram illustrated in FIG. 2, the control circuit 1 comprises an AND gate 11 which has one input terminal connected to the output terminal "a" of the pulse signal generator 4 and another input terminal connected to the output terminal of the speed detector 2. The output terminal of the AND gate 11 is connected to an input terminal of a counter 12. Output terminals of the counter 12 are connected to input terminals of a latch memory circuit 13 for temporarily storing a count value. The latch memory circuit 13 has five output terminals "f", "g", "h", "i" and "j". Among the five output terminals of the latch memory circuit 13, the four ones and "i" are respectively connected to input terminals of AND gates 141, 142, 143 and 144 of a logical circuit 14. Output terminals of the AND gates 141 and 142 are connected to the input terminal of an amplifier 18, while output terminals of the AND gates 143 and 144 and the remaining output "j" of the latch memory circuit 13 are all connected to the input terminal of an amplifier 19.

Further, the output terminal "b" of the speed detector 2 is connected to two one-shot multivibrators 161 and 162 of an actuating time signal generator 16. The two one-shot multivibrators are triggered by the actual speed pulse signal of the speed detector 2, and respectively provide pulse signals. The time constant of the one-shot multivibrator 161 is shorter than that of the one-shot multivibrator 162.

An output terminal "k" of the one-shot multivibrator 161 of the actuating time signal generator 16 is connected to the other input terminal of the AND gate 141, and is also connected through an inverter to the other input terminal of the AND gate 143. An output terminal "l" of the other one-shot multivibrator 162 is connected to the other input terminal of the AND gate 142, and is also connected through an inverter to the other input terminal of the AND gate 144.

A gate controller 17 has an input terminal which is connected to the output terminal "b" of the speed detector 2, and an output terminal "c" for a signal having a phase difference of 180.degree. from the input signal and an output terminal "d" for a signal being in phase with the input signal. Reference numeral 171 indicates an inverter.

FIGS. 3a - 3h illustrate input and output signal waveforms in various elements of the control circuit. The desired-speed pulse signal of the pulse signal generator 4 is shown in FIG. 3a. The process in which the desired-speed shifts from low speed to high speed is illustrated from the left towards the right as seen in the figure. Similarly, the actual speed pulse signal delivered from the speed detector 2 and having a period inversely proportional to the actual rotating speed of the shaft is shown in FIG. 3b.

The waveform of the output signal "c" of the inverter 171 connected to the other input terminal of the AND gate 11, is shown in FIG. 3c. The AND gate 11 permits the desired-speed pulse signal to pass therethrough only during the time interval during which the signal shown in FIG. 3c is at the level "1". The pulses contained within the desired-speed pulse signal having passed through the AND gate 11 are counted by the counter 12. The resultant count value is temporarily stored in the latch memory circuit 13. The counter 12 and the latch memory circuit 13 are reset by a reset signal at the output terminal "d" of the gate controller 17 which a waveform similar to that shown in FIG. 3b.

In response to the count value, the latch memory circuit 13 provides an output signal at one of the output terminals "f", "g", "h","i" and "j" thereof until the memory circuit 13 is subsequently reset by the reset signal.

The relationships between the count values and the output terminals in the present embodiment are given in the following table 1:

When the output signal appears at the output terminal "f" of the latch memory circuit 13, the AND gate 141 of the logical circuit 14 is enabled, so that the output pulse signal of the one-shot multivibrator 161 is amplified by the amplifier 18 and supplied to a brake coil 5. The waveform of the output pulse signal is shown in FIG. 3d.

When the output signal appears at the output terminal "g" of the latch memory circuit 13, the AND gate 142 of the logical circuit 14 is enabled, and the output signal of the one-shot multivibrator 162 is transmitted to the amplifier 18. The amplified output is supplied to the brake coil 5. FIG. 3e shows the waveform. As is apparent from FIGS. 3d and 3e, the pulse width .tau..sub.k of the one-shot multivibrator 161 is longer than that .tau.l of the one-shot multivibrator 162.

Where the output signal appears at the output terminal "h" of the latch memory circuit 13, the inverted output pulse signal of the one-shot multivibrator 161 as is shown in FIG. 3f is supplied through the amplifier 19 to a clutch coil 6 by way of the AND gate 143.

Similarly, where the output signal appears at the output terminal "i" of the latch memory circuit 13, the inverted output signal of the one-shot multivibrator 162 as is shown in FIG. 3g is supplied through the AND gate 144 to the amplifier 19. The amplified output is supplied to the clutch coil 6.

Where the output signal appears at the output terminal "j" of the latch memory circuit 13, it is directly amplified by the amplifier 19, and the amplified signal is delivered to the clutch coil 6. FIG. 3h shows the output waveform of the amplifier 19 at that time.

FIGS. 4a - 4d illustrate the operation process in which the rotating speed of the shaft 7 actually shifts from a low speed to a desired-speed. FIG. 4a shows a desired-speed pulse signal which has a prescribed period corresponding to a certain desired-speed. FIG. 4b shows an actual speed pulse signal which has a period being inversely proportional to the actual rotating speed of the shaft.

Where the actual rotating speed of the shaft 7 is low, the counter 12 counts fifteen or more pulses of the desired-speed pulse signal during the period of the actual speed pulse signal, as is illustrated in FIG. 4b. The output signal appears at the output terminal "j" of the latch memory circuit 13, a current is caused to continuously flow through the clutch coil 6 as is shown in FIG. 4d, and the clutch device is actuated. Thus, the actual rotating speed of the shaft 7 increases gradually, and the period of the actual speed pulse signal diminishes. Therefore, the number of pulses of the desired-speed pulse signal counted by the counter 12 during the period of the actual speed pulse signal decreases. When the count value becomes fourteen, the output signal appears at the output terminal "i" of the latch memory circuit 13, and current is caused to flow through the clutch coil 6 during a certain time interval. The time interval during which the clutch coil 6 is actuated, i.e., during which current flows through the clutch coil 6, is determined by the pulse widths of the output pulse signals of the one-shot multivibrators 161 and 162 of the actuating time signal generator 16. Further, when the count value reaches twelve, the output signal appears at the output terminal "h" of the latch memory circuit 13, and the period of the current flowing through the clutch coil becomes even shorter (FIG. 4d).

Where the actual rotating speed of the shaft 7 is increased and exceeds the desired-speed by the above operation, that is, where the counter 12 counts eleven pulses of the desired-speed pulse signal during the period of the actual speed pulse signal, the output signal appears at the output terminal p53p"g" g of the latch memory circuit 13. Thus, an output pulse signal of the one-shot multivibrator 162 is provided from the logical circuit 14. During the pulse width of the output pulse signal, current flows through the brake coil and the brake device is maintained actuated (FIG. 4c).

When the brake device is actuated and the actual rotating speed of the shaft becomes lower than the desired-speed, current flows through the clutch coil again so as to accelerate the shaft 7 (refer to the right end of FIG. 4d).

In this way, the clutch operation and the braking operation are repeated, and the desired-speed of the shaft 7 is maintained.