Logic Controlled Charge Transfer Device Transversal Filter Employing Simple Weighting

1. Field of the Invention

The present invention relates to the transversal filter art, and more particularly to a logic controlled transversal filter using charge transfer structures such as charge-coupled-devices or bucket brigade devices.

2. Description of the Prior Art

The use of charge transfer devices for transversal filtering has been taught in the prior art, for example, in the publication "Transversal Filtering Using Charge-Transfer Devices" by Dennis D. Buss, Dean R. Collins, Walter H. Bailey, and C. Richard Reeves, IEEE J. Solid-State Circuits, Vol. SC-8, No. 2 April 1973, pp 138-146. This publication presents techniques for making transversal filters using charge-coupled devices and bucket-brigade devices. In the charge-coupled device transversal filter, the delayed signals are sampled by measuring the current flowing in the clock lines during transfer, and the sampled signals are weighted by a split electrode technique. In the bucket brigade transversal filter, the delayed signals are "tapped" with a source follower whose load determines the weighting coefficient.

The transversal filters described in the cited publication require precise tap weights over a wide range of values which is difficult to achieve using the split electrode described or other known techniques. The transversal filter of the present invention requires only weighting of +1, -1 and 0 and additionally can be programmed, that is, logic controlled.

Another example of an analog filter using charge transfer techniques is U.S. Pat. No. 3,819,958 issued June 25, 1974 to Gosney on an application filed Nov. 3, 1972 and assigned to Texas Instruments, Incorporated. The filter described in the cited patent also requires completed weighting, incorporates the split electrode technique, and is not logic controlled.

In addition, there are copending patent applications assigned to the present assignee which describe certain specific devices and techniques which are incorporated in the present invention. U.S. application Ser. No. 625,425 describes a charge packet replicator, U.S. patent applications Ser. Nos. 662,626 and 670,781 describe charge packet generators, and U.S. patent application Ser. No. 636,862 describes a circuit for injecting charge packets into an input circuit.

An object of the present invention is to provide an improved transversal filter employing charge-transfer structure.

Another object of the present invention is to provide an improved charge transfer transversal filter requiring simple weighting.

A further object of the present invention is to provide an improved charge transfer transversal filter which is controlled by programmed logic.

Still another object of the present invention is to provide an improved charge transfer transversal filter using a charge redistribution circuit to provide a precision divide-by-2 feature.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.

FIG. 1 is a schematic block diagram of a typical transversal filter configuration which is used in a description of the present invention.

FIG. 2 is a schematic block diagram of one embodiment of a charge transfer transversal filter according to the principles of the present invention.

FIG. 3 is a schematic block diagram of an embodiment of a charge transfer register configuration which may be used in the structure of FIG. 2.

A filter can be characterized in the frequency domain(s) by a transfer function H(s) wherein the output V.sub.o (s) is related to the input V.sub.i (s) by the expression

where H represents the sampling coefficient function.

Inverting expression [1] to the time domain (t) results in

or from convolution ##EQU1##

The approximate summation expression [3] can be illustrated by the block diagram of the transversal filter of FIG. 1. As taught in the Buss et al publication, the filter of FIG. 1 can be implemented in charge transfer technology, either by charge-coupled-device or bucket brigade devices. However, as previously stated, techniques employed heretofore require precise tap weights over a wide range of values and they do not offer the ability to logic control the filter.

In the present invention, an embodiment for which is illustrated in FIG. 2, an input circuit 10 is provided including transistors 12, 14, 16 and 18 and capacitors 20, 22, 24 and 26. The input signal v.sub.i is the sampled analog signal. The input circuit 10 generates a sequence of charge packets for each of the sampled input signal values v.sub.i which is represented

From expression [4] it is seen that the first charge packet generated is C.sub.26 v.sub.i divided by a factor of 2. In other applications it may be desired to begin the sequence with the original charge packet C.sub.26 v.sub.i as the first packet of the sequence. The charge packets generated by input circuit 10 are transferred or injected into charge transfer device register 30. The input circuit 10 is fully described in the previously mentioned copending patent application, Ser. No. 670,781. In describing the operation of input circuit 10 herein it is assumed that charge transfer register 10 includes an input or transfer transistor having a control electrode to which a phase pulse (phase 1) is applied having a value V.sub.g. It is also assumed that input circuit 10 and the aforesaid input transfer transistor operate in combination with a conventional phase pulse generator which generates the various pulses phase 1, phase 2, phase 3 etc. which are applied to the control electrodes of its various transistors.

The circuit parameters of input circuit 10 of FIG. 2 can be understood from the following description of the operating cycle. Initially, at time t.sub.o the phase 1 pulse applied to the transfer transistor in CTD register 30 goes on to a d.c. level V.sub.g and remains on. The reset phase applied to transistor 18, phase 2 applied to transistor switch 16 and phase 3 applied to transistor 12 also go on at t.sub.o . The reset phase applied to transistor 18 goes off at t.sub.1 and node 23 charges up to V.sub.g -V.sub.th through the input transistor within CTD register 30 where V.sub.th is the threshold value of input transistor which is operated in saturation.

Phase 2 goes off at t.sub.2 and transistor switch 16 opens thereby isolating the node above capacitor 22 at a voltage v.sub.i. At t.sub.3, phase 3 drops, thereby turning transistor 12 off and phase 4 at transistor 14 turns on thereby discharging the node above capacitor 20 from v.sub.i to ground. At time t.sub.4 the phase 4 pulse goes off thereby isolating the node above capacitor 20 at ground. Phase 2 then goes back on and the charge due to v.sub.i redistributes between the two nodes above capacitors 20 and 22 which means that the node above capacitor 22 is discharged to a level v.sub.i /2 and a packet of associated charge C.sub.26 v.sub.i /2 is injected into CTD register 30. Phase 2 then goes off at time t.sub.5 opening switch 16 and phase 4 goes on again discharging the node above capacitor 20 back to ground through transistor 14. At time t.sub.6 phase 4 at transistor 14 goes off again isolating the node above capacitor 20 at ground and phase 2 goes on closing switch 16 and the charge due to v.sub.i /2 redistributes between the two nodes above capacitors 20 and 22 which means that the node 50 above capacitor 22 is discharged to a level v.sub.i /4 and a packet of charge C.sub.26 v.sub.i /4 is injected into the CTD register 30.

In like manner the input circuit 10 of FIG. 2 can continue to cycle to inject or transfer charge packets of C.sub.26 v.sub.i /8, C.sub.26 v.sub.i /16, C.sub.26 v.sub.i /32 etc into CTD register 30. A feature of the circuit of FIG. 1 is that with capacitance 26 in series with capacitance 22, the resultant capacitance as seen by the CTD register 30 is less than either capacitance 22 or 26. Thus, capacitances 20 and 22 may be large for high accuracy whereas the effective capacitance for the circuit time constant is small permitting fast operation. Of course, other charge generator circuits may be used instead of the specific configuration 10 shown in FIG. 2.

Thus, the sequence [4] generated by input circuit 10 is shifted serially into the charge transfer register 30. Charge transfer register 30 stores a sequence of divided-by-factors of two charge packets representative of an input signal sample. Register 30 is a conventional device and there are many devices in the prior art which can be employed for the structure of register 30. One example of a suitable structure is described in the publication "Charge Coupled 8- Bit Shift Register" by M. F. Tompsett et al in Applied Physics Letters, Vol. 17, 3, p.111, Aug. 1970.

When each sequence of charge packets for each input signal sample is fully contained in register 30, the charge packets are transferred in parallel into a plurality n of charge transfer registers 32-1, 32-2 . . . 32-n wherein each register stores charge packets of the same fractional value for the various samples of the input signal. For example, register 32-3 stores all the charge packets from the input signal samples which have been divided by eight. Thus, the term "same fractional value" is defined herein to mean those charge packets which were divided by the same value even though the resultant value of the "same fractional value" are different.

A significant feature of the present invention is that registers 32-1 through 32-n now contain each input signal sample in the form of a plurality of charge packets in decreasing fractional amounts which may be selectively weighted after each unit of delay with weights of +1, -1, and 0 and the weights of the values in registers 32 summed. The procedure results in a precise implementation of the convolution sum indicated in expression [3].

Thus, by applying weights of "+1", "-1" or "0"; any value of the weights h.sub.m of [3] multiplied by the delay values of v.sub.i (t-mt) in the form of charge can be summed to produce [3]. Therefore, as will be more fully illustrated, precise tapping weights are not required in the present invention, only tapping weights of +1, -1 and 0. The summing of the "+1" and "-1" weights can be implemented by using devices 34, 36 and 38 to perform a parallel replication as described in copending U.S. patent application Ser. No. 625,425 or by using integrating operational amplifiers. It should be clear that expression [3] can be produced by using on "+1" and "-1" weightings without "0" weighting with an inaccuracy comparable to v.sub.i /2.sup.n.

Referring to FIG. 3, a schematic block diagram of an embodiment of a typical one of the CTD registers 32-1 through 32-n is illustrated. Assuming that the input signal v.sub.i is sampled k times, the register of FIG. 3 contains k separate storage cells 40-1, 40-2 . . . 40-k with each storage cell containing a separate one of the charge packets produced by the time sampling and fractional dividing. Each of the storage cells 40-1, 40-2 . . . 40-k is connected to three FET switches 42, 44, 46 and 48, 52, 54, etc up to 56, 58 and 60. Each of the storage cells 40-1, 40-2 . . . 40-k are connected the same, for example, storage cell 40-1 is connected to a "+1" tap through switch 42, to a "-1" tap through switch 44 and to a "0" tap (if used) through switch 46. The FET switches are controlled through the control logic means 62.

Thus, by means of the CTD register illustrated in FIG. 3 used in n positions as shown in FIG. 2, the input signal v.sub.i which has already been both time sampled k times and each time sample fractionally divided by 2.sup.n , each divided time sample can be selectively weighted by a factor "+1", "-1" or "0" and the results combined on the output buses to produce the relationship set forth in expression [3]. No precise weight values are required and the control logic means 62 can be operated by program control so that the filter characteristics can be changed or adapted (i.e. the tap weights can be changed) merely by applying different sets of input instructions to the control logic means 62.

While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.