Methods for Making Transistor Structures

This invention relates to methods for making transistor structures, and more particularly, to methods for making transistors having impurity regions separated by extremely small lateral distances.

Because of its ease of fabrication, the field effect transistor (FET) is finding widespread use in integrated circuit technology. The most common FET is one using source and drain regions on the surface of a silicon wafer separated by a channel region through which current is controlled by a gate electrode overlying the channel region and insulated from it by a thin layer of silicon dioxide. These devices lend themselves to large scale integrated circuit fabrication techniques because all of the source and drain regions can be made by simultaneous impurity diffusions or implantations, and relatively large packing densities can be achieved. One drawback is that their electronic speed of operation is limited by the difficulty of making a short channel over which a gate electrode can be accurately registered.

A device that is structurally related to the FET is the lateral bipolar transistor in which emitter and collector regions on the surface of a wafer are separated by a short base region. The applicability of these devices are limited by the difficulty in making a sufficiently short base region on the surface of the wafer.

I have found that short channel FETs, and bipolar transistors having short base regions, can be made by using an edge of a semiconductor mask as a reference location for defining an extremely short lateral distance. Various techniques will be described by which the edge of a first mask is used to determine a first impurity region, and as a reference location for a second mask, the second mask having a second edge a short lateral distance from the first impurity region. This second edge is then used to define a second impurity region removed a short lateral distance from the first impurity region. The closely spaced impurity regions define a short channel region of an FET or a short base region in a lateral bipolar transistor.

A specific embodiment for implementing this principle is succinctly described in the Abstract of the Disclosure and will not be repeated. A significant consequence of that particular technique is that the gate electrode is inherently accurately registered over the extremely short channel region. Another consequence is that the device is susceptible to mass production and to large scale integrated circuit techniques so that arrays of high speed FETs can be made on a single semiconductor chip.

Other embodiments, objects, features and advantages of the invention will be better understood from a consideration of the following description taken in conjunction with the accompanying drawing.

FIGS. 1 through 3 illustrate an embodiment of the invention.

Referring to FIGS. 1 through 3, a method of making a lateral bipolar transistor in a wafer 60 is illustrated. First a thin oxide layer 61 and a thin metal layer 62 are formed. Next, a thick layer of deposited silicon dioxide 63 having a mask edge 64 is deposited. An ion implantation step using layer 63 as a mask forms an n-type collector region 66. Thereafter, another layer of metal 65 is deposited, as by electroplating, only on the exposed surface of metal layer 62.

Referring to FIG. 3, since layer 65 abutted against silicon dioxide layer 63 it has an edge 64. The silicon dioxide layer 63 and exposed metal layer 62 are selectively dissolved so that the only exposed metal is layer 65. Next, another metal layer 67 is selectively formed on metal layer 65, as by electroplating or by an electroless process. Metal deposited by electrochemical plating forms a layer of uniform thickness, and thus, the edge 68 of layer 67 is displaced a small predictable distance from edge 64. The emitter region 69 is then formed by ion implantation using edge 68 to define its lateral extent. The thickness of metal layer 67 of course defines the distance between emitter 69 and collector 66, and again, this distance may be made very small and with great accuracy. Layer 62 is preferably a very thin layer of tungsten. Layer 65 is preferably electroplated nickel and layer 67 is preferably nickel plated by electroless deposition. Tungsten may be selectively etched by a solution comprising 0.1 molar potassium ferricyanide (K.sub.3 FeCN.sub.6), 0.25 molar KH.sub.2 PO.sub.4 and 0.23 molar KOH.

The foregoing embodiments are to be considered as merely illustrative of the inventive concepts. The various materials and their corresponding etchants are illustrative of various such materials, as are the conductivities and implant processes. Diffusion could be used in certain instances rather than ion implantation and it may be used in conjunction with ion implantation. Various other embodiments and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention.