Apparatus for Generating Display Enabling Signals

A patent entitled "Character Recognition Techniques" bearing U.S. Pat. No. 3,840,856 and granted Oct. 8, 1974 to William Robert Beall et al and assigned to Input Business Machines, Inc. describes and claims a character recognition system upon which the present invention is an improvement.

1. Field of the Invention

This invention relates to a method and apparatus for generating display enabling signals concurrently from the unprocessed and processed data streams of a MICR or OCR character recognition system, and more particularly, to an apparatus that will generate display enabling signals to drive a display system upon receipt of predetermined accumulations or combinations of the unprocessed and processed data streams respectively from the character recognition system.

2. Prior Art

Previous mechanisms having to do with MICR or OCR character recognition systems did not adequately compensate for the relatively high incidence of particularly minimal quality signals being misread or unidentifiably read from encoded documents and thus were passed on as such into the data stream. This resulted in inadequate downstream machine recognition of such minimal quality signals in the data stream that possibly could have been recognized if transformed into a humanly readable format for diagnostic analysis and possible remedial action before being sent further.

Even those systems that may be capable of displaying the data stream as read from the encoded card in a humanly readable format are not adequately capable of allowing any degree of flexibility as to how to key in and capture the misread or unidentifiable signals in the data stream for subsequent display.

Additionally, such systems have lacked reliable means for displaying concurrently the unprocessed and processed data stream of the system representing the input and output respectively of such systems. A related problem of such systems has been the inability to display the unprocessed and processed data streams predeterminably on a real or delay time basis.

It is an object of the invention to employ digital logic in an apparatus for capturing, by use of keys, segments of both the unprocessed and processed data streams from a character recognition system capable of reading MICR or OCR encoded documents for purposes of generating a plurality of display enabling signals operative to drive a display system.

It is another object of the invention to provide programmed signals as keys for comparing with accumulations of the unprocessed data stream for selecting particular portions of the unprocessed data stream to be captured for an indefinite period for specific diagnostic analysis.

It is yet another object of the invention to provide predetermined processed data stream signals comprising combinations of such signals which, upon identifiably keying in thereon, will capture selected special types of information from the unprocessed data stream for an indefinite period, as above, for specific diagnostic analysis.

It is a further object of the invention to provide a capture of a section of the processed data stream precedent to the supra keys for concurrent display for an indefinite period also for specific diagnostic analysis.

It is yet a further object of the invention to provide the capability for concurrent display of the unprocessed and processed data streams from the character recognition system on a real time basis for on going general diagnostic analysis.

In carrying out the objects of the invention, a character recognition system capable of reading and identifying MICR or OCR encoded signals acts as the source of unprocessed and processed data streams to be inputted to the inventive apparatus for generating display enabling signals through the use of keys to a downstream display stream. The apparatus is operative to allow diagnostic display on a downstream display system of both the unprocessed and processed data streams on a real time basis, display of particular portions of the unprocessed data stream precedent to a programmed key, display of special types of data from the unprocessed data stream as precedent to a preselected key in the processed data stream, and concurrent display of the processed data stream precedent to the supra keys.

Various other objects, advantages and meritorious features of the invention will become more fully apparent from the following specification, appended claims and accompanying drawing sheets.

The features of a specific embodiment of the invention are illustrated in the drawings, in which:

FIG. 1 is a block diagram of the prior art character recognition system and the inventive apparatus for generating display signals;

FIG. 2 is a block diagram of the inventive apparatus for generating display enabling signals as illustrated in FIG. 1;

FIG. 3 is a block diagram of the unprocessed data stream display generator illustrated in FIG. 2; and

FIG. 4 is a block diagram of the processed data stream display generator illustrated in FIG. 2.

Referring now to the drawings comprising FIGS. 1 through 5 wherein like component parts are identified by like reference numerals, there is illustrated particularly in FIG. 1 the prior art character recognition system 10 as disclosed in the referenced U.S. Pat. No. 3,840,856 which is used for the purpose of inputting a data stream to the present inventive apparatus 15 for generating display enabling signals to a display system 20. Accordingly, the character recognition system 10 comprises scanner means 25, quantizing means 30, storage means 35, word detecting means 40, sequence detecting means 45, encoding means 50 and error detecting means 55.

The scanning means 25 is in operable communications with a presented character 60 such as an OCR or MICR encoded document and is capable of deriving an array of voltages representative of the configuration of the present character 60. For purposes of describing the illustrated embodiment of the system 10, scanning means 25 will be assumed to be of the optical or OCR type as will be the encoded document 60. The output of scanning means 25 is coupled on line 62 to quantizing means 30. The purpose of the quantizing means 30 is to convert the representative voltage produced by the scanning means 25 to corresponding binary signals. Quantizing means 30 is coupled on line 63 to storage means 35. In addition, stroke thickness compensating means 65 is provided between the quantizing means 30 and the storage means 35 on lines 66 and 67. Stroke thickness compensating means 65 is adapted to compensate for non-uniformities in the presented character 60 that might be deleteriously reproduced by quantizing means 30. Storage means 35 is adapted to store each of the weighted binary signals produced by the multilevel quantizing means 30 to thereby retain field arrays of binary levels, each representing weighted geometric configuration of binary signals that is in approximate conformity with the geometric configuration of presented character 60. The output of storage means 35 on lines 68 and 69 is a serial stream of real time data that could be characterized as an unprocessed data stream. Word detecting means 40 is coupled to storage means 35 on the line 68 and is adapted to examine each discrete area forming each weighted data field geometric configuration to determine if the information content of each examined discrete area is of a predetermined designation. More particularly, the information content of a discrete area is detected as a binary word. The detected binary word is then compared to a plurality of stored predetermined binary words in word storage means 70 on line 71. A favorable comparison therebetween results in a characterization of said detected binary word as one of said predetermined words.

Sequence detecting means 45 is coupled to word detecting means 40 on line 72 and is capable of sensing the order in which each binary word is identified by word detecting means 40. The sequence detecting means 45 is capable of storing a plurality of known sequences, each representing an alphanumeric character of a known type. As each binary word stored in storage means 35 is identified as being one of a predetermined plurality of binary words, the sequence of identified words is compared to each of the stored known sequences. A favorable comparision between a derived sequence and one of the known sequences results in an identification of presented character 60 as being the alphanumeric character associated with the known sequence. In addition to the compared character being outputted on line 80, a command signal indicating that a comparison has been made will be separately outputted on line 73 representing that a compared character as represented by the processed data stream may be available at this exact interval of time. The sequence detecting means 45 is additionally coupled to character positioning means 75 on line 76, the latter being coupled to storage means 35 on line 77. Character positioning means 75 is particularly adapted to sense when the arrays of binary signals serially supplied to storage means 35 are centered therein such that the weighted data field geometric configurations are properly positioned within the storage means 35. When so weighted, the character positioning means 75 applies an enabling signal on lines 76 and 78 to the sequence determining means 45. The sequence detecting means 45 is thus inhibited from recognizing a derived sequence of identified binary words during that period when invalid word identification might occur. The character positioning means 75 thus outputs two types of command signals, one a signal that the character or unprocessed data stream is centered on lines 76 and 78 and the other being a signal on line 79 indicating a period in which characters or the unprocessed data stream may occur.

To provide a translation from the high level human-like intelligible language, outputted by the sequence detector means 45 to a low level machine-like language, an encoder means 50 is provided to be coupled on line 80 to the sequence detector means 45. Encoding means 50 may comprise a conventional coding device capable of producing a unique binary coded signal for each of a plurality of input signals, supplied thereto. The unique binary coded signals comprising data identifiers or a processed data stream outputted in parallel form on line 81 by the encoding means 50 may be used to drive the downstream machine system that it was designed for and additionally the present inventive apparatus 15. Error detecting means 55 is coupled on line 81 to the output of sequence detecting means 45 and is adapted to prevent the erroneous identification of presented character 60 as being more than one predetermined type of alphanumeric character. The error detecting means 55 is further capable of detecting when the presented character 60 does not correspond to any of the known types of alphanumeric characters and, therefore, cannot be positively identified. The one of the outputs of error detecting means 55 is coupled on line 82' to a disable input of encoding means 50 to prevent the encoding means 50 from transmitting a binary coded signal representative of an erroneous character. An additional output on line 82 of the error detecting means 55 represents all the combinations of the processed data stream for which it has been predetermined that diagnosis shall be needed upon the occurrence of such combinations. The predetermined combinations may be created by hard or jumper wiring the error detecting means 55.

The inventive apparatus 15 itself is disposed to operate in either a real time or a delay time state. In the real time state using the unprocessed data stream display generator 84 of the apparatus 15, the unprocessed data stream on line 69 from the storage means 35 of the character recognition system 10 is allowed to flow relatively unimpaired, in turn, through a first data select module 83 in the apparatus 15, a delay line module 85 in the apparatus 15 on line 86 and finally on line 87 to its own video channel in a separate display stream 20. Concurrently, in the real time state using the processed data system display generator 88 of the apparatus 15, all of the processed data stream from the encoder means 50 of the character recognition system 10 on parallel lines 81 is routed, in turn, to a second data select module 90 in the apparatus 15, a data identifier storage module 95 in the apparatus 15 on line 96, a data identifier translator module 100 in the apparatus 15 on line 101, and again finally on line 105 to its own video channel of the above commonly shared display system 20. The display system 20 may include such components as a common oscilloscope having multichannel video inputs, control generators (not shown), and a display device such as a cathode ray tube (not shown) for concurrent display of the unprocessed and processed data streams.

In the delay time state it may be desired to display selected sections of the unprocessed and processed data streams indefinitely. Control, in this state, may be had either by hardware or software modes. Using the hardware mode, the error detecting means 55 in the character recognition system 10 may be hard or jumper wired to recognize preselected combinations of the processed data stream as keys and channels off the keyed combinations on line 82 to a separate input of the first data select module 83 in the apparatus 15. The keyed combination will enable the first data select module 83 in the apparatus 15 to order the delay line module 85 in the apparatus 15 to feedback on itself and thus capture special types of the unprocessed data stream precedent to that keyed combination which will usually be back to the start of an encoded print line as read by the scanner means 25 of the character recognition system 10. All of the unprocessed data stream subsequent to the keyed combinations will be excluded thereafter as long as that mode is operative. The captured special types of the unprocessed data stream will then be inputted to the downstream display system 20 on line 87.

In the software mode, a particular portion of the unprocessed data stream may be chosen for display by programming a key signal in an operator control module 110 in the apparatus 15 to be outputted on lines 111 and 112. The unprocessed data stream on line 69 from the store means of the character recognition system 10 may be fed into the first data select module 83 in the apparatus 15 for stored accumulation and comparison to the programmed key signal. When a true comparison is made, the delay line module 85 in the apparatus 15 is again enabled to feedback on itself and send on line 87 the captured particular portion of the unprocessed data stream to the display system 20 as before.

In both the hardware and software modes of the delay time state, all of the processed data stream contained in the section informationally equivalent to the captured unprocessed data stream and precedent to one of the supra keys may be displayed concurrently with the above mentioned captured particular portions or special types of the unprocessed data stream on the display system 20 which as indicated supra has multichannel inputs. This is accomplished by allowing the first data select module 83 in the apparatus 15 as enabled by its output signal on line 86 to the delay line module 85 in the apparatus 15 to arm a control circuit module 115 in the apparatus 15. The armed control circuit module 115 will be operative to preclude, on line 120, the second data select module 90 in the apparatus 15 from receiving subsequent sections of the processed data stream on line 81 from encoder means 50 of the character recognition system 10. As such, the control circuit module 115 in the apparatus 15 will then via control line 125 only allow sections of the processed data stream already residing in the data identifier storage module 95 in the apparatus 15 to be inputted back into itself and thus be captured. The captured section of the processed data stream is then fed on line 101, as in the real time state, to the data identifier translator module 100 in the apparatus 15 and then, as before, on line 105 to the display system 20.

Specifically describing the unprocessed data stream display generator 84 of the apparatus 15 illustrated generally in FIG. 2 and particularly in FIG. 3, the processed data stream on line 69 from store means 35 has its polarity reversed by an inverter 130 in the first data select module 83 before being sent on line 86 to the dynamic shift register 135 in the delay line module 85. The dynamic shift register (dym. S.R.) 135 in the real time state is operative to storably slow the travel of the unprocessed data stream as it inputs to terminal I and outputs at terminal 0 at a rate determined by the number of stages in the register 135 and the clock rate applied by a clock (not shown) on line 140 to terminal C1 of the register 135. In the delay time state when the C2 terminal is enabled by a signal on line 145 from the first data select module 83, the register 135 will continue to output as before from terminal 0 on line 87, as a video signal to a first channel input in the display system 20 but will cease to receive new input at terminal I and will only recycle the data aready stored in the register 135. The preferred dynamic shift register 135 is a National Semiconductor Corp. model MM1404.

The delay time state in the unprocessed data stream display generator 84 is made operable when it is desired to capture a section of the unprocessed data stream. The capture is made upon occurrence of a preselected key to thus enable the captured section to be displayed indefinitely. Such a capture may be made in either a hardware or software mode designating an automatic (auto) or manual (man) response, respectively. The hardware mode may be had by wiring the error detection module 55 to respond to preselected combinations of the processed data stream to automatically output, upon the occurrence thereof, an error or key signal on line 82 to a NAND gate 150 in the first data select module 83. This presupposes that a grounded SPST on-off switch 155 is disposed "on" and will output on lines 160 and 165 and particularly on line 160 to AND gate 170. As will be seen infra, when switch 155 is "on" or "off," the delay or real time state is enabled, respectively. AND gate 170 will be true when inputted to by supra line 160 and also line 175 from a grounded SPDT mode select switch 180 when disposed in its "auto" position where the "auto" and "man" positions are mutually exclusive. The true AND gate 170 will output on line 185 to NAND gate 150. Gate 150 will, in turn, output on line 190 when both lines 185 and 82 input thereto. NOR gate 200 will output on line 145 when receiving an ouput from either of lines 190 and 195. A signal on line 145 to the dynamic shift register 135 will, as mentioned supra, cause the register 135 to recycle back on itself thus causing a fixed display in the hardware mode of the delay time state. The true effect of such recycling is to give all the information for diagnostic purposes back to at least as far as the last start of line of characters such as a print line, or other arbitrary predetermined segmentation as read and identified by the character recognition system 15.

In the software mode of the delay time state of the unprocessed data stream display generator 84, the key signal may be programmed in manually to preselect the section of the unprocessed data stream to be captured and displayed indefinitely. This mode is initialized by again turning "on" the switch 155, setting mode switch 180 to "man" to output on line 201 thus enabling AND gate 202 to output on line 203 to NAND gate 204. The pair of sets of grounded programming switches PS-1 (205) and PS-2 (210) are set, according to a preselected code, to give a key signal collectively on sets of lines 215 and 220 representative of an accumulation of data from the unprocessed data stream from the beginning of a line to a preselected key in point on the line. The accumulation, to which the key signal on lines 215 and 220 is to be compared, is generated by using the command centering signal on line 78 from the character positioning means 75 as an incremental trigger. The signal on line 78 to inverter 225 is then bifurcated on lines 230 and 235 to the J input terminal of flip flop (FF) 240 and inverter 245, respectively. Then through line 250, the inverter 245 feeds the K input terminal of flip flop 240. The flip flops 240 and 255 are regular J-K flip flops. The output terminals Q--Q of flip flop 240 serially feed the J-K input terminals of flip flop 255 on lines 260 and 265, respectively. The Q output terminal and Q output terminal of flip flops 240 and 255 are then fed on lines 270 and 275, respectively, to AND gate 280 which will output upon the concurrent receipt thereof on line 285.

For clock triggering purposes, a signal from a clock (not shown) is sent on line 290 to inverter 295 where it is bifurcated on lines 300 and 305. The clock signal travels on line 305 through inverter 310 and is then outputted trifurcated on lines 315, 320 and 325. Lines 315 and 320 input to the C or clocking terminals of flip flops 240 and 255, respectively. Line 325 proceeds to the display system 20 to be used as clocking input for the first channel video signal on line 87 to the display unit 20 from the delay line module 85. Inputting to the first data select module 83 is a signal on line 79 from the character positioning means 75, as indicated supra, indicates a period when signals representative of the unprocessed data stream may occur or more specifically when a period is occurring when a line of characters may actually be in the process of being read. The negation of this is the relatively short period when no characters are being read or the unprocessed data stream does not occur. The line 79 is inverted by inverter 330 to achieve the supra mentioned negation and proceeds on line 335 to the R or reset terminals of flip flops 240 and 255, and additionally to first and second counters 340 and 345. The preferred counter to be used each for 340 and 345 is a Texas Instrument model 74161. Incrementing signals are sent on line 285 to the input "I" terminal of counters 340 and 345. Counter 340 increments counter 345 via line 350. The counters 340 and 345 are clocked on supra mentioned line 305. Each stage of each of the counters 340 and 345 is sampled and sent in parallel fashion by sets of lines 355 and 360 to first and second comparators 365 and 370, respectively. The preferred comparators 365 and 370 are each Texas Instrument model 7485. The parallel inputs of the first and second comparators 365 and 370 sample the paired sets of lines "215 and 355" and "220 and 360", respectively. When a compare is made, the serial Q output terminals of comparators 365 and 370 proceed on lines 375 and 380, respectively, to NAND gate 385 which upon the concurrent receipt thereof proceeds on line 390 to inverter 395. The signal from the inverter 395 is then sent on line 400 to the supra mentioned NAND gate 204.

The incrementing operation in the software mode of the delay time state proceeds by inputting the supra mentioned unprocessed data stream on line 78 from the character position means 75 to the flip flops 240 and 255 which act to synchronize the unprocessed data stream to the flip flop clock rate given on lines 315 and 320. When simultaneously clocked and inputted thereto, the flip flops 240 and 255 will always be in opposite stages. The flip flop circuit described supra of which flip flops 240 and 255 is a part of a common circuit and is shown and described on pages 79 and 80 under the subheading of shift registers in a book titled "Computer Data Handling Cicuits" by Alfred Corbin and was published in 1971 by Thomas Sam Publications. Once the unprocessed data stream is so synchronized, it may proceed through lines 270 and 275 to AND gate 280 to be outputted on line 285 to counters 340 and 345 which share the same clock and thus may be used to synchronously increment the counters 340 and 345. Counters 340 and 345 each count to nine with the first counter 340 being serially connected to the second counter 345 thus enabling the counters to incrementally count to a maximum two digit number of 99. Once the counters 340 and 345 have been reset by a no read signal on line 79, and additionally the switches PS-1 (205) and PS-2 (210) have been set for a key signal anywhere between zero and the maximum two digit number, the comparators 365 and 370 will continuously compare the incrementing counters 340 and 345 to the switches 205 and 210 until each of the comparators 365 and 370 registers a true compare at their output Q terminals as sensed by NAND gate 385. The true compare signal will be sent on line 145 to the delay line module 85 to recycle the stored unprocessed data stream as was done supra in the hardware mode of the delay time state.

In the real time state of the processed data stream display generator 88 of the apparatus 15 as shown in FIG. 4, the processed data stream or data identifiers on the parallel set of lines 81 from the encoder means 50 are inputted through inverters 405, 410, 415 and 420 to a routing multiplexer (mux) 425 in the second data select module 90. The preferred multiplexer 425 is a Texas Instrument model 74157. From there, the signal is channeled via set of lines 96 to a storage shift register (SR) 430 in the data identifier storage module 95. The preferred shift register 430 is a Texas Instrument model 3341. The signals, in turn, are directed via set of lines 435 to an interface counter 440 also in module 95. The preferred counter 440 is a Texas Instrument model 74161. Next, the signals are sent through set of lines 101 to the inputs of a read only memory (ROM) 445 in the data identifier translator module 100. The preferred ROM 445 is a National Semiconductor Corp. model 1702A. Then the signals are inputted on line set 450 to a "parallel to serial" shift register 455. The preferred shift register 455 is a Texas Instrument model 74165. The serial output of the shift register 455 is sent on line 105 as a video signal to a second channel input in the display system 20. The result of the supra state is to give a real time display of the processed data stream as it leaves the character recognition system 10.

The clocking circuit for the supra processed data stream display generator 88 comprises a clock (not shown) outputting a signal on line 460 to an inverter 465 in the second data select module 90. The inverter 465 outputs on trifurcated lines 470, 475, and 477. The clock signal on line 475 inputs to a clock terminal C of a time generator 480 in a second control circuit 485. The preferred time generator 480 is a counter made by Texas Instrument model 74161. The time generator 480 provides a relatively slower clock rate to synchronize the interface counter 440 and an address counter 487 as to each other when they interact on parallel line sets 101 and 488, respectively, with the ROM 445 as will be seen infra. The preferred counter 487 is a Texas Instrument model 74161. The time generator 480 trifurcatably outputs on lines 490, 495 and 500, an inverter 505, to an AND gate 510 in the data identifier storage module 95, and to a clocking input for the second channel video signal of line 105, respectively. The AND gate 510 is also adapted to receive an input from the supra clocking line 470.

As mentioned supra, the time generator 480 acts to synchronize via bifurcated clocking lines 512 and 513 both from inverter 505, the interface counter 440 and the address counter 487 respectively as to each other and delayably synchronize as to the other modules in the apparatus 15. The interface counter 440 is a device for generating a variable relative address through its count cycle dependent on the parallel input initializing by the storage shift register 430 per any given line of print being read corresponding to an arbitrary segmentation between system resets as will be seen infra. The address counter 487, on the other hand, is a device for generating a fixed relative address through a count cycle with a constant initialization. The combined variable and fixed relative addresses generated by counters 440 and 487, respectively, are operative to uniquely access the ROM 445 so as to output on line set 450 to the "parallel to serial" shift register 455 which is synchronously clocked on supra line 477 at the same synchronized rate as the address generator 487. The address counter 487 is further operative to give a synchronized pulse at the end of each count cycle through its serial output 0 on bifurcated lines 515 and 517 to a NAND gate 520 and also the AND gate 510, respectively. The NAND gate 520 is also adapted to receive an input on line 525 from the output read (OR) terminal of the storage shift register 430. The output ready terminal will output whenever the shift register 430 detects stored data therewithin. Concurrent receipt of signals at its inputs by the NAND gate 520 will enable an output signal to be sent on bifurcated lines 530 and 535 to the K terminal of the interface counter 440 and an inverter 540, respectively. Receipt of a signal at the K terminal of the interface counter 440 will enable the counter 440 to receive signals at its inputs.

The apparatus 15 is operative to have a scanner type mode selection circuit in the data identifier translator module 100 for flexible manual switching into either an OCR or MICR reader environment at will. This is accomplished through a grounded SPDT switch 545 operative to select OCR in its high state or MICR in its low state and thus output on lines 550 or 555 to AND gates 560 to 565, respectively. The gates 560 and 565 are in a ready condition whenever a control signal is outputted on line 570 from the high parallel stage output terminal Q3 of the interface counter 440. The Q3 terminal is enabled whenever there is data incrementing the counter 440. Once either the AND gate 560 or 565 is put into a true state, a signal on line 575 or 580 will be sent to the A7 or A6 input terminals of the ROM 445 to condition it accordingly to an OCR or MICR state, respectively.

The first control circuit module 115 enables the delay time state for the Processed Data Stream Display Generator 88 and also disables delay time state for real time operation as desired. In the real time state, an "off" signal indicating no delay time from switch 155 in the operator control module 110 is sent via line 590 to a stop latch circuit comprising cross connected NOR gates 595 and 600 which act to disable the stop latch. When so disabled, a signal will be sent to NAND gate 605 on line 603. The supra described signal indicating a period or read interval in which characters or data in the processed data stream may occur is inputted on line 79 to an inverter 610 which in turn bifurcatably outputs on lines 615 and 620 to the J terminal of a conventional J-K flip flop 625 and an inverter 625, respectively. The inverter 625, in turn, outputs on line 630 to the K terminal of flip flop 625. Flip flop 625 is serially connected through its outputs on lines 635 and 640 to the inputs of another J-K flip flop 645.

The flip flops 625 and 645 are both clocked by a clock (not shown) on bifurcated line 650 and 655, respectively. As before in the previous flip flop circuit of 240 and 255, when not inputted to, the flip flops 625 and 645 will both clock down to their low states. When regularly clocked, the flip flops 625 and 645 will alternately be in opposite states, but unlike as before, the input to the flip flops 625 and 645 does not regularly alternate, but rather once on, stays on for a relatively long period corresponding to that interval of time in which characters or the processed data stream as read may be available. As such, once an input signal is applied to the flip flops 625 and 645, they will go from both being low to the first 625 being high and the second 645 being low, to finally both being high for the duration of the period of the signal on line 79 after which both flip flops 625 and 645 will be affirmatively reset to low or with the absence of input they will de-facto both be clocked back to a low state.

In a typical operative case in the real time state of the Processed Data Stream Display Generator 88 where both flip flops 625 and 645 are initially low, signals will be sent by low flip flop 645 on bifurcated lines 660 and 665 to the NAND gate 605 and also a NAND gate 670. Subsequently, when the stop latch 595 and 660 is disabled by a signal on line 590 from operator control 110, it may be assumed that a real time state is affirmatively desired. Gate 605 will thus remain false for the interim and will not reset the flip flops 625 and 645 through line 675. Instead, when a signal appears on supra described line 79 indicating a character available period, the flip flops 625 and 645 will begin to increment with flip flop 625 high and flip flop 645 low after the first clock. This will set gate 670 true through lines 680 and 665 to output on line 685 to reset the storage shift register 430 to zero for the new line of read characters coming in representing the processed data stream. The next clock pulse puts both flip flops 625 and 645 high. At this point, it is assumed that there is a signal coming in on line 73 through inverter 690 and out on bifurcated lines 695 and 700 to gates 705 and 710, respectively, representing that a compared character may be available at this precise interval as described supra.

With flip flop 645 outputting high on bifurcated lines 715 and 720 to NAND gate 710 and routing multiplexer 425, respectively, gate 710 will be made true and multiplexer 425 will be directed to receive new processed data stream input, and not feedback old input on line set 725 from output line set 435. When gate 710 is true, it will output on line 730 to NOR gate 735 and out on line 740 to the shift input (SI) of the storage shift register 430 thus enabling the register 435 to receive input from multiplexer 425 on line set 96. Once the period of the signal on line 79 expires indicating an end of line or termination of a character availability period, the flip flops 625 and 645 will clock themselves low again. With the flip flops 625 and 645 low, gates 690 and 510 will begin to be clocked true through lines 745 and 470-517-495 to output on lines 750 and 755 to shift-in and shift-out out respectively of the register 430.

When a delay time state in the Processed Data Stream Display Generator 88 is operatively desired, a signal on line 145 from the first data select module 83 is received and sent through inverter 760 and out on line 765 to NAND gate 770 and then on line 775 to the stop latch 595 and 600. This enables the stop latch 595 and 600 which, in turn, sends a signal to gate 605. At this point, all operative action will cease until the end of the read line is reached and the signal on line 79 is removed thus enabling flip flops 625 and 645 to begin clocking down. Once this occurs and after the first clock thereafter, flip flop 625 will be low and flip flop 645 high. This will enable gate 510 to be clocked true thus enabling storage shift register 430 to output again. Gates 690 and 735 will be clocked true thus enabling the storage shift register 430 to also again input. The subsequent clock to the flip flops 625 and 645 will place them both in a low state. This will set gate 605 true and thus lock the flip flops 625 and 645 into a low state reset condition immune to any further input on line 79 until stop latch 595 and 600 is again disabled by a signal from operator control 110 on line 590. Until such disabling, the delay time state will continue to allow the storage shift register 430 to feedback on itself and thus display the stored or captured read line of the processed data stream or data identifiers indefinitely.

While the above referenced embodiments of the invention have been described in considerable detail, it will be appreciated that other modifications and variations therein may be made by those skilled in the art without departing from the true spirit and scope of the invention.