FM Multiplex Demodulator Circuit

1. Field of the Invention

This invention relates to an FM multiplex demodulator circuit. More particularly, it is directed to an FM multiplex demodulator circuit which is constructed into a semiconductor integrated circuit.

2. Description of the Prior Art

Although the PLL(phase locked loop) technique is conventional, because of the need for a complicated circuit arrangement and a high cost, its fields of utilization have been restricted to measuring instruments, space communications, etc.

With the progress and development of semiconductor integrated circuit technology, the fields of utilization have been expanded.

As an example, a double balance type synchronous detection circuit employed in an FM multiplex demodulator circuit has been developed. This circuit and a semiconductor integrated circuit are inseparable. The FM multiplex demodulator circuit formed as a semiconductor integrated circuit has heretofore acquired signal outputs of a right channel and a left channel by passing outputs of the synchronous detection circuit through an LPF (low-pass filter) as an externally-mounted circuit.

In a differential circuit which constitutes the synchronous detection circuit, in order to make the number of externally-mounted pins small and to realize de-emphasis, a load resistance determining the gain of the differential circuit has been formed by an externally-mounted resistance and it has been impossible to make the value of the resistance large.

Therefore, the following problems are involved:

1. The obtainable detection output is only several tens of mV-500 mV or so. Since the detection output is small, an amplifier circuit is required separately from the FM multiplex demodulator circuit constructed into the semiconductor integrated circuit device.

2. Since the load of the detection circuit is the externally-mounted resistance, the gain of this circuit is determined by the ratio between the externally-mounted resistance and an internal resistance (a resistance formed within the semiconductor integrated circuit). The dispersion of the values of the internal resistances is as large as .+-.30 to 50% or so with respect to a design value, so that the gains are largely dispersed.

3. The LPF (low-pass filter) has a low input impedance, so that its impedance matching with the detection circuit cannot be established. Where the LPF and the detection circuit are directly coupled, the intrinsic characteristic of the LPF cannot be attained.

This invention has been made in order to solve the above problems, and has for its objects (1) to enlarge the detection output, (2) to reduce the dispersion of the detection outputs and (3) to establish impedance matching between the LPF and the detection circuit, without increasing the number of pins in the FM multiplex demodulator circuit constructed into a semiconductor integrated circuit.

The fundamental construction of this invention for accomplishing the objects resides in an FM multiplex demodulator circuit constructed into a semiconductor integrated circuit, which employs, within a semiconductor integrated circuit, at least a double balance type synchronous detection circuit which includes load elements formed within the semiconductor integrated circuit, a pair of negative feedback type differential amplifier circuits which amplify a pair of detection outputs from the detection circuit and also perform de-emphasis thereof, respectively, and a pair of feedback circuits which include low output impedances connected to outputs of the negative feedback type differential amplifier circuits, respectively.

The single FIGURE is a circuit diagram showing an embodiment of this invention.

A double balance type synchronous detection circuit composed of transistors Q.sub.1 - Q.sub.6 and resistances R.sub.1 - R.sub.6 has its load resistances R.sub.1 and R.sub.2 formed within a semiconductor integrated circuit IC indicated by a broken line in the FIGURE. Detection outputs of the detector circuit are respectively amplified by negative feedback type differential amplifier circuits formed within the semiconductor integrated circuit, and are delivered through emitter follower output circuits to output pins 3 and 5. More specifically, a subcarrier signal V.sub.REF (38 kHz) which is formed from a pilot signal (19 kHz) in an FM stereo composite signal received is applied between the base of the transistor Q.sub.3 (and Q.sub.6) and the base of the transistor Q.sub.4 (and Q.sub.5) of the double balance type synchronous detection circuit. On the other hand, the composite signal is applied to the bases of the transistors Q.sub.1 and Q.sub.2. Thus, a right channel detection output is obtained at an output O.sub.1 of the synchronous detection circuit, while a left channel detection output is acquired at an output O.sub.2. The right channel detection output is amplified by a differential amplifier circuit which is composed of transistors Q.sub.7, Q.sub.8, and Q.sub.10 and diode Q.sub.9, resistances R.sub.7 and R.sub.8 and a constant-current load I.sub.01, and it is delivered as an output through an emitter follower circuit which is composed of a transistor Q.sub.11 and a constant-current load I.sub.02. The left channel detection is amplified by a differential amplifier circuit which is composed of transistors Q.sub.12, Q.sub.13 and Q.sub.15 and diode Q.sub.14, resistances R.sub.9 and R.sub.10 and a constant-current load I.sub.03, and it is delivered as an output through an emitter follower circuit which is composed of a transistor Q.sub.16 and a constant-current load I.sub.04.

An externally-mounted pin 1 is a power supply terminal, and pins 2 and 4 are feedback terminals of the differential amplifier circuits, respectively.

Resistances R.sub.11, R.sub.12 (R.sub.14, R.sub.15) which are externally mounted on the power supply terminal 1, the feedback terminal 2 (4) and the output terminals 3 (5) are d.c. bias resistances. A capacitor C.sub.2 (C.sub.4) is a de-emphasis capacitor. A series circuit consisting of a resistance R.sub.13 (R.sub.16) and a capacitor C.sub.1 (C.sub.3) forms an a.c. feedback circuit.

In accordance with the invention, its objects can be achieved on the following ground:

First, since the detection output is amplified by the amplifier circuit formed within the same semiconductor integrated circuit, a large detection output is obtained. The gain of the detection circuit is determined by the ratio between the values of the resistance elements formed within the semiconductor integrated circuit, and the dispersion of the resistance ratios is small, so that the dispersion of the detection outputs can be made small.

Further, since the output circuit is constructed of an emitter follower circuit of low output impedance, impedance matching of the output circuit with the LPF of low impedance can be established, and the output circuit and the LPF can be directly coupled. Thus, the intrinsic characteristic of the LPF can be maintained.

The output terminal serves also for the terminal with which the de-emphasis circuit is to be connected, so that the number of externally-mounted pins does not increase.

Another advantage of the invention is that the constants of the de-emphasis circuit can be freely selected without considering the gain of the detection circuit. Still another advantage is that, by additionally providing a variable resistance R.sub.16 between the feedback terminals 2 and 4 of the negative feedback type differential amplifier circuits which amplify the detection outputs of the right channel and the left channel respectively, the separation control between both the channels can be effected very simply.

More specifically, due to the connection of the resistance R.sub.16, e.g. the right-side, output R is attenuated and is applied to the base of the transistor Q.sub.13 constituting the left-side differential amplifier circuit. On the other hand, even when the left-side detection output L and a right-side leakage signal component .DELTA.R are applied to the base of the transistor Q.sub.12, the right-side signals are applied to the bases of the differential pair transistors Q.sub.12 and Q.sub.13 in phase at this time. Therefore, by adjusting the right-side attenuation signal level, which is impressed on the base of the transistor Q.sub.13, so as to become equal to the leakage signal .DELTA.R by means of the resistance R.sub.16, only the left-side output L is obtained at the collector of the transistor Q.sub.13, and excellent separation between both the channels can be obtained. This technical result is similarly achieved for the separation of the right-side output R. The same result is attained when the resistance R.sub.16 for the separation is connected between the output terminals 3 and 5.

This invention is not restricted to the foregoing embodiment, but it can adopt various aspects of performance.

By way of example, the emitter resistances R.sub.7, R.sub.8 and R.sub.9, R.sub.10 of the negative feedback type amplifier circuits may be omitted. The constant-current circuits I.sub.02 and I.sub.04 of the output circuits may be mere resistances. Further, the output circuit may be made a push-pull circuit or an n-p-n differential amplifier circuit by subjecting the detection output to a level shift by means of a p-n-p transistor.