Interface for Establishing Communications Between a Data-Processing Unit and a Plurality of Stations

The present invention relates to an interface for connecting a data-processing unit to a group of m working stations including items of data emitting and receiving apparatus.

Exchanges of data between a data-processing unit and working stations generally take place via cable connections. In a known method of connection, termed star connection, each of the items of apparatus at a working station is connected to the unit by a cable associated with it. Such a connection does away with the necessity for an addressing circuit to be fitted to each item of apparatus and, by the use of standardized plugs and sockets, allows the user to make up the working station to suit his needs. However, star connections make it necessary for any given working station to have as many cables as there are items of apparatus at the station and require wiring done at the time of installation to be such as to indicate to the data-processing unit which socket corresponds to which item of apparatus. Also, since the input/output management capabilities of the data-processing unit are limited, the number of items of apparatus which can be connected must remain limited if the design of the unit is not to become excessively complicated.

The exchange of data between a processing unit and an apparatus is the responsibility of a pair of data transmitting and receiving circuits which are situated at respective ends of the cable connecting the apparatus to the unit. If the number of items of apparatus is high, the number of transmitter/receiver circuits is correspondingly greater. Because the plugs and sockets are standardized at the end of the cable connected to the unit, it is necessary when a working station is brought into operation to indicate to the unit the type of apparatus which is connected to the concerned plug. Type should be understood to cover not only the general type of peripheral at the apparatus (keyboard, display screen, ETC.) but also sub-types within a given type; for example whether a keyboard is digital or alpha-numeric. Each item of apparatus must therefore include a circuit to allow it to recognize a type query from the unit and to reply by transmitting to the unit an indication of its type. While star connections theoretically allow the unit to operate simultaneously with the various different items of apparatus connected to it, this possibility is not usually available because of the sequential nature of addressing software which the unit employs to establish a communication link with the items of apparatus at one and the same working station.

One of the objects of the present invention is to provide an interface for connecting a data-processing unit to a plurality of working stations, which interface has a small number of data transmission channels and transmitter/receiver circuits, thus reducing its manufacturing costs in comparison with known interfaces.

Another object of the invention is to provide apparatus that can be removed from or added to a working station without the necessity of increasing or removing circuits at the inputs and outputs of the unit at the time of installation.

Another object of the invention is to provide a new and improved interface between a data processing unit and a number of working stations, which interface allows a large number of items of apparatus to be provided at the same working station.

Another object of the invention is to provide a new and improved interface between a data processing unit and a number of working stations, wherein connections to a transmission means are more readily established than those used in the prior art, such as the star connection.

Another object of the invention is to provide reliable apparatus for exchanging data between a data-processing unit and items of apparatus at stations which are connected to the unit.

According to the invention, there is provided an interface for connecting a data-processing unit to a group of m working stations made up of items of data emitting and receiving apparatus. The unit and each of the items of apparatus are designed to transmit and receive binary data in parallel, character by character, as a result of control signals generated in the unit. The interface contains m transmitter/receiver circuits, one of which is associated with each of the m stations. At each of the stations, a separate transmitter/receiver circuit is associated with each item of apparatus. Each transmitter/receiver circuit is designed to convert a received, input parallel character having a predetermined number of simultaneously occurring bits, into a series character, the constituent bits of which are transmitted in succession by an output to a first transmission line of a channel for connecting a station transmitter/receiver circuit and the apparatus transmitter/receiver circuits at that station together. Each transmitter/receiver circuit also converts the bits forming an input series character, i.e., bits which are successively received by an input of the circuit from a second transmission line of a channel into a parallel character having a number of simultaneously occurring bits corresponding to the number of serial bits in a series character fed to the circuit. The data processing unit supplies parallel characters to the parallel inputs and is responsive to the parallel character outputs of the transmitter/receiver circuits associated with the m stations. Each item of apparatus supplies parallel characters to the parallel inputs and is responsive to the parallel characters outputs of the transmitter/receiver circuit associated with it.

The above and still further object, features and advantages of the present invention will become apparent upon consideration of the following detailed description of one specific embodiment thereof, especially when taken in conjunction with the accompanying drawing.

FIG. 1 is a general diagram of a system wherein a data processing unit is connected to a plurality of stations by a connecting interface according to the invention;

FIG. 2 is a diagram wherein there are illustrated greater details of the connecting interface shown in FIG. 1;

FIG. 3 is an example of a format for characters transmitted by the interface according to the invention and of the invention which each character contains;

FIG. 4 is a diagram of a station transmitter circuit for the interface according to the invention:

FIG. 5 is a diagram of a station receiver circuit and monitoring circuit for the interface according to the invention;

FIG. 6 is a diagram of a control circuit for the interface according to the invention;

FIG. 7 is a diagram of a apparatus transmitter/receiver circuit associated with each item of apparatus.

In FIG. 1, a group 10 of inputs and outputs of a data-processing unit UT, is connected in parallel to m transmitter/receiver circuits (TRP1, TRP2 . . . TRPm) of the connecting interface according to the invention. Data are transmitted between unit UT and each of the m transmitter/receiver circuits TRP as multi bit parallel characters, which are sequentially derived at a rate controlled by a clock in the unit.

A serial output signal terminal 11 and a serial input signal terminal 12 of circuit TRP1 are respectively connected to lines LT1 and LR1 which form a channel C1, to k transmitter/receiver circuits (TRA11, TRA12 . . . TRA1K) associated with the k items of input-output apparatus (A11, A12 . . . ALk) at a first station P1; m stations P are provided so that there is one interface circuit TRP for each station P. An output 13 and an input 14 of circuit TRP2 are connected in series, by respective ones of lines LT2 and LR2 which form a channel C2, to L transmitter/receiver circuits (TRA21, . . . TRA2L) associated with the items of apparatus (A21, . . . A2L) forming a second station P2. An output 15 and an input 16 of circuit TRPm are connected in series, by lines LTm and LRm forming a channel Cm, to n transmitter/receiver circuits (TRAm1, . . . TRAmn) associated with the n items of apparatus (Am1, . . . Amn) forming an m.sup.th station Pm. Exemplary of the several apparatus items A at the m stations P are card readers, key boards, CRT alpha numeric displays, and memories of mini-computers. Each item of information received by the inputs of circuit TRP1 from unit UT, which is to be communicated to apparatus A11 for example, is transmitted to apparatus A11 from output 11 of circuit TRP1, which is connected to circuit TRA11 by line LT1. Each item of information which apparatus A11 communicates to unit UT is transmitted by circuit TRA11, which is connected to input 12 of circuit TRP1 by line LR1. Once a communication link has been established between unit UT and station P1, for example by circuit TRP1 and lines LT1 and LR1, unit UT may communicate successively with the k items of apparatus A at station P1 without addressing a different one of channels C.

The interface for connecting unit UT to the group of m stations (P1, P2 . . . Pm) in FIG. 1 includes, as illustrated in FIG. 2, a control circuit COD which is connected to be responsive to control signal outputs 20 of unit UT; the control signals enable a communication link between unit UT and a selected apparatus at a selected station to be established via the interface. The control signal outputs 20 are fed to circuit COD from unit UT in response to clock signals or pulses (HoC) which are generated by the unit once a character. Each time a clock pulse HoC derived from unit UT, a control signal is supplied by unit UT to controller COD. In response to the control signals from unit UT circuit COD selectively generates a CTE signal during the interval between adjacent HoC pulses; the CTE signal causes data to be fed from the unit UT to an input buffer circuit TE in the interface and thence to be transferred to one of the station transmitter circuits TP under the control of the further signal (VT) selectively derived from circuit COD under the control of outputs 20 of unit UT. The signal (VT) enables a selected AND gate to transfer the address data contained in circuit TE to the selected transmitter circuit TP; e.g.; if it is desired to establish a link from unit UT to station P.sub.1, the unit supplies a signal to COD which generates a VTP.sub.1 signal to enable AND gate 21 so as to transfer the data contained in circuit TE to transmitter circuit TP1. In response to unit UT signaling it is to be responsive to a signal from a selected one of stations P, a VR signal is derived from controller COD. The VR signal enables an AND gate connected to the selected circuit RP to enable the selected RP circuit to couple a parallel character to buffer TS and thence to unit UT; e.g., if it is desired to establish a link from station P1 to unit UT, control circuit COD derives a VRP.sub.1 signal that enables AND gate 23. (Gates corresponding to gates 21 and 23 for the remaining TP and RP circuits are only illustrated for the circuit TRPm but do not have reference numerals.) Connections to the selected transmitter and receiver circuits TRP and TRA are controlled by signals generated by circuit COD.

Additional signals for controlling parallel to serial readout from interface circuits TRP to stations P and for controlling serial to parallel read in from stations P to circuits TRP are supplied by circuit COD to a selected TRP station under the control of signals VT and VR. The additional control signals are selectively coupled between controller circuit COD and one of circuits TRP through further AND gates enabled by signals VR and VT; for example two AND gates 22 and 24 are respectively enabled by signals VTP1 and VRP1 to transfer control signals from circuit COD to circuits TP1 and RP1 (gates corresponding to gates 22 and 24 for the remaining TP and RP circuits are only illustrated for the circuit TRPm but do not have reference numerals).

Unit UT generates clock signals or pulses (HoT) that are transmitted to the receiving and transmitting circuits TRP and TRA transmission to the apparatus receiver/transmitter circuits TRA at the m stations P is made by the m channels C1, C2 . . . Cm. The HoT signals define the frequency at which data, in the form of characters composed of several binary bits, are transmitted by a pair of lines LR and LT; each of the pairs is included in a separate channel C. The HoT signals have a frequency corresponding to the serial bit rate of data transmitted over channels C. One interval of clock HoC defines the time between adjacent parallel characters being coupled between unit UT and the interface of the invention. The HoT signals provide synchronization between the transmitter and the receiver circuits TRP and TRA which are in communication.

By means of a transmission and reception identifying circuit IRT, which is connected to be responsive to each of the station transmitter and receiver circuits and to supply signals to unit UT via buffer TS, a fresh transfer of information is performed by giving orders to unit UT as a function of the status of the TRP circuit in which or from which the data are to be stored or read. Signals ERTT and ERTR which validate transfers of data, character by character, between the interface transmitter and receiver circuits TRP and unit UT are derived from and generated as a function of the state of the circuits TRP. The high level of an ERTT signal is derived from circuit TP and transmitted to transmission identifying circuit IT in circuit IRT in response to the particular circuit TP being ready to receive new data from unit UT via circuit TE. The high level of an ERTR signal is derived from a particular RP circuit and transmitted to reception identifying circuit IR in circuit IRT in response to the circuit being ready to transmit information to unit UT via circuit TS. For example, in response to circuits TP1 and RP1 being respectively activated to transmit data to channel C1 and buffer TS, signals ERTT1 and ERTR1 have binary one values. Multi-bit control signals for read out control of circuits IR and IT, are respectively supplied from circuit COD to circuits IR and IT through AND gates 22' and 24'. Read out from circuits IR and IT into buffer TS is via gates 21' and 23' that are selectively enabled by signals VIR and VIT. In response to the output signals of circuits IR and IT, unit UT senses the states of circuits IT and IR to determine the state of the circuits TRP with which it wishes to exchange information; hence, unit UT signals to the circuit that it wants to determine the state of a particular TRP circuit and circuit COD derives enabling signals VIT and VIR and control signals which are transmitted to the IR and IT circuits.

A reception monitoring circuit COR is connected to the m reception lines (LR1, LR2 . . . LRm) of the m channels by m inputs to the m station receiver circuits by respective ones of m sets of inputs, and to circuit COD by m other inputs as well as by another set of inputs via circuit COD which derives control signals (CCCR). Information transmitted by one of the station receiver circuits to circuit COR is monitored, in response to control signals emitted by circuit COD, each time a series character is received by one of lines (LR1, LR2 . . . LRm). Circuit COR responds to its input signals to determine if the signals received from lines LR by circuits RP are in error. The results of the monitoring operation by circuit COR are communicated to unit UT through output buffer circuit TS.

An example of the format of the characters which are transmitted by the lines LR and LT in each channel C is given in FIG. 3. Each character contains a first, starting bit bd, eight data bits (bi1, bi2 . . . bi8), a parity bit bp, and two stop bits b1a, b2a. The start bit bd is at a low level NB, preceded by a high level NH. The stop bits b1a and b2a are at a high level NH which is followed by a high level that separates the particular character from the next character transmitted along the same line. The clock signals HoT which are transmitted to the station transmitter and receiver circuits and the apparatus transmitter and receiver circuits have a frequency of transmission and reception of bits of a character, for example, sixteen times higher than that at which bits are transmitted along the lines. FIG. 3 shows the information contained in a character in cases (a), (b), (c), (d), (e), (f), (g), as binary values 1, 0 and either of these two values (represented by X) in the case of the data bits (bi1, bi2 . . . bi8). Cases (a), (b), relate to two kinds of characters which may be transmitted by a transmitter circuit TPj to a station Pj. Cases (c), (d), (e), (f), (g), relate to five other kinds of character which may be received by a receiver circuit RPj from a station Pj selected by signals VTPj and VRPj. In case (a), bit bi8= 1, bit bi7= 1, and bits bi6 to bi1 represent the number of the apparatus to be selected to communicate with unit UT; In case (b), bi8=0 and the following bits from bi7 to bi1 represent the commands or data to be transmitted to the apparatus which has been selected by the preceding case (a), character, i.e., by its number which has previously been transmitted along the LTj line. In case (c), bi8=0 and the following bits from bi7 to bi1 represent the data which are received from an apparatus which has been selected by having its number transmitted previously by circuit TPj. Case (d), in which bi8=1, bi7=0 and bits bi6 to bi1 may be of any value whatever, represents the case in which there has occurred an error which is not a transfer error on one of the lines LTj or LRj. Case (e), where bi8= 1, bi7= 0and each of bi6 through bi1 is a binary 0, represents the case where one of the items of apparatus; a keyboard for example, requests an interruption to the program by which unit UT is communicating with any apparatus at station Pk. Case (f), in which bi8= 1 bi7=1 and the other bits bi6 to bi1 are of any value whatever, represents the case where an error has occurred during the transfer of data from the unit UT to an apparatus. Case (g), in which bi8, bi7, and a11 the succeeding bits are of any value whatever, represents the case where an error has occurred during the transfer of data from an apparatus to the unit UT.

Transmitter circuit TPj, FIG. 4, for station Pj, contains a parallel access buffer register RTTj in which data bits bi1, bi2 . . . bi8, FIG. 3 are stored after having passed through an AND gate 21j corresponding to gate 21 connected with circuit TP1. The data stored in register RTTj is derived from unit UT and supplied to the register via input buffer circuit TE, having a number of parallel stages equal to the number of data bits (in FIG. 4 buffer TE is a register having eight storage locations); the data bits stored in register RTTj are awaiting transmission along line LTj. The low level of a signal (CRTTj) fed by circuit COD to an enable input of register RTTj causes the data passed through the AND gate 21j to be fed into buffer register RTTj. Circuit TPj also includes a parallel to series converter or register RTj to which the outputs of register RTTj are applied in parallel. In response to signal (CRTTj) going to a high level, the 8 bit character in register RTTj is fed into register RTj via AND gate 40 which is enabled by a signal (RTjV) being generated by register RTj to indicate that the register is empty of data, that is to say that nothing is being transmitted along line LTj.

Each character transmitted by line LTj has the sequential format shown in FIG. 3. The sequential bits are generated by cascaded circuit including start-bit generator GbdTj, the register RTj (which contains the data transmitted by register RTTj), a parity bit generator GbpTj and a stop-bit generator GbaTj.

Each time a set of data is transferred from register RTTj to register RTj; register RTTj generates a signal (ERRTj), the high level of which indicates that the register RTTj is ready to receive a new 8-bit data character from unit UT. The state of register RTTj is transmitted to the transmission indicating circuit IT in response to signal (VIE) derived from circuit COD data are transferred from register RTTj to register RTj while VIE has a high state to enable AND gate 41. Circuit COD derives two control signals (CGC.sub.T) to cause bits bd, bp, b1a, b2a to be generated respectively by the three generators Gb.sub. d T, Gb.sub. p T and GbaT interconnected with register RTj in the same order that generated bits according to the format of character shown in FIG. 3.

The clock pulses (HoT), FIG. 2, are transmitted to register RTj and to station Pj via channel Cj. During the first clock pulse (HoT), bit bi1 is transferred or shifted into generator GbdTj; in response to bit bi1 being shifted into generator GbdT.sub. j, the generator transmits to line LTj the start bit bd which was previously generated therein. All the other bits forming the character are shifted one place towards the left in register RTj and generators GbpTj and GbaTj. All the bits in a character are thus transmitted in succession along line LTj in the course of a transmission sequence, until stop bit b2a has been transferred from register RTj to generator GbdTj during a last clock pulse (HoT); immediately after bit b2a has been transferred to generator GbdTj, it is transmitted along line LTj. Generator GbdTj continues to derive a high level (the same level as bit B2A) until the next character is fed into converter RTj, i.e., until the start bit bd of the next character is derived from generator GbdTj under the control of the CGCT pulse at the beginning of the next character.

In FIG. 5, a station receiver circuit RPj of the interface according to the invention is illustrated as containing a serial to parallel converter or register RRj which has a series input from line LRj of channel Cj and parallel outputs. After a series character has been loaded into converter RRj, the eight data bits (bi1, bi2 . . . bi8) in the character are supplied by the parallel outputs of the converter to parallel inputs of a buffer register RTRj where they are stored while waiting to be read by unit UT, which is connected to buffer RTRj via AND gate 23j and output buffer circuit TS; each of registers RRj, and RTRj and TS has a number of stages equal to the number of data bits in a character so that in the system of FIG. 5 each of these registers has 8 storage locations. When register RRj is full, that is to say when it contains the 8-bit data (bi1, bi2 . . . bi8) making up a series character received from line LRj, it emits a signal (RRjP) which enables AND gates 50 to allow the data bits to be transferred to register RTRj. Circuit COD derives a signal (LRTRj) that enables buffer register TS to read from register RTRj. When register RTRj has been emptied of its content, the high level of a signal (ERTRj) is transmitted to the reception identifying circuit IR of FIG. 2 through an AND gate 51 which is at this time enabled by signal (VIE) of FIG. 4, that is derived from circuit COD.

To separate the start, stop and parity bits from the data bits in each series character coupled to circuit RPj so that only the data bits are supplied to converter RRj, circuit RPj includes a character detection circuit CDEj having one input responsive to the eight sequential character forming bits on line LRj; the bits are coupled to circuit CDEj at a frequency controlled by the clock signals (HoT) coupled to circuit CDEj from unit UT. To control circuit CDEj so that only the data bits are supplied to converter RRj and other bits in the received series character are routed to monitoring circuit COR for error checking purposes, control signals (CCCR) are generated by circuit COD in response to the program being run by unit UT. This is to be expected since the format of the character (such as that shown in FIG. 3) is determined by the program being carried out by unit UT. The start bit, bd, of a character received from line LRj is detected by circuit CDEj and the following eight bits, i.e., data bits bi1 to bi8, are transmitted by circuit CDEj to the series input of register RRj for storage there (before being transferred to register RTRj) at a loading frequency which is determined by the clock signals (HoT).

Monitoring circuit COR includes a first monitoring circuit CPa for checking the parity (or lack of parity) of the 8 data-bits received in a character by receiver circuit RPj. To this end, the parity bit coupled by line LRj is detected by circuit CDEj and thence routed to circuit CPa under the control of signals CCCR. Circuit CPa comprises a parity generator responsive to the parallel outputs of register RRj to calculate the parity of the data bits bi1 to bi8 which are received from line LRj. The parity calculated by the parity generator is combined with the detected parity supplied by detector CDEj in a comparator which derives an error signal EPa in response to the calculated parity being different from bit bp.

Circuit COR contains two other circuits CCa and DSu for checking justification and detecting overloading in response to selective bits of a serial input character. To this end, the first data bit bi1 and the stop bits are coupled from detector CDEj to circuits DSu and CCa under the control of signals (CCCR). For the format of FIG. 3, the first stop bit b1a must be at a high level, otherwise the character is mis-justified. Circuit CCa determines whether bit b1a is at the required high level; if bit b1a is not at the high level circuit CCa derives a justification error signal ECa. Overflow detecting circuit DSu determines whether and end-of-character received by an input from the detection circuit CDEj reception signal Fc, is approximately in time coincidence with the derivation from register RRj of the signal (RRjP) when the content of register RRj is feed into register RTRj. If circuit DSu receives signal Fc before circuit COD has indicated to it by means of signals (CCCR) that the previous character has been read out from register RTRj, circuit DSu derives an overflow error signal ESu.

Circuit COR includes an OR gate OU2, selectively responsive to the outputs of circuits CPa, CCa, and DSu, as respectively coupled through AND gates 52, 53 and 54, all of which are enabled by output signal (VIE) of circuit COD. If at least one of the three error signals EPa, ECa, ES is present at the input to OR gate OU2, the OR gate derives an error signal ERj. Six-bit data consisting of bits bi1 to bi6 are respectively transferred from locations b1 to b6 of register RTRj to locations B1 to B6 of register TS in response to an enabling signal (VRPj) being derived from circuit COD. As shown in FIG. 3, the binary value of data bits bi7 and bi8 is significant of the state of the character. By means of OR gates OU7 and OU8 in circuit COR the two bits bi7 and bi8 are transferred from locations b and b8 of register RTRj to locations B7 and B8 of register TS by signal VRPj enabling AND gates 55 and 56 which are respectively connected to the outputs of OR gate OU7 and OR gate OU8. In response to an error signal ERj being derived from gate OU2, bits bi7 and bi8 are made to assume the value 1 to indicate to unit UT that the character being transferred to it is erroneous. To this end the ERj signal is applied in parallel to OR gates OU7 and OU8, and thence to stages B7 and B8 of buffer register TS. When locations B1 to B8 or register TS have been loaded, the 8 data bits in register TS are transferred to unit UT in response to an enabling signal (LTS) being coupled to the register from circuit COD.

The control circuit COD illustrated in FIG. 2, 4 and 5 contains in FIG. 6 a control register RC into which are successively fed the interface command signals (CI) which are transmitted by the unit UT when it is running the program that controls the communications with at least one of the m stations via the interface of the present invention. Clock signals (HoC) derived from unit UT cause register RC and a register RS of circuit COD to be loaded respectively with the signals CI and signals CS which are the coded number of each circuit to be selected by circuit COD. The coded number of any circuit to be selected is transferred from register RS to a decoder DCD by means of read-enabling signal LRS being coupled from register RC to register RS. A control signal (CDCD) transmitted from the output of register RC to decoder DCD allows the circuit number supplied to decoder DCD to be decoded as being that of one of the station receiver and transmitter circuits (TRP1, TRP2, . . . TRPm) of FIG. 1 or the reception and transmission identifying circuit IRT of FIG. 2.

Decoder DCD has at least (m+1) outputs (VP1, VP2, . . . VPm, VIRT) only one of which may be energized at any particular time to select any one of the (m+1) TRP and IRT circuits. The (m+1) outputs (VP1 . . . VPm, VIRT) of decoder DCD are connected to respective ones of two sets of AND gates respectively enabled by a transmission enable signal (VT) and a receive enable signal (VR) transmitted by register RC when the unit has to exchange information with station transmitter/receiver circuits via registers TE and TS. Thus, when station number P1 is decoded by decoder DCD and the transmission enable signal (VT) is derived from register RC, a signal (VP1) is transmitted from the first output of the decoder through the first AND gate 60 to produce the signal (VTP1) of FIG. 2. In response to the number of monitoring circuit IRT being decoded by decoder DCD and the transmit enable signal VT being derived, a signal (VIRT) is derived from the (m+1).sup.th output of the decoder and coupled through enabled AND gate 62 as signal (VIT) (FIG. 2). Similarly, if station number P1 is decoded by decoder DCD while a receive enable signal VR is being derived, signal (VP1) is transmitted from the first output of the decoder to generate signal (VRP1) (FIG. 2) at the output of the first AND gate 61. The number of monitoring circuit IRT being by decoder DCD, a signal VIRT is generated at a (m+1).sup.th output of the decoder and two decoded signals VIT and VIR (FIG. 2) are generated respectively from the output of two (m+1).sup.th AND gates 62 and 63 enabled by signals VT and VR.

The control signals CI are sets of bits successively generated by unit UT and loaded, by inputs in parallel of register RC, in the set of flip-flop of which is composed the register enabled by successive clock signals HoC. Each set of bits loaded in register RC is then transmitted, during an interval of time between two adjacent clock pulses HoC, by at least one signal generated at one of the outputs in parallel of register RC. Thus, by seven successive sets of bits sent by unit UT, the signals CCC.sub.R, LRTR, VIE, CRTT, CGC.sub.T, LTS, CTE, are successively generated at different outputs of register RC. Said outputs are respectively connected with circuit COR of FIGS. 2 and 5, register RTR in circuit RP of FIG. 5, AND gate 41 in circuit TP on FIG. 4, register RTT in circuit T.sub.P of FIG. 4, generator Gb.sub.a T in circuit TP of FIG. 4, register TS of FIGS. 2 and 5, and register TE of FIGS. 2 and 4. The four other signals LRS, CDCD, VT and VR of FIG. 6 are also generated at four other outputs of register RC respectively connected with register RS, decoder DCD and the two sets of AND gates such as gates 61 and 60.

In FIG. 7 there is illustrated an embodiment of the apparatus transmitter/receiver circuit TRAjd associated with an apparatus Ajd at station Pj. Circuit TRAjd contains a receiver circuit RAjd to convert a received series-character from line LTj into a parallel-character which is coupled to apparatus Ajd while AND gate 70 is enabled by signal VRAjd that is selectively derived from control circuit CODjd. Circuit TRAjd includes a transmitter circuit TAjd for converting a parallel input character derived from apparatus Ajd into a series-character which is transmitted along line LRj by one output. The parallel input to circuit TAjd is through AND gate 71 while the AND gate is enabled by a VTAjd output signal of control circuit CODjd. Circuits RAjd and TAjd are of a similar design to the station receiver and transmitter circuits shown in FIGS. 4 and 5.

Clock signals (HoT) are transmitted along channel Cj to circuits RAjd and TAjd to synchronize their operation with that of the receiver and transmitter circuits of station Pj with which they respectively exchange information. The first character transmitted along line LTj by the transmitter circuit TPj contains the number of the apparatus to be selected. This first character, having been converter by circuit RAjd into a parallel character, is transmitted to an apparatus identifying circuit IAjd which compares the apparatus number received with the apparatus number Ajd which is generated by a generator GAjd. If the two numbers are the same, circuit IAjd generates a signal to enable control circuit CODjd which controls circuit TRAjd. A monitoring circuit CORjd responsive to parallel output bits of circuit RAjd monitors each received character to derive a character indicating error signal that is supplied to control circuit CODjd.

After a complete character has been transmitted by circuit TAjd to line LRj, circuit TAjd derives a signal that causes circuit CODjd to generate the signal VTAjd for enabling AND gate 71 to transfer a fresh character from apparatus Ajd to transmitter circuit TAjd. In the event of an error being detected by circuit CORjd when a character is being received by circuit RAjd, circuit CODjd supplied a disable signal to the transfer of a character to apparatus Ajd. Detection of an error in the signal received by circuit RAjd also causes circuit CORjd to change bits bi7 and bi8 of the character to be transmitted along line LRj in accordance with the state code shown in FIG. 3; so an abnormal state resulting from an error being detected by circuit CORjd is indicated to unit UT by the changed bits bi7 and bi8 of the character transmitted by line LRj.

To initiate a message from unit UT through the connecting interface which is the subject of the present invention, when requested by an operator the unit UT derives a sequence of apparatus call-ups by transmitting along the channel C for the selected station P characters having codes that follow a binary progression, for example. If the apparatus requested is not at the selected station, unit UT requests the next apparatus in the sequence by the call-up, since no signal is supplied to the unit by buffer TS within a predetermined interval after the signal for the particular apparatus was derived from unit UT; to this end UT includes a programmed timer. After making a complete round, the data-processing unit UT knows, the configuration of the station, that is to say the numbers of the items of apparatus situated at the station. For example, by allotting different numbers from 0 to 63 to the items of apparatus at a given station (these numbers being represented by the different combinations of the six address bits bi1 to bi6 in FIG. 3), a large number of items of apparatus may be installed and addressed at a station without it being necessary to take into consideration their nature, that is type and sub-type of the apparatus item, as is necessary with star connections.

With an interface of the type described, it is possible to interrupt the execution of a running program by which unit UT is communicating with one of the items of apparatus in the stations connected to it. An item of apparatus, such as a keyboard may transmit a character, as in case (e) (FIG. 3) which, when transmitted to unit UT, causes the running program to be interrupted. In general terms, there is an interruption of the program of unit UT when: bit bi8 received by a station receiver circuit RP has a value of one in the event of a malfunction being detected by circuit TRA at a station P or when bit bi8= 1, in response to an error being detected by circuit COR at the interface as occurs when an erroneous character is received by the interface on line LRj. As a result of this interruption, an instruction to restart the interrupted program allows unit UT to identify the number of the station responsible for the interruption. Thereby, a diagnosis may take place in the event of a fault, or a message may be initiated with the keyboard, for example which has data to exchange with the unit.

A modification to the interface according to the invention involves connecting data-processing unit UT to at least one apparatus in a working station through two channels, one of which is connected to another apparatus transmitter/receiver circuit. Thereby, said apparatus can communicate with unit UT through two stations since two channels can connect it to the unit and simultaneous communications between the apparatus and unit UT can be along two channels by selecting the two stations in parallel.

The invention described is particularly beneficial when applied to so-called slow items of apparatus, that is, to apparatus which is able to transmit or receive data only at a rate slower than that at which unit UT can transmit or receive data. In effect, the series-transmission of each character does not represent a drawback from a performance point of view. Also, because unit UT is only able to communicate with a single apparatus in the same working station at any one time, the sequential connections between unit UT and the items of apparatus at a station does not represent a drawback.

The invention also has the advantage that it can be employed if data-processing unit UT is a microprocessor having a cycle time of approximately 2 microseconds, in which case the unit is easily able to manage eight working stations. In a preferred embodiment of the invention, transmission along each channel takes place at a rate of the order of 10,000 bauds.

While there has been described and illustrated one specific embodiment of the invention, it will be clear that variations in the details of the embodiment specifically illustrated and described may be made without departing from the true spirit and scope of the invention as defined in the appended claims.