Gain Ranging Amplifier System

This application forms part of a group of patent applications filed concurrently, having the following attorney's docket numbers, serial number, titles and inventors:

The invention generally relates to gain-ranging amplifier systems and more particularly to binary gain-ranging amplifier systems such as are employed, for example, in digital seismic systems.

In multi-channel analog-digital data acquisition systems, the signals are first multiplexed or sampled and then converted into digital numbers corresponding to the sampled signal amplitudes. When these amplitudes have a very wide dynamic range, say between 0 and 90 dB, it is desirable to first pass the sampled analog signals through a binary gain-ranging amplifier system prior to converting them into digital numbers. In this fashion, the amplified output signals will fall within a limited range thus enhancing the signal to noise ratio.

A widely employed binary gain-ranging system includes a plurality of fixed-gain amplifiers whose outputs can be selectively connected to a common bus by a system controller. A comparator makes a comparison between the amplitude of the output signal from the common bus and a single reference voltage. If the output signal is smaller than the reference voltage, then the comparator will cause the controller to insert into the system an additional amplifier. The process is repeated until the output signal from the common bus becomes greater than the single reference voltage. The gain of a number of cascaded amplifiers can be expressed in digital form to any particular base, typically 2. For example, if the gain is to range in incremental gain steps having a ratio of 2:1 from 2.sup.0 to 2.sup.15, sixteen gain decisions and fifteen amplifiers are required. The drawbacks of such a binary gain-ranging system stem primarily from the relatively large number of required fixed-gain amplifiers. Also, the comparator must be adapted to make sixteen decisions based on sixteen comparisons and the controller must be adapted to execute these sixteen decisions.

In such a system the total time required to select the proper gain in order to amplify each sampled analog signal, including the time required by the amplifiers to settle to their steady states, is relatively large and wasteful of expensive data processing time. Additionally, the large number of required amplifiers and associated hardware would require a larger volume than is generally available in miniaturized systems. Furthermore, since signals having different amplitudes must pass through different numbers of amplifiers, differences in amplifier characteristics of the various amplifiers adversely affect the output signals.

Accordingly, the main objects of the present invention are to reduce the number of required amplifiers and to reduce the size of conventional gain-ranging amplifier systems.

It is a further object of the present invention to provide a new and improved binary gain-ranging system which is especially adapted for use in confined areas, for example within a seismic streamer cable having an outside diameter of a few inches.

The gain-ranging amplifier system comprises at least two and preferably four bi-gain amplifiers connected in cascade between an input terminal and an output terminal. Each amplifier normally has a low-gain state and can be switched by a controller to a high-gain state. Voltage reference means selectively provide a discrete reference voltage to correspond with each amplifier. A comparator makes a comparison between the system's output voltage and the selected reference voltage. If the comparison shows that the reference voltage is greater than the output voltage, the controller adjusts the first amplifier to its high-gain state. Thereafter, the comparator makes a second comparison between the system's output voltage and the reference voltage which corresponds to the second amplifier. Again, if the comparison indicates that the reference voltage is greater than the output voltage, the controller will adjust the second amplifier to its high-gain state. This process will be repeated until the comparison indicates the the system's output voltage is greater than the reference voltage corresponding to a particular amplifier, or until all of the amplifiers have been adjusted to their high-gain states. Thus, the overall gain of the system is adjustable in incremental steps from a low-gain value, preferably unity, for large-amplitude incoming signals, to a high-gain value for small-amplitude incoming signals. By this means, no amplifier is in danger of being overdriven.

In a further embodiment of the invention arrangements are provided for automatically cancelling DC or very low frequency noise signals that may be present at the input terminals to each amplifier as a result of the individual amplifier characteristics. The noise-cancelling circuit includes a capacitor and switch connected between the input-output circuit of each amplifier for periodically isolating the amplifier and charging the capacitor with the self-generated amplifier noise. The charge on the capacitor will have an amplitude and polarity equal and opposite to the self-generated noise such as to substantially cancel the DC noise signals appearing on the input terminals to each amplifier.

A distinct advantage of the disclosed system stems from the fact that all four amplifiers are always connected in the circuit. The above fact being true, there is no danger of differential distortion at different signal levels as was true of the prior art.

For a better understanding of this invention reference may now be made to the accompanying drawings and detailed description wherein:

FIG. 1 is a block diagram representation of an improved binary gain ranging system of the invention;

FIG. 2 is a schematic diagram of an amplifier with noise-cancelling means; and

FIGS. 3A and 3B are schematic representations of the noise-cancelling principle.

An analog to digital acquisition system includes a multiplexer 10 having a plurality of signal input channels C.sub.1, C.sub.2, . . . , C.sub.n all connected to a bus 12 through DC blocking capacitor 14, resistors 15, and switches 16. Each resistor 15 in combination with its capacitor 14 forms a high-pass RC filter for its channel. Switches 16 are high-speed FET switches of any well known type. Seismic sensors 9.sub.1, 9.sub.2, 9.sub.n may provide the source signals for the system.

The output of multiplexer bus 12 is typically connected to the non-inverting input of a unity-gain buffer amplifier 20 that may be an operational amplifier such as an LF 356, made by National Semiconductor, Inc. The output of buffer amplifier 20 is connected to a sample-and-hold circuit 22 having a series capacitor 24 and a shunt switch 26. The output of circuit 22 is coupled to the gain-ranging system 28 of this invention.

The gain-ranging amplifier system 28 has an input terminal 30 and and output terminal 32 and basically consists of at least two and preferably four bi-gain amplifiers A.sub.1, A.sub.2, . . . , A.sub.m connected in cascade. Each amplifier would typically include a pair of input terminals 33, 34 and an output terminal 35 (FIG. 2). The non-inverting input 33 to the first amplifier A.sub.1 is coupled to the input terminal 30 which receives the output signal of the sample-and-hold circuit 22. The output voltage of the last amplifier A.sub.m on output terminal 32 is applied to a signal utilization device such as an analog-to-digital (A/D) converter 36 as well as to a window comparator 38 (FIG. 1). The gain of each amplifier may be set or adjusted to one of two states, a low-gain state, preferably equal to unity, or to a high-gain state G.sub.i, where G.sub.i is a discrete high-gain value for the ith (i = 1, 2, . . . ,m) amplifier.

A state controller 40 is interconnected with switches 16, 26, through a control bus 41 having a plurality of control lines. Controller 40 sequences the signal input channels C.sub.1 -C.sub.n through a multiplexer scan cycle.

Associated with state controller 40 are a variable reference decoder 44 and the window comparator 38. Gain-control lines 50 and noise-cancelling control lines 60 interconnect state controller 40 with each one of the amplifiers A.sub.1 -A.sub.m. For simplicity, only one gain-control line 50 and one noise-cancelling control line 60 are shown in FIG. 1, but it should be understood that there will be as many such control lines as there are amplifiers.

In a preferred embodiment, state controller 40 is a synchronous programmable counter such as a 74S161 integrated circuit made by Texas Instruments. Reference decoder 44 is a digital-to-analog converter (DAC) such as MC 1408L made by Motorola. Comparator 38 may be a LM 311 voltage comparator, and each one of amplifiers A.sub.1 -A.sub.m is a high input impedance operational amplifier such as LF 156 both devices being made by National Semiconductors, Inc.

Each one of the amplifiers A.sub.1 -A.sub.m has a gain-control circuit and a noise-cancelling circuit, both shown in detail in FIG. 2. The control circuit includes a voltage divider network formed by resistors 70, 72, FET switches 74, 76, and a gain-control line 50. In the gain-setting operation, when switch 76 is closed and switch 74 is open, the amplifier's output signal is fed back from output 35 to the inverting input 34, thereby setting the amplifier to its low-gain state which is equal to one. When switch 74 is closed and switch 76 is open, the amplifier is set to its high-gain state G.sub.1 since resistor 70 is now in the amplifier's feedback loop. The desired gain state is set in response to a control signal from controller 40 through a control line 50.

The noise-cancelling circuit comprises FET switches 82, 84, 86, a capacitor 88, and a noise-cancelling control line 60. When switch 82 is closed, switches 84 and 86 will open.

In the noise or offset removal mode by means of which the characteristics of each amplifier are corrected, controller 40 sends a signal through a control line 50, to close switch 76 and open switch 74, thereby setting each amplifier to unity gain-state. Simultaneously, controller 40 disconnects the input terminal 30 to system 28 by opening switch 82 and establishes connection, by closing switch 84 (FIG. 2 and 3A), between junction 90 and the output terminal 35 of the amplifier. Input terminal 33 to the amplifier is grounded by closing switch 86. Switches 82, 84 and 86 are actuated by a signal arriving on a control line 60. Any DC noise ("offset") will now appear on the amplifier's output terminal 35. Capacitor 88 will become charged with the polarities across its plates 88a, 88b as shown for an offset voltage +V appearing on input terminal 33 (FIG. 3B). When the offset removal mode has been completed, controller 40 will close switch 82 and open switches 84 and 86 by means of a second signal through control lines 60, thus reconnecting the input terminal 30 with the amplifier system 28 and restoring the amplifiers to their normal operating mode.

The charge voltage +V across capacitor 88 will now be algebraically added to the incoming signal V.sub.in, and will substantially completely cancel the amplifier's inherent offset signal +V as demonstrated in FIG. 3B. The amplifier's output signal will therefore become free of DC noise regardless of the gain to which the amplifier may have been set. The factors which determine how often it is necessary to go into the offset-removal mode will depend on the rate the offset noise drifts and on the value of the amplifier's input impedance.

In the gain-ranging operation, the gain-determination cycle for each channel (such as channel C.sub.1) starts with all of the amplifiers set to unity gain. State controller 40 provides a sequence of digital codes representing a corresponding sequency of variable reference voltage steps. The digital codes are converted to corresponding discrete reference voltages V.sub.R by reference decoder 44. The reference voltages can be stepped through the sequence

where G.sub.1, G.sub.2, . . . , G.sub.m are the higher gain values of amplifiers A.sub.1, A.sub.2, . . . , A.sub.m, respectively, and V.sub.B is a base voltage equal to a preselected fraction of the full-scale voltages of A/D converter 36. The gains G.sub.1 are proportional to a preselected power of some number base, say two; the preselected power is unique for each amplifier. The variable reference voltage steps V.sub.Ri are inversely proportional to the unique gain values of their corresponding amplifiers. It may be noted in passing that the controller 40 includes as part of both offset removal mode and the gain ranging mode, the setting of the amplifier to their unity gain state. This common step simplifies the implementation of these functions.

In a preferred embodiment, G.sub.i = 2 exp 2.sup.(m-i). For an amplifier system 28 comprising four amplifiers (m = 4), the respective high-gain values for the amplifiers would be: G.sub.1 = 256, G.sub.2 = 16, G.sub.3 = 4, G.sub.4 = 2. With only four high-gain settings, the overall gain of the binary amplifier system 28 can be made to range from 2 to the zeroth power (i.e. one) to 2 to the 15th power (i.e. 32,768) in steps of powers of 2. To accomplish the above, only four gain decisions need to be made. The gain comparisons must be made using the amplifier having the highest gain setting first, and thereafter the comparisons are made in order of descending amplifier gain, regardless of the electrical position of the particular amplifier in the cascade.

The gain-ranging operation will now be explained in greater detail. With all four amplifiers set to unity gain, the absolute value of the system's output voltage .vertline.V.sub.O .vertline. appearing on output terminal 32 is compared with the first reference voltage V.sub.R1 = V.sub.B /256 by comparator 38. Comparator 38 rectifies V.sub.O and compares its absolute value with reference voltage V.sub.R1. The decision based on this comparison is applied to controller 40. If .vertline.V.sub.O .vertline..gtoreq. V.sub.R1 controller 40 causes the gain of amplifier A.sub.1 to remain at unity gain. If .vertline.V.sub.O .vertline. < V.sub.R1 controller 40 sets the gain of amplifier A.sub.1 to G.sub.1 or 256. The variable reference voltages V.sub.R2, V.sub.R3, V.sub.R4, are then sequentially compared with the successive values of .vertline.V.sub.O .vertline. that appear after the sequential switching decisions are made. As each comparison is made, a gain decision is also made by controller 40 for the amplifier having the next successive lower gain corresponding to the reference voltage used for the comparison.

In sum, the comparator 38 compares the output signal .vertline.V.sub.O .vertline. on terminal 32 with reference voltage V.sub.R1 corresponding to amplifier A.sub.1. When the comparison is negative, that is, when the absolute value of V.sub.O is less than V.sub.R1, then comparator 38 will instruct controller 40 to open the normally-closed switch 76 and close the normally-open switch 74 (FIG. 2). Amplifier A.sub.1 is now at its high-gain setting. The sampled signal held by the sample-and-hold circuit 22 is again amplified by the binary gain ranging system 28, with amplifier A.sub.1 adjusted to its high-gain setting and the remaining amplifiers A.sub.2 -A.sub.4 remaining at their unity gain settings. If the new value .vertline.V.sub.O .vertline. < V.sub.R2, i.e., if the result of the second comparison is again negative then comparator 38 will instruct the controller 40 to set amplifier A.sub.2 to its high-gain setting. The sampled signal will again be amplified by the binary gain-ranging system 28 having amplifiers A.sub.1 and A.sub.2 at their high-gain settings and amplifiers A.sub.3, A.sub.4 at their unity gain settings. If the next value .vertline.V.sub.O .vertline. < V.sub.R3, i.e., if the result of the third comparison is again negative, controller 40 will cause amplifier A.sub.3 to assume its high-gain setting. If after the fourth comparison .vertline.V.sub.O .vertline. < V.sub.R4, then controller 40 will cause amplifier A.sub.4 to assume its high-gain setting but if .vertline.V.sub.O .vertline. .gtoreq. V.sub.R4, controller 40 will hold the amplifier at unity gain. After completion of the fourth comparison, comparator 38 will instruct controller 40 to cause the A/D converter 36 to accept the voltage V.sub.O that now appears and to convert it into a digital number.

After the completion of each gain-selection sequence, the overall gain of the cascade of four amplifiers is encoded by controller 40 as a digital gain-code word which will include as many bits as there are amplifiers in amplifier system 28. Each bit of the gain-code word represents the state of switch 76. The gain-code is ONE if switch 76 is open, it is ZERO if it is closed. Thus, in the case of four amplifiers, if all of the amplifiers are set to unity gain, the gain code will be 0000. If the overall gain is 64, the gain code will be 0110.

Thus with four amplifiers, requiring only four decisions, the binary gain-ranging system 28 of the present invention will provide 2.sup.15 gain steps, a job which previously required fifteen amplifiers and sixteen distinct decisions and executions. Hence the binary gain-ranging system 28 of the present invention can accomplish the job of selecting a suitable gain for the amplifier system 28 in a fraction of the time previously required by the known systems. System 28 will occupy a fraction of the volume previously needed to house a conventional binary gain-ranging amplifier.

In the foregoing specification, one illustrative embodiment of the invention has been described. It is to be understood, however, that minor modifications and departures from the specific structure and circuitry are within the scope of the present specification. By way of example but not by way of limitation, the gain states of the amplifiers could be based on a ternary, octal or decimal number base instead of binary.