Integrated Zener Diode

This invention relates to an integrated zener diode and, more particularly, to an integrated circuit having a current-voltage characteristic of the conventional pn-zener diode and which is capable of being integrated and assigned to two-polar use. Further, the term zener diode is understood to mean a pn-diode whose breakdown mechanism is governed by the zener breakdown and not by the so-called "avalanche"-effect, hence a pn-diode having a negative temperature coefficient of the breakdown voltage below about 5V. Relative thereto, reference is made to the technical journal "Electronic Industries" (February 1959), pp 78 to 83.

As is well known, zener diodes are classified according to types corresponding to selected zener breakdown voltage ranges. One problem in the mass production is to achieve certain types as desired by customers. In the manufacture of conventional zener diodes, this is accomplished by selecting semiconductor material having a predetermined specific resistance, and is more difficult when tolerances in breakdown voltages are demanded.

It is the object of the invention, therefore, to reduce the dependency on the tolerances of the specific resistance of the employed semiconductor material.

According to a broad aspect of the invention, there is provided an integrated zener diode, comprising: a first forward-biased load transistor having an emitter, base and collector; a resistor; and a second transistor having a collector, base and a plurality of emitters, the base of said first transistor coupled to the collector of said second transistor and, via said resistor, to the emitter of said first transistor and a first emitter of said plurality of emitters, the collector of said first transistor coupled to a second emitter of said plurality of emitters.

Preferably, the integrated zener diode according to the invention is realized by a planar embodiment of the transistors in an epitaxial layer of one conductivity type on a plate-shaped substrate of another conductivity type. This enables the mass production within a semiconductor wafer which is to be divided into the individual integrated zener diodes, by employing photolithographic etching processes and planar diffusion processes which are both carried out on one surface side of the semiconductor wafer.

The above and other objects of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 shows the equivalent circuit diagram of the integrated zener diode according to the invention; and

FIG. 2 is a cross sectional view taken vertically in relation to the plane of the wafer through the zones of an integrated zener diode of planar design according to the invention.

For the zener diode of the invention there is used, as shown in FIG. 1, the emitter-collector path E.sub.2, B.sub.2, C.sub.2 of a load transistor which, according to the plus-sign and the use of a pnp-type transistor T.sub.2, is biased in the forward direction. The base of this load transistor T.sub.2 is coupled through resistor R, to its own emitter E.sub.2. Parallel to resistor R and the collector to the base B.sub.2 path of the load transistor T.sub.1, there is arranged the emitter-collector path E.sub.11, B.sub.1, C.sub.1 of a further transistor T.sub.1 which may be considered to be a transistor without a base terminal or as a transistor having an emitter E.sub.11 serving as the base terminal. Accordingly, there is omitted an ohmic base terminal which would require additional semiconductor surface area.

The base B.sub.2 of the load transistor T.sub.2 is also connected to the collector C.sub.2 of the load transistor T.sub.2 via a further emitter-collector path E.sub.21, B.sub.1, C.sub.1 biased in the forward direction of transistor T.sub.1.

Since the coarse selection during manufacture is carried out during the base diffusion, there is provided for the fine selection of a type of the integrated zener diode corresponding to a constricted tolerance range of the zener voltages in the base zone of the further transistor T.sub.1, at least one further emitter or one further emitter zone E.sub.31 which, just like the emitter E.sub.11, may be likewise connected to the emitter E.sub.2 of the load transistor T.sub.2.

For the planar embodiment of the integrated zener diode according to the invention as shown in FIG. 2, the zones of the two transistors T.sub.1 and T.sub.2 are brought into the epitaxial layer of the one conductivity type by employing the well known planar diffusion process. For this purpose, however, two planar processes are required. During the first planar process the emitter zone E.sub.2 of the load transistor T.sub.2 is diffused together with the base zone B.sub.1 of the further transistor T.sub.1, whereas during the second planar process, the emitter zones E.sub.11, E.sub.21, E.sub.31 and, if so required, also further emitter zones are inserted into the base zone B.sub.1 of the further transistor T.sub.1.

Accordingly, in the planar type of embodiment of the integrated zener diode according to the invention, both the collector zone C.sub.1 of the further transistor T.sub.1 and the base zone B.sub.2 of the load transistor T.sub.2 are designed to have the shape of one continuous epitaxial layer 5. The plate-shaped or wafer type substrate 4 is effective below the emitter zone E.sub.2 of the load transistor T.sub.2 as a collector zone C.sub.2 of this load transistor T.sub.2, and provided with the ohmic contact 6.

The other ohmic contact 7 which, in a type of embodiment employing a pnp-type load transistor T.sub.2 and an npn-type transistor T.sub.1, receives the more positive potential, is connected to a contact layer 8 serving to contact the emitter zone E.sub.2, the base zone B.sub.2 within a frame-like emitter zone E.sub.2 of the load transistor T.sub.2, and the emitter zone E.sub.11, as well as in accordance with the type selected, still one or more further emitter zones E.sub.31, etc. In this way, the resistor R is realized by a semiconducting channel 1 serving as a partial zone of the base zone B.sub.2 of the load transistor T.sub.2, within the frame-like emitter zone E.sub.2 of the load transistor T.sub.2 and the contacting layer 3 shortcircuiting the emitter-base junction 2 within the frame-like emitter zone E.sub.2. As the material for this contacting layer, it is possible to use e.g. a metal such as aluminum.

Furthermore, in the integrated zener diode according to the invention and on the interface between the epitaxial layer 5 and the substrate 4, there is provided a buried layer of the other conductivity type, hence of the same conductivity type as the epitaxial layer 5, with this layer containing a recess below the emitter E.sub.2 of the load transistor T.sub.2. Whereas the buried layer 8 below the base zone B.sub.1 of the further transistor T.sub.1 serves to reduce the collector spreading resistance, this layer has been omitted below the emitter zone E.sub.2 of the load transistor T.sub.2 where it would otherwise affect the minority charge carrier current.

In addition thereto, the planar embodiment of the integrated zener diode according to the invention as shown in FIG. 2, comprises a surrounding insulating zone 9 of the same conductivity type as that of the substrate, which extends through the epitaxial layer 5. On one hand, this zone serves the purpose of contacting the emitter zone E.sub.21 of the further transistor T.sub.1, via the contact layer 10, to the substrate 4. On the other hand, this insulating zone safeguards that all pn-junctions of the integrated zener diode remain protected by the surface protecting layer 11. Because after splitting or dividing the semiconductor wafer, the lateral junction between the substrate 4 and the epitaxial layer 5 would otherwise end at a surface disturbed in its crystal lattice.

Of course, the integrated zener diode according to the invention may also be realized in mesa form, as instead, the place of the insulating zone 9 will be taken by the circumferential area of a mesa carrying the contacting layer 10 on an insulating protective layer.

For effecting the above mentioned fine selection, still further emitter zones, such as E.sub.31, of the further transistor T.sub.1 are preferably provided which are contacted with the emitter zone E.sub.2 of the load transistor T.sub.2 in accordance with the respective type to be manufactured. The fine adjustment in connection with selecting the types, is carried out via the setting of the surface area relationship of the total surface area of all emitters connected to the emitter zone E.sub.2 of the load transistor T.sub.2 in relation to the surface of the emitter zone E.sub.21 of the further transistor T.sub.1, which is contacted to the collector C.sub.2 of the load transistor T.sub.2. In practice, this will result approximately in a variation of the zener voltage of about 0.8V when changing this surface area relationship by the factor 4.

However, the coarse adjustment is carried out during the base diffusion via the surface concentration. This surface concentration, in fact, is determinative of the breakdown voltage of the emitter zones of the further transistor T.sub.1 as connected to the emitter zone E.sub.2 of the load transistor T.sub.2 and which, unlike the emitter zone E.sub.21 as connected to the collector zone C.sub.2 of the load transistor T.sub.2, are operated in the reverse direction.

It is considered an advantage that the differential resistance of the integrated zener diode according to the invention is chiefly dependent upon the current dependence of the current gain factor of the transistors, and not upon the "zener voltage" of pn-junctions operated in the reverse direction. From this there results the advantage of obtaining a differential resistance which is reduced by about the factor 3, as compared to conventional, non-integrated zener diodes.

While the principles of this invention have been described above in connection with specific apparatus, it is to be understood that this description is made only by way of example and not as a limitation on the scope of the invention as set forth in the objects and features thereof and in the accompanying claims.