US 4,025,901 AGrant
Database Instruction Find Owner
Issue Date:1977-05-24
•10 Claims
•35 Drawing Sheets
Abstract
One of a series of hardware/firmware primitives is disclosed for converting a general purpose digital computer into a database machine. The invention comprises a hardware/firmware implemented machine instruction called the find owner instruction, which fetches a set descriptor, which along with a base register BR, allows access to the owner pointer of a member record. The address of the owner record is then loaded into a register or registers.
Metadata
Assignee
- Honeywell Information Systems, Inc.
Inventors
- Charles W. Bachman
- Benjamin S. Franklin
Application Information
Application Number:US 5884349
Filing Date:1975-06-19
Priority Date:1975-06-19
Art Unit:237
Classifications
IPC:
G06F 920G06F 916G06F 1300
Field of Search:
340445444172.51
Patent Drawings (35 sheets)
Description
BACKGROUND
1. Field of the Invention
This invention relates generally to computer systems and more particularly to an improved digital computer in the area of database operations.
2. Description of the Prior Art
Electronic computers have grown from first generation hardware characterized mainly by vacuum tubes, to second generation hardware characterized by transistors, to third generation hardware characterized, in the main, by integrated circuits. Along with these different generations of hardware there were different generations of software, wherein first generation software was characterized mainly by machine language, assemblers and subroutines, and second generation software was characterized by high level languages, monitors and micro-assemblers. Third generation software is characterized by operating systems, on-line real-time systems, multiprogramming systems, and database management systems.
First generation hardware in combination with first generation software, and also the second generation hardware in combination with second generation software were primarily oriented toward batch processing where jobs were executed primarily in serial fashion. Moreover, the third generation of hardware/software systems are also batch process oriented; however, because of the advent of multiprogramming, several jobs may be executed in parallel rather than serial, and permits the acceptance of input information for processing as it is generated.
The fourth generation system will typically be classified as a communication and control system capable of widely diversified processor applications, and will be stimulated primarily by transmitted data rather than by batch programs (i.e. system control will be established primarily by input rather than by operator action) wherein submission of information will generally be in real-time.
In the evolution of the above generations of computer systems, a major requirement was to develop effective methods for accessing the databases of the computer systems. In the development of system databases, the initial result was the growth of many different databases for each use. As a result of this growing number of databases, problems were encountered in excess storage requirements and in redundant data storage which aggravates the problem by having redundant data being updated at different times correctly in one spot and incorrectly in another spot. Steps were taken to correct these problems by integrating the many databases of a system into one single database. The Honeywell Integrated Data Store (IDS) was an example of a system designed to alleviate these problems. The Integrated Data Store was composed of one central database which could be used, for example, by the inventory control system, the internal auditing procedures and payroll procedures for accessing their relevant data in the database. In this central integrated database, there would be a single record describing information which was common to several functional needs. For instance, inventory control and internal auditing would access the number of a given part in the warehouse.
Effective techniques using integrated databases were evolved through continually improving software techniques. The set concept is a technique which allows access to records in the integrated database on the basis of relationships between records. A typical relationship would be, say, all of the employees in a particular department, such as the manufacturing department. The manufacturing department would be described by what would be called an owner record and the employees in the department would be described by what would be called member records. The set which describes a relationship such as membership in the department could then be accessed through the owner record, which allows the software to obtain all of the member records and thus, for instance, print out all of the employees in the department.
At this state of development the integrated data store had solved some of the pure data problems mentioned above, i.e. redundant data in different databases and the problem of updating multiple copies of records. The problem had been solved by one single record which therefore allowed a reduction in data storage size and a single copy of data. Other problems in using databases still remain in the performance areas. The set concepts represented new techniques of utilizing the computer and henceforth there were no specialized hardware instructions which existed on current central processors to aid these new techniques. As a result, a set operation like find the first member of the set would be implemented in the software through a series of standard machine instructions such as add, load, stores, etc. The result was a long execution time for the rather simple set operations of find first member, insert a record in a set, and the other set operations.
What was needed was a database system which both solved the traditional data problems as had already been solved in the integrated data techniques using set operations and also an efficient database system in terms of execution time and other system performance parameters. To effect this specialized hardware/firmware supported instructions were needed to assist in the set operations. For instance, a single instruction to a database address of a member record's owner record (member and owner records described infra) in a register would allow execution in a much smaller period of time than the series of 5 to 10 extended machine instructions to perform the same operation in a traditional machine.
OBJECTS OF THE INVENTION
It is a primary object of the invention to provide an improved general purpose digital computer.
It is another object of the invention to provide an improved general purpose digital computer having improved performance of database management operations.
It is still a further object of the invention to provide a hardware/firmware instruction that loads the database address of a member record's owner record into a register or registers.
It is still a further object of the invention to reduce the number of instructions in user and operating system programs.
SUMMARY OF THE INVENTION
The foregoing objects are achieved according to one embodiment of the invention by providing one of a series of hardware/firmware implemented instructions that fetches a set descriptor, which along with a base register BR, allows access to the owner pointer of a member record. The owner pointer is converted to a segmented address according to its pointer class, and then the segmented address is loaded into the base register BR. If the pointer is a part of a database type record, the pointer is also loaded into an index register.
BRIEF DESCRIPTION OF THE DRAWINGS
The novel features which are characteristic of the invention are set forth with particularity in the appended claims. The invention itself, however, both as to organization and operation together with further objects and advantages thereof may best be understood by references to the following description taken in conjunction with the drawings in which:
FIG. 1 is a block diagram of a multiprogramming system utilizing the invention.
FIG. 2 is a schematic representation of various hardware structures utilized by the invention.
FIG. 3 is a legend of terms used for reserved areas of storage in registers depicted in FIG. 2.
FIG. 4 is a schematic diagram of a process control block of a machine utilized by the invention.
FIG. 5 is a schematic diagram of a system for addressing a process control block.
FIG. 6 is a schematic diagram of the system base of a computer system utilizing the invention.
FIGS. 7A and 7B are schematic representations of a stack segment and a stack frame of a computer system utilizing the invention.
FIG. 8 is a schematic diagram of a system for addressing G-segments and in particular the queue of processes in the G-0 segment of a computer system utilizing the invention.
FIG. 9 is an exploded schematic diagram of a G-0 segment illustrating queue of processes and process linking of a computer system utilizing the invention.
FIGS. 10A through 10L are block diagrams of structures in the PCB.
FIGS. 11A through 11R are block diagrams of structures in the system base.
FIG. 12 is a schematic diagram of addressing schemes of user and system segments utilizing the system base and PCB structures.
FIGS. 13A through 13C are schematic diagrams of the control unit of the invention.
FIGS. 14A through 14I are flow diagrams of the dispatcher unit in firmware of the computer system utilizing the invention.
FIGS. 15A through 15H are diagrams of the records and their pointers used in the set instructions.
FIGS. 16A through 16C are diagrams of the database page format and the descriptors describing those pages.
FIG. 17 is a flow chart of the firmware used to locate a database page in main memory.
FIG. 18 is a logic block diagram of a hardware mechanism to locate a database page in main memory.
FIGS. 19A and 19B are diagrams of the descriptors describing sets and records used by database instructions.
FIGS. 20A through 20F are diagrams of the instruction formats used by the database instructions.
FIGS. 21A through 21E are the flow diagrams of the find owner database instructions in firmware/hardware.
FIGS. 22A through 22D are logic block diagrams for a hardware find owner database instruction.
I. INTRODUCTION
A. Scope and Organization of the Disclosure:
The environment employed for the find owner database instruction in a large scale computer are necessarily complex and are typically found in the Honeywell Series 60 computer. Moreover, a full appreciation of the teachings of the present invention can be obtained only if the reader has some familiarity with the environment in which such instrumentalities reside. For this reason, it is desirable to at least briefly explore the general architecture of a typical large scale data processing system of the type in which the principles of the present invention may be utilized to advantage. It is also desirable to first establish and understand the basic concepts of which the present invention is based.
The database set concept unifies several techniques (table, list, chain, ring, file and field array) which have been in common usage for most of the history of the computers, primarily in programming. (This concept is a specialization of the more general mathematical set concept from which the Data Structure Set gets its name and many of its properties. In this disclosure the word "set" will always be used in the data structure and not the mathematical sense).
Many systems support the set concept, but only in software. In the database management area, the Honeywell Integrated Data Store (IDS) system pioneered broad usage of the set concept to process complex manufacturing and banking problems. IDS uses the chain (ring) form of the set implementation. These basic concepts are implemented in hardware/firmware and incorporated in existing machines to produce a new and improved digital computer.
The set is one of three complementary concepts (record, field and set) needed to build and store data structures which closely approximate their natural world counter-parts. If the natural world is considered in terms of the entities that exist, the attributes which describe them, and the relationships which associate them, then the equivalent information systems concepts are: record, field, and set, respectively. In a simple example taken from a school situation, the entities would be the teachers and the children. Some of the attributes of a teacher are "name", "grade-level," and "classroom." Some of the attributes of a child are "name," "age," "parent-name." A relationship exists between teachers and children. In an information system model of this natural world situation, two classes of records (one for teachers, one for children) would be created. In each teacher record there would be a field that stores the teacher's name, another for the grade-level and another for the classroom number. Each child's record would have a file for the child's name, another for his age and yet another for his parent's name.
The information system could tie each child's record to his teacher's record in one of several ways which have been selected to implement the set concept. This might be done by physically placing all the child's records after their teacher's record array in the file. This is called a table or record array. The present embodiment incorporates the chain (ring) implementation technique of the set concept. In this form the owner record contains a pointer to the first member record. Each member record in turn contains a pointer to the following member record. The last member record of the set contains a pointer back to the owner record. Variations are allowed which provide the owner record, or the owner and all the member records with additional pointer fields to hold the address of the prior record and possibly a pointer to the owner record for member records.
The data structure set concept thus described is a refinement on the mathematical set concept, i.e. in the data structure set the set definition is embodied in the instance of the "owner" roll. Set membership is embodied in the instance of the "member" roll. Records may concurrently have many rolls as owners and members of different sets. This property permits the creation and manipulation of complex structures which model the complexity of the real world. In this refinement of the mathematical set concept one can go reversibly either from owner as definition to members or from any member to owner to re-establish the set definition.
For data structure sets, the set definition is normally based upon the value of some field or fields within the owner record while the membership in the set is re-established in the computer by the matching value of an equivalent field or fields within a potential member record. Advantage is frequently taken of this phenomenon by removing the field from the member records which carry the matching data and depending upon the owner record for reconstruction.
In the school example above, it was said that a teacher has the role of "owner" of a teacher/children set. To extend this example, we will recognize that in most schools the relationship between teacher and child is not a simple relationship (1:n) but a rather complex relationship (m:n) as the children have different teachers for different subjects. This complex relationship of teacher:child may be transformed into a new relationship entity, "pupil," and two simple relationships; teacher:pupil and child:pupil. The teacher has many children as pupils of her class and, as a pupil, the child has many teachers. The new "pupil" entity has the attributes "subject" and "hour" which serve to describe and differentiate one relationship entity from another. A child may have the same teacher for several subjects.
The data structure set concept has four basic properties:
1. A set has one, only one, and always one record in the owner roll.
2. A set has zero, one or more records in the member roll and the number varies with time.
3. Any record may be the owner of zero, one, or more sets concurrently.
4. Any record may be a member in zero, one, or more sets concurrently and thus simultaneously owned by several owner records. Each record may appear only once as a member of a particular set. Member rolls do not interfere with the owner rolls.
The notion of "next" and "prior" are important concepts to procedural algorithms which are basic to problem solving in a storage program computer. In addition to the procedural limitation of handling one record at a time, there are more important simplifying consequences to an algorithm if the member records within the set can be delivered to it in a predefined data value ordered sequence or a time insertion ordered sequence (FIFO, First-In-First-Out or LIFO, Last-In-First-Out). The notions of "first" and "last" are vital to starting and stopping the iterative execution of data algorithms. Thus the ordering of members in a set is a prerequisite to rational manipulation of the set.
The primary motivation of associating records into sets within a file is to model the natural world relationships and to assist in the accessing of selected records within the file that represent some particular relationship. The set access methods fall in between and complement the more traditional access methods. They are listed in Table I.
The first four access methods are primarily used in transaction and inquiry processing, where there is a need to determine the recorded status of a particular entity, a related group of entities, or to update their recorded status. The File Sequential Access Method is primarily used for periodic batch file updating and report generation. It is possible for the same record to be accessed by all five methods as the occassion may require. Similarly, it is possible to use these access methods in combination to achieve a particular effect.
Taking the example given above, a teacher's record might be retrieved by the Data Key Access Method and then all of her pupil's records could be retrieved by Set Member Access Method. For each pupil record, the child's record may be retrieved with the Set Owner Access Method. Alternately, retrieval might start with Data Key Access to the child's record and then access all of the child's pupil records and hence the teacher's records. The basic retrieval opportunities derived from the set are given in Table II below.
There is a set of primitive operations which apply to sets. These are complementary to the primitive operations on records and fields which are better known. The collection of primitive operations on sets and the complementary primitive operations for records and fields compose what are known as the manipulative facilities which are a collection of hardware/firmware instructions by which a user accesses, modifies, moves, deletes, etc., the data with which he is working. This collection of primitives (i.e. hardware/firmware instructions) can be subdivided into operations with respect to fields (i.e. data items), records, sets, and procedure logic control.
The following group of hardware/firmware instructions provide for manipulation of data within fields. It is assumed the field descriptive information (e.g. size, location, recording mode) that is needed for an operation to be performed is carried as part of data descriptors associated with the operation. The operations included in this group are, for example: move, compare, hash, add, subtract, multiply and divide.
The following group of hardware/firmware instructions provide for both direct and serial access processing of data. These provide for the creation of a data record, its subsequent retrieval, modification, testing and destruction. The record firmware/hardware instructions are: create record, destroy record, find direct record, find serial record and test record type.
The following group of set hardware/firmware instructions provides the substance of conventional data processing and the building blocks for advanced database and message management systems. They provide for the creation, access to, manipulation and testing of sets. The hardware/firmware instructions are: insert record, remove record, find relative record, (find first, find last, find next, find prior, find ith), find owner record, test set for empty, test member inserted, initiate owner record, and initiate member record.
The following group of base register hardware/firmware instructions provide the determination of and modification of current process status relative to the database access. The hardware instructions are: unload base registers, nullify base registers and the previously mentioned "find" instructions which load a base register.
As well as being used to organize and provide access to records in an application database, sets can also be used in a great variety of system software areas. Tabulated below are a list of areas of system software and for each is enumerated some usages in that area of the set concept. This list is intended to be illustrative of obvious usages and there is no intent to be complete.
1. Data Base Systems
a. Index construction (index sequential and index random)
b. Data Description structures
c. Shared access control lists
d. Process responsibility structures
2. File Systems
a. Catalog construction
b. Access rights control
3. Message Systems
a. Construction of mailbox indexes
b. Queueing Messages
c. Accessing Multi Element Messages
4. Programming Systems
a. Controlling program libraries
b. Text editing
c. Program control structure
d. Symbol reference and symbol definition structures for binding
e. Intermediate program form for compilation
5. Operating Systems
a. Queues of jobs
b. Resource allocation tables
c. Deadly embrace detection
d. Queues of processes waiting on events (I/O completion, timer)
e. Dispatching queues
1. GENERAL DISCUSSION
The invention operates typically in the hardware system environment, hereinafter described, coordinated by an operating system. Referring to FIG. 1 the subsystems are the processor subsystem 101, the storage subsystem 102, and one or more --up to 32-- peripheral subsystems 103. The processor subsystem contains a central processing unit (CPU) 104 and up to four input/output control units (IOC) 105. Each peripheral subsystem consists of a peripheral control unit (PCU) 106, a number of device adapters (DA) 107, and up to 256 peripheral i/o devices 108. The storage subsystem 102 consists of one to four semiconductor memory modules of 32 to 512 kilobytes each.
In the processor subsystem 10, the CPU 104 performs the basic processing operations for the system, and interfaces with memory 102. The IOC 105 controls all information exchanges between the storage subsystem 102 and peripheral devices 106.
A. CENTRAL PROCESSING UNIT
The CPU includes a main memory synchronizer 109, a buffer store 110, various elements that comprise the computational unit 111, and optional emulation facilities 112. The main memory synchronizer 109 resolves conflicts for the use of main memory among the computational unit 111, the buffer store 110, and the IOC 109. Conflicts are resolved on a priority basis: the IOC has the highest priority followed by memory writes (from the computational unit) and then memory reads (into the buffer store). The main CPU also includes the address control unit ACU 131 which controls main memory addressing and the associative memory AS 132 used to store most recently used addresses of main memory. The buffer store 110 is a small high-speed buffer memory that reproduces a selected region of main memory and interfaces with the computational unit to decrease average memory access time. During each memory read, both the buffer store and main memory are accessed. If the information to be fetched is already in the buffer store, the main memory read is terminated and the information fetched from the buffer store. Otherwise the main memory 102 is read. Every time this is done, the CPU 104 fetches 32 bytes that contains the desired information. This information remains in the buffer store for future memory references. Since the buffer store is transparent to software, the program controlling the computer at any given moment cannot determine whether the information it is processing has been fetched from the buffer store or from main memory.
The computational unit 111 performs all data processing and address generation within the CPU. A typical control store 130 within the computational unit (see a book entitled Microprogramming: Principles and Practices, Samir S. Husson, Prentice Hall, Inc.) contains firmware which initializes the system, controls the CPU 104 and IOC 105, and decodes an instruction set. Optionally the control store may provide scientific instructions, test routines, emulation packages, or special purpose features which extend the capabilities of the processor subsystem.
As an option, the CPU provides emulation of systems other than the instant system. Emulators 112 are components of firmware, software, and in some instances hardware.
B. INPUT-OUTPUT CONTROL UNIT
The IOC 105 portion of the processor subsystem provides a data path between any peripheral subsystem 103 and the storage subsystem 102. This path allows for the initiation of peripheral commands and controls the resulting data transfers. An IOC can typically handle up to 32 channel control units (not shown).
C. PERIPHERAL SUBSYSTEMS
In a peripheral subsystem 103 on FIG. 1 the PCU 106 is a stand-alone microprogramming processor that relieves the load on the CPU 104 by controlling the i/o devices 108 during i/o operations. The PCU does this by executing instructions contained in a channel program. This program results in arithmetic, logical, transfer, shift, and branch operations being performed in the PCU. There are several kinds of PCU's according to the kind of device each controls: i.e. unit record, mass (disk) storage, magnetic tape, communications, etc.
Device adapters 107 mediate between every PCU and the devices it controls. Each contains the dedicated firmware and logic necessary to implement communication with a particular type of device. Depending on the type, a DA 107 controls one or several devices.
The major functions performed by a peripheral subsystem 103 are as follows:
1. Transforming CPU instructions into a series peripheral device.
2. Packing and unpacking data in the form needed by the CPU or the appropriate peripheral device.
3. Keeping the CPU informed of the status of the subsystem and of the devices under its control.
4. Independently initiating and processing error and recovery procedures.
5. Allowing on-line diagnosis of a device without disturbing the device-sharing capabilities of the associated peripheral processor.
The PCU resolves conflicts for main memory between devices attached to it; however, the IOC resolves conflicts between PCU's.
D. STORAGE SUBSYSTEM
Each memory module 1-4 is 4 or 8 bytes wide. The number of modules, their size, and the data path width may vary according to size of computer. Memory modules are four-way interleaved in such a way that the four modules are accessed sequentially (module 1 contains the first 8 bytes, module 2 contains the second 8 bytes, etc.). Interleaving decreases the number of conflicts for access to main memory and thereby decreases the average memory access time. Memory is reconfigurable in case of failure; i.e., blocks of memory within a module may be removed without destroying contiguous addressing.
Main memory 102 consists of a capacitive storage medium in the form of metal oxide semiconductor (MOS) chips. This medium operates on the refresh principle to maintain information. Each memory location is typically refreshed at least once every 2 milliseconds; the design ensures that few conflicts occur between refresh timing and memory accesses. (In cases of conflict, refreshing takes precedence).
An area at the beginning of main memory is reserved for hardware and firmware. The upper limit of this area is defined by the content of a boundary address register (BAR - to be later described) which is visible to the system software. The BAR content is set at system initialization time. The memory area below the address specified in the BAR can contain IOC tables which define the configuration of the peripheral subsystems, firmware to control the CPU, or microprograms and tables for emulation. The size of the area below the address specified in the BAR depends on the system configuration. Whether microprograms are in main memory or control store depends on the system configuration and the applications run on the system.
2. BASIC MACHINE STRUCTURES
There are typically three basic data structures utilized in this hardware: data formats, software visible registers, and the instruction formats.
A. DATA FORMATS
Information is transferred between memory and the CPU in multiples of 8 parallel bits. Each 8-bit unit of information is called a byte. Parity or error correction data is also transferred with data but cannot be affected by software. Therefore, in this patent specification the term data excludes the associated parity or error correction data.
B. BYTES
Bits within a byte are numbered 0 through 7 from left to right. Bytes are processed separately or in groups. Two bytes constitute a halfword, 4 bytes a word, 8 bytes a doubleword, and 16 bytes a quadword. These are the basic formats for all data, including instructions.
C. DATA REPRESENTATION
All data are in binary form, but may be interpreted as binary, decimal, or alphanumeric. Data bits are interpreted in groups of four, as binary coded decimal data; eight as alphanumeric, or 16 to 64 as binary digits. The latter are interpreted as signed, fixed, or floating-point numbers in binary notation. Any number of contiguous bits up to a doubleword may also be manipulated as a string. The alphanumeric character set is represented in EBCDIC. ASCII is supported as an alternate exchange code.
D. BYTE ADDRESSES
Byte locations in main memory are consecutively numbered starting with zero; each number is the address of the byte. A group of consecutive bytes is said to be halfword-, word-, doubleword-, or quadword-aligned, if the address of the left byte in a group is a multiple of 2, 4, 8, or 16, respectively. Whenever a halfword, word, doubleword, or quadword is so aligned, that unit can be fetched from that address. The location of data in main memory is specified by a data descriptor which is accessed indirectly during address development. (See U.S. Pat. application No. 425,356 filed Dec. 17, 1973 entitled "Apparatus for Developing an Address of a Segment within Main Memory and an Absolute Address of an Operand within the Segment" and assigned to the same assignee as the instant application and issued into U.S. Pat. No. 3,938,096 on Feb. 10, 1976.
E. VISIBLE REGISTERS
There are 33 user-visible registers in the CPU 104 FIG. 1 whose contents collectively define the state of the CPU. There are four types: (See FIG. 2).
1. general registers
2. base registers
3. scientific registers (optional)
4. miscellaneous registers
F. GENERAL REGISTERS
General registers (GR) 201 FIG. 2 are used to manipulate fixed-point binary numbers and bit strings. There are typically sixteen 32-bit general registers in the CPU 104 --GR0 through GR15. General register GR8 through GR15 are also usable as index registers. When used as index registers, they are herein called X0 through X7; Indexing is performed using the 32-bit two's complement integer contained in a register.
G. BASE REGISTERS
Base registers (BR) have the same format as instruction counters IC and stack registers 202-203. Base registers are used during address computation to define a part of memory. There are typically eight 32-bit base registers, BR0 through BR7.
H. SCIENTIFIC REGISTERS
Scientific registers (SR) are optional equipment for computation with floating-point binary numbers. There are typically four 8-byte scientific registers which are referred to as SR0 through SR3. Scientific registers have the format 204-205 of FIG. 2.
I. MISCELLANEOUS REGISTERS
There are five other registers:
instruction counter -having format 202-203;
status register -having format 207;
stack register (called the T register);
boundary address register -having format 202-203; and
hardware control mask register -having format 208.
The instruction counter (IC) is a 32-bit register that contains the address of the instruction being executed. The status register (STR) 207 is an 8-bit register that records facts about the procedure currently being executed, for example, whether an underflow was caused by the most recent operation. The stack register also known as the T-register is a 32-bit register that contains a pointer to the top of a pushdown stack associated with the currently active procedure. Stacks to be described infra provide a work space, and a mechanism for saving local variables and preserving procedure entry, and return information. The boundary address register (BAR) 206 is a 28-bit register which specifies the lowest absolute main memory address accessible by software. This register is loaded during system initialization and can only be read by software. The hardware control mask register 208 is an 8-bit register which records machine condition information.
J. INSTRUCTION FORMATS
There are approximately 200 instructions although more or less may be utilized. Each instruction is one of four different lengths but always an even number of bytes long. Instructions are stored in consecutive storage locations. The address of the leftmost byte is a multiple of 2, and is the address of the instruction.
The eight most significant bits (and in some cases bits 8 through 11 or 12 through 15) of an instruction represent the operation code, while the remaining bits represent one or more operands. An operand may be a register designator, displacement designator, address syllable (logical address), literal value, immediate literal value. The type and number of operands are determined by the instruction format.
3. SYSTEM ORGANIZATION
A. JOB STEP AND TASK
Work to be performed by the computer system is defined externally by a series of job steps via a job control language. A job step is a unit of work to which hardware resources are allocated. Typically a job step consists of several tasks. A task is the smallest unit of user defined work consisting of a stream of instructions executed without parallelism.
B. PROCESS
The user-visible concepts of task and job step are represented in the hardware by a process and process group, respectively. A process is defined as an ordered sequence of instructions which can be executed asynchronously by the CPU (i.e., several processes can be active and sharing resources, but only one process is actually running at any one instant). A process group is a related set of processes necessary to perform one job step.
C. PROCESS CONTROL BLOCK AND SYSTEM BASE
Because processes can relinquish CPU control at various points during their execution, a storage area in main memory is made available to a process to save CPU status. This status information is utilized to precondition the CPU before a process regains control of the CPU.
The storage area assigned to a process is called a process control block (PCB) 400 on FIG. 4. The data contained in a PCB include the addresses of memory areas (address space) assigned to the process, the contents of all pertinent registers, and the state of the process. Thus a PCB serves as a temporary storage area for information necessary to start or restart a process without any information loss. Each PCB is visible to the hardware and can be addressed by the operating system via a set of hardware tables developed during system initialization and modified during system operation (FIG. 5).
There is an absolute main memory area which is referred to as the system base (FIGS. 5 and 6). This area is developed by firmware and is accessible via the base address register (BAR) 501 which can be read but not written. The system base 502 contains a number of system attributes which include a job step number and a process group number (J, P) respectively for the currently running process. Another attribute in the system base is a pointer to a hardware defined data structure known as the J table 503. This table contains an entry for every job step presently in the system. Each entry in the J table 503 points to an associated P table 504 which is also a hardware defined data structure. This table defines a process group and contains an entry for every process in the process group. Each P-table entry points to a PCB 400.
Referring to FIG. 5 the J-table pointer 505 indexed by the J number via the arithmetic portion 506 of computational unit 111 (FIG. 2) provides access to a J-table entry 503. This entry contains a P-table pointer which when indexed by the P number via computational unit 506 provides access to a P-table entry 504. The P-table entry contains a pointer 507 to the PCB of the current running process. Thus the operating system can access the active PCB using the contents of the BAR 501 and can access any other PCB given its associated (J, P) logic name.
D. MEMORY SEGMENTATION
In a multiprocess environment, such as herein described there are many processes in memory at any given time. These processes vary in size and demand for memory which causes a memory allocation problem. The hardware herein described in cooperation with an operating system (not shown herein) solves the problem by dynamically allocating memory space. Due to the random nature of memory requirements, memory is allocated in variable size segments and the memory allocation can be restructured during process run time. Thus, a process may be allocated a number of noncontiguous memory segments. This memory allocation method is called segmentation.
Segmentation presents an additional problem in that memory addresses have to be modified whenever part or all of a process is relocated. To alleviate this problem the system herein described provides a technique whereby addresses used by a process are logical rather than absolute main memory addresses. These logical addresses are used to develop absolute addresses.
Segmentation also allows each process to access its own or related memory segments via a system of segment descriptors. By accessing a segment descriptor, a process can obtain the address of a segment. Segment descriptors are contained in main memory and are maintained by the operating system.
Each process may have access up to 2068 memory segments. Normally, this would require an equal number of segment descriptors per process. However, since segments can be shared, the operating system groups segment descriptors into segment tables. This grouping is based on accessability by one process (task), a process group (job step), or globally (system wide). Each process may have up to 15 segment tables associated with it. This technique requires only one segment descriptor for each segment which can be accessed by a process via a segment table. Thus, the memory space required for segment descriptors is decreased; memory updating during relocation is reduced; and some program protection is provided. (The main mechanism for program protection is the ring system. See U.S. Pat. application No. 424,239, filed Dec. 12, 1973, entitled "Ring Checking Hardware" and now issued into U.S. Pat. No. 3,916,385 on Oct. 28, 1975.)
A process must be able to determine which segments it is allowed to access. Accordingly, the system provides a process with two segment table word arrays (STWA). These arrays contain the addresses of all segment tables accessible to a process. There are two segment table word arrays per process because there are two segment sizes, large and small. Large segments have a maximum size of 2.sup.22 bytes while small segments have a maximum size of 2.sup.16 bytes. All segments vary in size in 16-byte increments up to the maximum. A system can typically accommodate up to 28 large segments and 2040 small segments.
Segment table word arrays may be relocated by the operating system; therefore, a process must know the absolute address of its associated STWA's. The PCB for any process contains two words which contain this information which are known as address space words ASWO-1 on FIG. 4. Each word points to a segment table word array STWA. The operating system updates the contents of the ASW's whenever the associated STWA's are relocated. Working down the chain of pointers and decoding the segment descriptor is a firmware function and thus once initiated is not visible even to the operating system.
Segmentation defines over 200 million bytes of address space as being available for processes. This number exceeds the capacity of main memory; therefore, a secondary storage (magnetic disk or drum) is used in conjunction with main memory. The operating system creates the illusion that the system has a much larger main memory than is really available. This concept is called virtual memory.
At any given time, a defined segment may or may not be physically in main memory. The contents of a segment descriptor indicates whether or not the associated segment is in main memory. The hardware detects any attempts by a process to access a segment not in main memory and notifies the operating system. The operating system causes the desired segment to be loaded into main memory from secondary storage. Then the operating system places the segment's memory address in the segment descriptor which is the only place where the absolute address of a segment can be found. This operation is invisible to the process and thus it is not aware that the segment was not in main memory or that it may have to be relocated in main memory. (For details on memory segmentation see U.S. Pat. application No. 425,356, filed Dec. 17, 1973, referenced supra.
The computer system herein described provides data and procedure protection by preventing processes from interferring with each other or sharing each other's address space in an unauthorized manner. This protection is accomplished by restricting addressability via memory segmentation and by a ring system.
The segment tables isolate the address space of the various processes in the system. Processes always use a segmented address during execution. A segmented address consists of a segment number and a relative address within the segment (see above referenced application on Segmented Address Development). The hardware checks that the address used by a process is part of the address space assigned to the process. If the address is outside the prescribed address space, an exception occurs. A process cannot refer to data within the address space of another process because the hardware uses the segment tables of the referencing process. Thus, there is no possibility for a process or process group to reference an entity belonging to another process group.
Generally, overlap in address space in the system occurs for those segments shared by all processes. These public segments are created by system programs which check to insure against address conflicts. Thus, segmentation protects user programs against each other and protects the operating system against user programs.
Segments shared by several processes are not protected from misuse by one of these processes. To solve this problem, a ring system is utilized whereby procedure and data segments are grouped into a four-class hierarchy. The four ring classes are numbered 0 through 3. Each ring represents a level of system privilege with level 0 (the innermost ring) having the most privilege and level 3 (the outermost ring) the least. Every procedure in the system has a minimum and a maximum execute ring number assigned to it which specifies who may call the procedure. A procedure is a subroutine which is capable of calling other procedures and passing parameters to them:
The general rules of the ring system are as follows:
1. A procedure in an inner ring has free access to data in an outer ring. Conversely a procedure in an outer ring cannot access data in an inner ring.
2. A procedure in an outer ring can branch to a procedure in an inner ring, but the reverse is not allowed.
3. Each segment containing data is assigned two ring values, one for read (RD) and one for write (WR). These ring values specify the maximum ring value in which a procedure may execute when accessing the data in either the read or write mode.
Each time a procedure instruction is executed, the procedure's ring number (effective address ring, EAR) is checked against the ring numbers assigned to the segment containing the referenced data. The EAR is the maximum number of process ring numbers in the instruction counter and all ring numbers in base registers and data descriptors found in the addressing path. Access to the data will be granted or denied based on a comparison of the ring numbers. For example, if a system table exists in a segment having a maximum read ring value of 3 and a maximum write ring of 1, then a user procedure executing in ring 3 may read the table but may not update the table.
By predesign, rings 0 and 1 are reserved for the operating system and rings 2 and 3 are reserved for the user. Ring 0 contains those segments critical to total system operation. Ring 1 contains the bulk of the system segments whose failure would not be catastrophic and would allow recovery. The user may utilize ring 2 for checked-out programs and ring 3 for programs being debugged.
F. PROCEDURE CALLS
The procedure call is an important function in the system herein described. Procedure calls are used to pass from one procedure to another; to allow user procedures to employ operating system services; and to achieve a modular structure within the operating system. A procedure call is effected by instructions and a hardware recognized entity called a stack (FIG. 7A).
A stack is a mechanism that accepts, stores and allows retrieval of data on a last-in-first-out basis. Stacks reside in special segments called stack segments. A stack segment consists of a number of contiguous parts called stack frames 701 (FIGS. 7A and 7B) which are dynamically allocated to each procedure. The first stack frame is loaded into the top of the segment and succeeding frames are loaded after it. The last frame loaded is considered the top of the stack. The T-register 702 locates the top of the stack for the currently active process. A virtual T-register exists in the PCB of all other processes in the system.
A stack frame 701 of FIG. 7B consists of three areas: a work area 702 in which to store variables, a save area 703 in which to save the contents of registers, and a communications area 704 in which to pass parameters between procedures. Prior to a procedure call, the user must specify those registers he wishes saved and he must load into the communications area the parameters to be passed to the called procedure. When the call is made, the hardware saves the contents of the instruction counter IC and specified base registers to facilitate a return from the called procedure.
Each procedure call creates a stack frame within a stack segment 701 and subsequent nested calls create additional frames. Each exit from one of these called procedures causes a stack frame to be deleted from the stack. Thus, a history of calls is maintained which facilitates orderly returns.
To insure protection between procedures executing in different rings, different stack segments are used. There is one stack segment corresponding to each protection ring per process. A PCB contains three stack base words which point to the start of the stack segments for rings 0, 1 and 2 associated with the process. The ring 3 stack segment can never be entered by an inward call; therefore, its stack starting address is not required in the PCB.
4. PROCESS MANAGEMENT AND SYNCHRONIZATION
The system herein provides for multiprocessing operations which are controlled by an operating system using a combination of software, hardware and firmware. Software creates and deletes processes within the system while hardware and firmware multiplex processes on the CPU. In addition, a combination of software, hardware and firmware provide for synchronization between processes.
Processes are normally, but not always, started and stopped at the initiation and termination of i/o operations, during related job handling, and at other times for purposes deemed necessary by the operating system. Therefore, a communications system is necessary to efficiently start and stop related processes and to pass information between them. The hardware system herein provides internal messages called semaphores to provide a communications link between the processes.
A. PROCESS STATES
A process can be in one of four possible states at any time: running, ready, waiting or suspended. The hardware recognizes these four possible process states and executes various firmware procedures to effect process dispatching, state changes and to maintain data structures based on a process's state. The PCB contains a state field which defines the current state of its associated process.
A process is in the running state when it has control of the CPU. This state involves supplying the CPU with an address space (segment tables) and a starting address. The CPU then executes instructions in the procedure segments of the process. The process name J table word (logical address) of the PCB for the currently running process is retained in the running process word (BAR +60) within the system base (FIG. 6). (Note: The system base shown in FIG. 5 is the same as that shown in FIG. 6, but with some details omitted.)
The ready state is equivalent to running state except that the process does not have control of the CPU because it has not been recognized by the CPU. A process in the ready state is in contention for the CPU with other ready processes and the running process.
A process is in the wait state when it cannot continue until a specific event occurs such as a message via a semaphore. A waiting process is not in contention for the CPU but it may be in contention with other waiting processes for the required event.
A suspended process is a process which has been stopped for a time by software and may be resumed later. The decision to stop and resume the process is external to the process. Thus, a suspended process is not active and therefore cannot receive notification of event occurrences and cannot utilize the CPU.
A process is suspended under the following conditions:
(1) By executing a Terminate instruction (as a result of having completed all its functions.)
(2) By execution of a Suspend instruction by the operating system.
(3) By the occurrence of an exception condition whereby control is transferred to the operating system.
B. PROCESS DISPATCHING
Processes move from one state to another voluntarily by action of the process while running or involuntarily by the actions of other processes. CPU firmware, known as the dispatcher, controls the transaction of processes between states. The dispatcher uses a set of queues (to be later described) to manipulate processes which are in the ready or the waiting states. Suspended processes are controlled by software.
Referring to FIGS. 6, 8 and 9, a ready or waiting process is represented by a PCB and a special queue entry called a process link. FIG. 9 shows an exploded view of contents of the GO segment 802, and contains process links 803a-803b and 803c-803g of active processes, and free process links 805a-805c of suspended processes. Each process link specifies the process name (J, P), the process priority and a pointer to the next process link in the queue. There are various types of queues such as wait queue 803a- b and ready queue 803c-g.
A hardware device similar to the J table, known as the G table, (FIGS. 6 and 8) contains pointers to all general (known system wide) segments 802- 802n. The first element, GO, of the G table 801 points to that segment 802 containing the dispatcher queues. A G-table pointer to the G table 801 is found in the system base 502 on FIG. 5. Also in the system base is an entry called the internal process queue word (IPQW) which identifies the head 805 of the ready queue 803c-803g in the GO segment 802.
Thus, the dispatcher can examine all ready processes processes by consulting the ready queue 803c-803g. When the currently running process changes states, the dispatcher removes the process link at the head of the ready queue and uses the J, P name to access its PCB. The process defined by the PCB then becomes the new running process.
Since more than one process may be awaiting on the same event, a quene of waiting processes 803a-803b exists for each event. Waiting processes are also strung together via process links 805 residing in the GO segment. A pointer to the head of a wait queue exists in a semaphore 903 (to be later described). A number of events exist for which a process may wait; therefore, there are a number of wait queues each of which has an associated semaphore 903, 904.
The number of processes ready or waiting varies dynamically. Thus, the number of process links required for the ready and wait queues also varies. This fact introduces a memory management problem for the dispatcher. The problem is solved by another queue called the free process link queue 805a-c. This queue links together all process links in segment GO that are not being used by the ready or the wait queues and can be used to extend a particular queue of ready or waiting processes. A pointer 901 to the head 902 of the free process link queue 805 resides near the beginning of the GO segment 802.
C. PROCESS SYNCHRONIZATION
Process synchronization is required to coordinate the activities of two processes working on the same task. The synchronization is achieved using semaphores 903-904 which are data structures residing in the address space of communicating processes. A semaphore is used to signal event occurrence and to handle queues of messages. An event in this context is anything observed by a process which may be of interest to some other process. The event may be the completion of an asynchronous operation or the availability of a resource.
A process uses two semaphore operations to signal an event occurrence. One operation sends a signal to a semaphore; the other picks up a signal from a semaphore. (The sending operation is often called a V-operation; the receiving operation is called a P-operation). The sending operation allows a process to send data or a signal that data are ready. The semaphore stores the signal until another process is ready to pick it up. Thus, the sending process is free to proceed, since it has sent the data. The receiving operation examines a specified semaphore and picks up the signal. If a signal is present, the receiving process continues executing. However, if there is no signal at the semaphore, the receiving process enters the wait state. The semaphore then serves as a pointer to the head of a wait queue. The process remains in the wait state queued at the semaphore until another process sends a signal to that particular semaphore. Thus, a semaphore can hold a signal until a process picks it up, or a semaphore can hold a process until a signal is sent to it.
Messages can also be passed from process to process. A message has the same present or not present quality as a signal plus additional information. Part of the information is supplied by hardward and part is supplied by the procedure of the process that sent the message. A message carries the process name of the sending process. Thus, many processes can send information through a single semaphore stamped with the sender's name.
A message semaphore may have a queue of messages waiting to be picked up by processes. As with signal semaphores, requirements for memory space increases and decreases thus presenting a memory management problem. Again, the problem is solved with a queue of free message links. These links reside in a known place in a segment that can easily be found when needed to supply or absorb message links.
Because semaphores and the queues built on them are shared by different processes, the total semaphore structure is protected. This is accomplished by hardware and software conventions that restrict access to any segment containing semaphores. Thus, semaphores must be in semaphore descriptor segments, some of which may be G segments (if system communications is necessary). However, all G segments (except GO) are semaphore descriptor segments.
Each semaphore descriptor contains a pointer to a semaphore. Semaphore addresses are developed via a semaphore descriptor, thus providing added protection for the semaphore. A semaphore segment can be addressed logically using a segment number and a relative location within the segment or directly using the G, D number.
E. PROCESS CONTROL BLOCK STRUCTURES
Referring to FIG. 4 there is shown the format of the process control block (PCB). The process control block 400 is a storage area in main memory made available to a process to save the CPU status. Addressing a PCB is performed as described supra in relation with FIG. 5. The PCB pointer 507 (FIG. 5) points to the process control block PCB at memory location 0 on FIG. 4. It will be noted that proceeding in a downward direction memory locations increase by 4 bytes whereas in proceeding in an upward direction from memory location 0 they increase by 8 bytes. The downward memory locations are considered positive from 0 whereas the locations in an upward direction from 0 are considered negative directions. The upward locations are optional and may or may not be included in the process control block; also locations 148 through 176 are also optional. (Note that the numerals under memory location specify the displacement in bytes from the 0 reference location of the process control block PCB and are not to be confused with the reference numerals commonly used to identify parts in a patent drawing). Starting at byte 0 up to but not including byte 16 there are stored four process main words PMW 0 through PMW 3 with each process main word PMW being four bytes in length. Process main word 0 occupies bytes 0 through 3 and is comprised of 4 parts: a capability byte, a priority byte, a state byte and a decor extension byte DEXT. Referring to FIGS. 10a through 10d there are shown details of process main word PMW 0, with further details of the capability byte 1001 shown on FIG. 10b. Referring to FIG. 10b, the first bit 1005 is the accounting mode bit for indicating whether or not time accounting functions are being performed for the process. When the accounting mode bit 1005 is set to binary 0 no time accounting function is being performed for the process: whereas when the accounting mode 1005 is set to binary 1, time accounting is being performed. The scientific mode bit 1006, when set to zero, indicates that saving of scientific register of the machine is not performed and the scientific register saving area located at bytes 148 to 176 on FIG. 4 does not exist in the process control block PCB. When the scientific mode bit 1006, is set to binary 1, the scientific optional feature exists and is being used in the process, and the scientific registers saving area is used to save the contents of the scientific registers when necessary. The code mode bit 1007 indicates whether or not a standard code set or compatibility code set is being used by the process, with a binary 0 in that position indicating that standard code set is being used; whereas a binary 1 in the third bit position 1007 indicates a compatibility code set is being used. The remaining of the bits of the capability byte are set to zero.
Details of the priority byte 1002 are shown on FIG. 10c. Referring to FIG. 10c the first four bits 1008 of priority byte 1002 is utilized to set the priority level of the process associated with that given process control block PCB. Each process is assigned one of 16 levels of priority which is used for ordering competing processes i.e. (a) for choosing the process to be run among ready processes, (b) for putting processes is queues. Priorities decrease from 0 to 15, and for a given priority level the FIFO (first in first out) rule is applied. The next 4 bits 1009 of priority byte 1002 are zeroes.
Referring to FIG. 10d details of the state byte 1003 are shown. A state byte is utilized to provide information with regard to the process associated with the process control block PCB 400. The active field bit A 1010 is set to binary 1 when the process is activated. The suspend field S 1011 is set to binary 1 when the process is suspended. The substate field SS 1012 is a 2 bit field and defines the following substates of the process: (a) when set to binary 00 the process is inactive; (b) when set to binary 01 the process is waiting in the queue of ready process (Q/PR/RDY); (c) when set to binary 10 the process is waiting on a semaphore in a queue of semaphores (Q/PR/S); (d) when set to binary 11 the process is being executed by the processor. The mid-operation field (MOI) 1013 is set to binary 1 when an interrupt happens and is taken care of during the execution of an instruction --i.e. before the completion of the process. The extended decor mode bit EXTD 1014 is set to 1 when the process is operated in an extended decor mode which is an emulation mode of the machine. Bits 1015 and 1016 are set to 0. The fourth byte of process main word PMW 0 contains the decor extension number and is utilized when the system is in emulation mode.
Process main word PMW 1 is stored in bytes 4-7 of the process control block PCB. Details of PMW 1 is shown on FIG. 10e. The status byte 1016 is the first byte in PMW 1 and stores the status register contents. The multiprocessor byte MP 1018 is significant in a multiprocessor architecture otherwise this field is zero. The second and fourth bytes of process main word 1 are the MBZ fields 1017 and 1019 respectively which must be zero for normal operation.
Process main word PMW 2 occupies bytes 8 through 11 of the process control block and is shown in more detail on FIG. 10f. Referring to FIG. 10f the field from bit 4 through bit 31 contains the local name SEG, SRA 1021 of the semaphore to which the PCB is linked when the process is either in the waiting or suspended states. The exception class and type field 1023 contains the class and the type of the interrupt-like exception which cause the process to enter the suspended state after an exception. The field from bits 4 through 15 is meaningless 1022 when a process is in a different state than those mentioned above.
Process main word PMW 3 occupies bytes 12 through 15 in PCB 400 and points to a decor extension table. Referring to FIG. 10g for details of PMW 3 the DETSZ field 1024 defines the number of entries in the table and if this field is zero no decor extension is allowed to the process. The DETA field 1025 is the absolute address of the decor extension table in units of 16 bytes and is significant only if DETSZ is not 0. The decor extension table is made up of DETSZ entries. Each entry is one byte size. The DEXT.sup.th entry of the table defines the capability of the process to operate in the decor extension mode DEXT. When the DEXT.sup.th byte is 0 the decor extension number DEXT is not allowed, whereas if the DEXT.sup.th byte is 1 the decor extension number DEXT is allowed. Values of DEXT other than 0 and 1 are illegal. (See FIGS. 10a DEXT number 1004).
Bytes 16 through 23 of PCB 400 contains 2 address space words ASW 0 and ASW 1 respectively and each ASW contains a pointer to an array of segment table words. Both ASW 0 and ASW 1 respectively have the same format shown on FIG. 10h. The size of the array of the segment table words is defined by the number of segment table words in an array and typically comprises six for ASW 0 and eight for ASW 1. The STWSZ field 1026 indicates the size of the array of the segment table words. The segment table word array field STWA 1027 contains the absolute address STWA of the array in units of 16 bytes --i.e. the absolute address of the array is 16 times STWA in bytes.
Bytes 24 through 27 in the PCB contain an exception word EXW shown in greater detail on FIG. 10i. The exception word contains a pointer (SEG, SRA) 1029 to an exception class table which defines the action to be taken following a process exception according to its class as stored in process main word PMW 2. (See FIG. 10f). The MBZ field 1028 of exception word EXW must be 0.
The stack word SKW located in bytes 28 through 31 of the PCB contains the value of the top of the T register of the stack of the process when the process is not running and is shown in greater detail in FIG. 10j. Referring to FIG. 10j, bits 0 and 1 define the TAG field 1030. The TAG indicates the type of descriptor by its contents and must be zero for SKW. Bits 2 and 3 of the SKW word contain the RING field 1031 which contains the ring number associated with the segmented address of the stack for protection purposes and in this case must be zero. Bits 4 through 31 contain the segment number SEG, and the segment relative address SRA 1032 and is a field which identifies the segment described in a segment table and the segment relative address within the segment. The stack word SKW is updated every time the process leaves the running state. It is used to restore the T register contents every time the process becomes running. In this last case the TAG 1030 and RING 1031 are tested to be zero, otherwise an illegal PCB exception occurs.
Bytes 32 through 35 of the PCB 400 contain the instruction counter content word ICW sometimes also referred to as ICC. Referring to FIG. 10k there are shown details of the instruction counter word ICW wherein the TAG field 1033 must contain binary 00 (i.e. values other than zero are illegal in the instruction counter). The current RING field 1034 occupying bits 2 and 3 defines the current ring number of the process to be used in determination of access rights to main storage. Bits 4 through 31 define the segment number and the segment relative address (SEG, SRA) 1035 which define the address of the next instruction to be executed.
The MBZ field in bytes 36 through 39 must be zero. (Note the MBZ field always indicates a field which must be zero). The MBZ word is tested every time the PCB is accessed from the name J, P. If it is not zero an illegal PCB exception occurs.
Stack base words SBW 0-2 occupy bytes 40-51 in the process control block 400. These words have the same format which is shown in greater detail on FIG. 10l. They are utilized during stack operations and whenever used their TAG field 1036 and RING field 1037 must be zero otherwise an illegal PCB exception occurs. Bits 4 through 31 contain the segmented address (SEG, SRA) 1038 of the first bytes of the stack segments for ring zero, 1 and 2 respectively.
Bytes 52 through 83 of the process control block 400 is a space reserved for the base registers saving area (8 words). Bytes 84 through 147 is a saving area which is utilized to save the values of all general registers (16 words). Bytes 148 through 179 is a saving area which is utilized to save the scientific registers (8 words).
Five double words are provided in the PCB 400 above the PCB zero address, for time accounting purposes when the accounting mode bit in the PMW 0 word is set. These words are located from PCB address minus 8 to PCB address minus 40. Each word contains a time or a time interval expressed in microsecond units in its first 52 bits with bits 52-63 filled with zeroes. The residual time out double word RTO (first 8 bytes above 0 in the PCB) contains the quantum of time which is actually spent by the processor on behalf of the process before a time out exception occurs. The RTO word is updated in the following way: each time the process exits the running state the process timer value is stored in the RTO word. Each time the process enters the running state, the process timer value is loaded from the RTO.
The running time accounting RUA double word at bytes 7 through 15 is a time counter which specifies the total amount of processor time a process was in the running state. The time accounted for is the time actually spent by the processor on behalf of the process exclusively. The RUA word is updated in the following way: each time the process exits the running state, the value of the process timer PT is read. The difference of the contents of RTO and PT is added to RUA. (Consecutively, the PT value is stored in RTO). Note that the time during which the process is suspended is not computed. The RTO and RUA words are updated even if the accounting mode bit is set to 0. However the CET, RTA, and WTA words (to be later described) are provided in the process control block only if the accounting mode bit in the process main word PMW 0 is set to 1. They are updated only in this case.
The waiting time accounting WTA word at bytes 17 through 23 is a real time counter which specifies the total amount of real time the process was in the waiting state. The WTA word is updated in the following way: each time the process exits the waiting state the time of day clock (not shown) value TOD is read and the value of TOD minus the value of CET word is added to the WTA word.
The ready time accounting RTA word located at bytes 24 through 31 is a double word which is a real time counter which specifies the total amount of real time the process was in the ready state. The RTA is updated in the following way: each time the process exits the ready state, the time of day clock value TOD is read, and the contents of TOD minus the contents of CET is added to RTA.
The current entry time CET double word at bytes 32 through 39 contains the time of day at which the process entered one of the following states: ready, waiting, running, and suspended.
SYSTEM BASE STRUCTURES:
Referring to FIG. 6 the format of the system base 600 is shown. The system base resides in absolute main memory and is developed by firmware and is accessible via the boundary address register (BAR) which can be read but not written. The boundary address register BAR is below an area in main memory reserved for hardware and separates this area in memory reserved for hardware and the system base 600. Referring now to FIG. 6 the system base 600 contains a number of system attributes which includes a job step number and a process group number (J, P) for the currently running process. From the logical name of the process J, P, the absolute address of the corresponding process control block PCB is obtained. The size and address of the J table are defined by the contents of the J table word (JTW). This word is located at the address defined by the BAR register. The format of the JTW is shown on FIG. 11a. The size (JTSZ) 1101 or the J table 1204 on FIG. 12 defines the number of entries in the J table 1204 which may be up to 255 entries. The JTSZ 1101 is an 8 bit positive integer; an out of J table exception occurs if J is greater than JTSZ. The absolute address of the J table 1204 is obtained by multiplying the J table pointer 1102 by 16. The J table 1204 contains J table entries whose format is shown in greater detail on FIG. 11b. Each J table entry defines the absolute address of a P table 1205 which is obtained by multiplying the P table pointer 1104 by 16. The size (PTSZ) 1103 of a P table defines the number of entries in the P table. The PTSZ is an 8 bit positive integer which may typically vary from 0 to 255 to indicate the number of entries in the P table. An out of P table exception occurs if P is greater than PTSZ. Each entry of the P table 1205 defines the absolute address of a process control block (PCB) 1206 by multiplying the process control block pointer 1107 by 16. A presence indicator P 1105 indicates the absence of a PCB 1206 when set to binary 0 and indicates the presence of a PCB when set to binary 1. (When the presence indicator P 1105 is found to be 0 a vacant P table entry exception occurs). Bits 1 through 7 of the P table indicator (FIG. 11c) must be 0 (MBZ) 1106, otherwise an illegal P table entry exception occurs.
At address BAR plus 4 of the system base 600 there is the format byte of a G table word (GTW) shown in greater detail on FIG. 11d. The size and the address of a G segment-table 1212 on FIG. 1200 are defined by the contents of the G table word (GTW). The size (GTSZ) 1108 of the G table 1212 defines the number of entries in the G table which may typically be up to 255 entries. GTSZ is an 8 bit positive integer; an out of G table exception occurs if the G number is greater than the GTSZ. The absolute address of the G table 1212 is obtained by multiplying the G table pointer 1109 by 16. The format of the G segment table entry has a two word size (8 bytes) and is called a G segment descriptor. The format of the G segment descriptor is shown in detail on FIGS. 11e and 11f. All G segment descriptors are direct and therefore the indirect bit I, 1111 must be 0 otherwise an illegal segment descriptor exception occurs. The presence indicator P 1110 is a one bit field which when set to binary 1 indicates that a segment is defined in main storage for the segment number to which that descriptor corresponds; whereas if it cleared to 0 no segment is defined and a reference to the segment descriptor causes a missing segment exception. The available bit A 1112 is a one bit field which indicates whether or not the segment is available; it is only checked if this segment is defined (i.e. P equals binary 1), otherwise it is ignored. The used flag field U 1113 indicates whether or not the segment has been accessed. If the U bit is set to binary 0 the segment has not been accessed; whereas if the U field is set to binary 1 the segment has been accessed. The written flag field W 1114 indicates whether the segment has been written. If W is set to binary 0 the segment has not been written; whereas if W is set to binary 1 the segment has been written. The gating indicator GS 1115 of a G segment descriptor must be set to binary 01, otherwise an illegal segment descriptor exception occurs. The reason for this is that a G segment always contains semaphores (although the reverse is not true i.e. all semaphores are not required to be in a G segment) and instructions on semaphores require the GS code to be binary 01. The absolute address of the base of a segment 1214 is defined in the G segment descriptor of FIG. 11e by the 24 bit base field 1116; the content of this field is multiplied by 16 to obtain the absolute address. The second word of the G segment descriptor of FIG. 11f occupies bit position 32 through 63 in the G table 1212. The RSU field 1117, bits 32 through 39 is reserved for software use and is generally ignored when used as a G segment descriptor as it is in this case. The MBZ field 1118 must be 0 otherwise an illegal segment exception occurs. Since the MBZ field 1118 occupies bits 40 through 51 it sets the SIZE field 1119 which is the field for a small segment SIZE; hence all G segments must be of the small segment type. The segment SIZE 1119 is a 12 bit positive integer defining the number of bytes in the segment and the segment size is interpreted as a multiple of 16. Therefore the segment size for a G segment 1214 cannot exceed 2.sup.16 bytes (small segments). If a displacement D within a G segment is referenced where D is greater than or equal to SIZE 1119, an out of segment exception occurs. The method of accessing main memory which uses a G segment and a displacement D within that segment is called G, D accessing. The various exceptions which may occur during G, D memory operations are referred to as G, D access exceptions.
Referring once again to the system base 600 of FIG. 6 there are 9 system exception cell words located between BAR plus 8 and BAR plus 44. The format of the system exception cell words EXC is shown on FIG. 11g. Since semaphores are utilized for transmitting messages to dedicated processes when a system exception occurs the pointers to these semaphores are found in 9 locations of memory each location called a system exception cell --one per class of system exception. The MBZ field 1120 must be set to binary 0 otherwise a system check occurs. Each exception cell (EXC) contains the system name G, D 1121 and 1122 respectively.
The channel exception cell located in BAR plus 44 of the system base 600 has a format which is similar to the system exception cell previously discussed and contains the system name GD of a semaphore which is used for transmitting messages to dedicated processes when a channel exception occurs.
An internal processor queue word IPQW is located beginning at BAR plus 48 and details of its format are shown on FIG. 11h. The IPQW word points to the head of a queue of processes ready (Q/PR/RDY) as shown on FIG. 9 by reference numerals 905 and 805. The queue of processes ready (Q/PR/RDY) links all processes which are in the ready state. It is referenced by the HEAD of Q/PR/RDY-field 1124 (FIG. 11h) of the IPQW word by pointing to the top of the ready process queue. The HEAD of Q/PR/RDY-field 1124 contains a 16 bit positive integer which is the displacement from the base of the G segment number 0, referred to as the GO segment, to the first byte of Q/PR/RDY. If this Q/PR/RDY bit field is 0, the ready queue is considered to be empty. The MBZ field 1123 must be 0 otherwise a system check occurs.
At BAR plus 52 of the system base 600 there is shown the storage for the initial and current retry counts whose format is shown in detail on FIG. 11i. The NFS field 1125 is a nonfunctional storage field and is not utilized by the system base. The initial retry count field 1126 and the current retry count field 1127 are used to control the number of times automatic instruction retry is executed before a machine error is made to produce a machine failure exception condition. They are loaded with the same number by a Reset Retry Count (not shown herein).
The running process word (RPW), shown in FIG. 11j, is stored in BAR plus 56 of the system base 600 and is used to store the name of the running process with its priority in case of a monoprocessor architecture. The NFS fields 1128 and 1131 respectively are nonfunctional storage fields and may be utilized for any purpose by any facility but is generally not utilized by the system base. The priority level of a running process is stored in the PRI field 1129. An asynchronous trap bit is stored in AB field 1130; whereas an asynchronous trap ring is stored in ARN field 1132. The logical name J, P of the running process in case of a monoprocessor architecture is stored in the J, P field 1133.
An Absolutization Table Pointer word shown on FIG. 11k is located at BAR plus 60 in the system base 600 and is utilized in initial system load to initialize the absolute addresses in the initial system load (ISL) program by adding the contents of BAR to all absolute addresses in the ISL program. The Absolutization Table Pointer 1135 defines the location of an Absolutization Table (not shown). The Absolutization Table Size is shown by the ATSZ field 1134.
The CPU serial number word shown on FIG. 11l is a 4 byte word located at BAR plus 64 and contains the serial number of the CPU in the CPU serial number field 1136.
A main storage upper limit word shown on FIG. 11m is located at BAR plus 68 and indicates the main storage upper limit 1139 by providing the absolute address of the last available word in main storage.
At BAR plus 72 there is located a word shown on FIG. 11n for providing the initial system load ISL device channel number (CN) 1140 and the hardware device channel number (CN) 1141.
The type and subtype of a device used in the computer system is shown by a hardware device type word (FIG. 11o) in fields 1143 and 1144 respectively; where the RSU field 1142 is reserved for software. This word is found in the system base at BAR plus 76. A similar word having a similar type format shown on FIG. 11p contains the type and subtype of the device used in the initial system load. This word is located at BAR plus 80.
when the restart button of a computer is pressed, a simulated V-operation is preformed on a semaphore and the Ready state is entered. A pointer to this semaphore is found at BAR plus 84 of the system base 600 and is called a restart cell word, and has a format shown on FIG. 11q. The format is similar to the system exception cell described supra and contains the system name G, D of a semaphore in the G field 1149 and D field 1150 respectively. The MBZ field 1148 must be 0.
Where there is more than one processor to the computer system, a word is provided in the system base 600 at BAR plus 88 for multiprocess extension. Details of this word are shown on FIG. 11r.
EXAMPLES OF SYSTEM BASE AND PROCESS CONTROL BLOCK USE
Referring to FIG. 12 there is shown one example, how the system base may be utilized in combination with the process control block in order to address and access a user segment, a system segment, or a queue of processes ready (Q/PR/RDY) segment. Main memory 1200 has a portion 1203 reserved for hardware use. A boundary address register BAR 1202 separates the system base 1215 from the portion of memory 1203 reserved for hardware. The boundary address register BAR 1202 is utilized to address items in the system base 1215 by adding the contents of the boundary address register to the displacement in 4 byte units of the item desired in the system base. This address then points to the first byte of the item in the system base desired. In FIG. 12 the BAR 1202 is pointing at the J table word (JTW). The J table word, as previously discussed, has a pointer which points to a J table 1204. By indexing to the J number shown on FIG. 5, a J table entry 1216 is obtained. At the J table entry there is a P table pointer which points to the absolute address of the P table 1205. By indexing to the P number (see FIG. 5) within P table 1205 the absolute address of the process control block 1206 is obtained. As previously shown in process control block PCB 1206 there are two address space words ASW 0 and ASW 1. The high order bits of the segment table number field STN in the base register 1201 is used to access one of these two address space words, in this instance ASW 1 which has a segment table word array STWA pointer that points to segment table word array STWA 1208. Together with the segment table number STN of the base register 1201 one of 8 segment table words is accessed in STWA 1208, which points to one of 8 segment tables 1210. The segment table entry STE from base register 1201 is then utilized to make one of 256 entries in segment table 1210 where a segment descriptor is located. The segment descriptor is then utilized to access a user segment 1211. (For greater detail see U.S. Pat. Application No. 425,356, filed on Dec. 17, 1973, entitled "Apparatus for Developing an Address of a Segment within Main Memory and an Absolute Address of an Operand within the Segment," and issued into U.S. Pat. No. 3,938,096 on Feb. 10, 1976.
In order to access a system segment 1214 which is utilized to store semaphores a G table word CTW is utilized in the system base 1215. The address of the G table word is obtained by adding the displacement of the G table word in the system base to the boundary address register BAR 1202. (See FIG. 6). The G table word GTW includes a G table pointer which points to a G table 1212. By utilizing a G number available to the system and indexing in the G table a G segment descriptor is accessed which is utilized to address a system segment 1214.
Similarly the system base 1215 is utilized to access the queue of process ready (Q/PR/RDY) 1213 by locating an internal processor queue word IPQW which points to the Q/PR/RDY segment 1213.
G. CONTROL UNIT
Referring to FIGS. 13a-13c details of the control unit are shown. The control unit, although shown separate from the central processing unit (CPU), is in actuality a part of the CPU and is comprised of a control store unit CSU 1301, a control store interface adapter CIA 1302 and appurtenant subunits, control store loader CSL 1303 and control and load unit CLU 1304.
The control store unit CSU 1301 receives micro-instructions from the control store loader CSL 1303 via the control and load unit CLU 1304 and the control store interface adapter CIA 1302. Under normal operating conditions, microprograms are loaded from an external source during system initialization and become a permanent control function of the machine. However the control store unit CSU 1301 has the ability to be reloaded and initialized in a manner that provides for a variety of central processing units CPU 1306 operational modes. The following modes of operation of the CPU are available under control of the CSU 1301; (a) native mode; (b) emulation mode; (c) concurrent native and emulation modes; (d) diagnostic mode. This capability is possible because the micro-instructions resident in the CSU are the source of micro-operations used to control the operation of all other CPU functional units such as the emulation unit 1316, the arithmetic logic unit ALU 1317, the instruction fetch unit IFU 1318, the address control unit ACU 1319 and the data management unit DMU 1321. Also shown within the central processing unit CPU 1306 are previously described general registers 1307, base registers 1308, scientific registers 1309, T-registers 1310, status registers 1311, instruction counter IC 1312, and hardware control mask register 1313.
Typically the control store unit CSU 1301 is a 9K bipolar integrated circuit programmable read-only memory (PROM) mixed with read/write random access store (RAM). It has a typical 150 nanosecond read cycle and a 450 nanosecond write cycle. Each location of control store stores one 84-bit micro-instruction word (to be later more fully described), and each micro-instruction word controls one CPU cycle. As each location of the control store of the control store unit CSU 1301 is read, its contents are decoded by micro-operation decoders which provide micro-operation control signals each of which causes a specific operation within the CPU to take place (to be later described in detail).
By grouping locations within each micro-instruction word (to be later described in detail) control store sequences are obtained that can perform a specific CPU operation or instruction. As each instruction is initiated by the CPU, certain bits within the op-code are used to determine the control store starting sequence. Testing of certain flops (not shown) which are set or reset by instruction decode functions allows the control store memory to branch to a more specific sequence when necessary.
The control store interface adapter CIA 1302 communicates with the control store unit 1301, the data management unit DMU 1321, the address control unit ACU 1319, and the arithmetic logic unit ALU 1317 for directing the operation of the control store memory 1333 of FIG. 13b. The CIA 1302 includes logic for control store address modification, testing, error checking, and hardware address generation. Hardware address generation is utilized generally for developing the starting address of error sequences or for the initialization sequence.
The data management unit DMU 1321 provides the interface between the CPU 1306 and the main memory and/or buffer store memory shown on FIG. 1. It is the responsibility of the data management unit to recognize which unit contains the information required by other units and strobe in information into the CPU registers at the proper time. The data management unit DMU also performs the masking during partial write operations.
The instruction fetch unit IFU 1318 interfaces with the DMU 1321, the ACU 1319, the ALU 1317, and the CSU 1301, and is responsible for keeping the CPU supplied with instructions. The instruction fetch unit has the next instruction available in its registers before the completion of the present instruction. To provide this capability, the instruction fetch unit IFU 1318 contains a 12-byte instruction register (not shown) that normally contains more than one instruction. In addition, the IFU, under control of the CSU, requests information (instructions) from main memory before the instruction is actually needed, thus keeping its 12-byte instruction register constantly updated. Instructions are thus prefetched by means of normally unused memory cycles. The instruction fetch unit also decodes each instruction and informs the other units of the instruction's length and format.
The address control unit ACU 1319 communicates with the IFU, ALU, DMU, and the CSU via the CIA. The ACU 1319 is responsible for all address development in the CPU. All operations of the ACU, including transfers to, from, and within the unit, are directed by CSU micro-operation and logic in the unit. The normal cycling of the ACU depends on the types of addresses in the instruction rather than on the type of the instruction. Depending on the address types the ACU may perform different operations for each address in an instruction. The ACU also contains an associative memory 1319a that typically stores the base address of the 8 most recently used memory segments, along with their segment numbers. Each time a memory request is made, the segment number is checked against the associative memory contents to determine if the base address of the segment has already been developed and stored. If the base address is contained in the associative memory 1319a, this address is used in the absolute address development, and a considerable amount of time is saved. If the base address is not contained in the associative memory 1319a it is developed by accessing the main memory tables. However, after the base address of the segment is developed, it is stored in the associative memory, along with the segment number, for future reference.
Interfacing with the ACU, IFU, DMU, and the CSU is the arithmetic and logic unit ALU 1317. Its primary function is to perform the arithmetic operations and data manipulations required of the CPU. The operations of the arithmetic logic unit are completely dependent on micro-operation control signals from the control store unit CSU 1301.
Associated with the ALU 1317 and the CSU 1301 is the scratch pad memory unit LSU 1315, (sometimes referred to also as the local store unit). It is typically comprised of 256-location (32 bits per location) solid state memory and selection and read/write logic for that memory. The scratch pad memory 1315 is used to store CPU control information and maintainability information. In addition, the scratch pad memory 1315 contains working locations which are primarily used for temporary storage of operands and partial results during data manipulation. Also associated with the ALU 1317 is an auxiliary memory 1317a comprised typically of 64 flip-flops for storing miscellaneous states of the computer system.
The CPU also has a clocking unit 1320 and is essentially 2 clocking systems in 1: the first clocking system generates the timing for the control interface adapter CIA 1302 and the second clocking system generates the timing pulses for the operations of the functional unit within the central processing unit.
Referring now to FIG. 13c there is shown the format of the control store word 1325. The control store word is typically 84 bits wide and is divided into 6 main fields:
a. sequence type field 1326 (3 bits);
b. branching and/or micro-operations 1327 (23 bits);
c. constant generation and designation 1328 (14 bits);
d. data to bus 1329 (8 bits);
e. micro-operations 1330 (32 bits); and
f. checking 1331 (4 bits).
The 3-bit E field of the control store word 1325 is used as a sequence control field. There are typically 7 different sequence types and 1 reserved type for the instant computer system. Referring to block 1335 of FIG. 13b, when E field equals binary 0, 1, or 2, the branching field A, B, C, D and L of micro-instruction 1325 is utilized to generate the next address. The first 6 bits of KS register 1337 is utilized together with the B field, a C test results, the D test results and the L field to provide the next address of the next micro-instruction which is then placed in address register KS 1337. When the E field is set to binary 4 (see block 1335) the next address selected is taken from interrupt return register KA 1339. The address stored in the KA register is the one generated by the next address generation logic when the hardware interrupt occurs. When the E field is set to binary 5 a branch is used to initiate a subreturn from a micro-program subroutine. When used, the contents of the return register KR 1346 are used as the next control store address. The return register 1346 is loaded by issuing a control store command which will load present control store address in KS register 1337 plus 1, from incrementor 1338, into the KR register 1346. A one-level-nesting subroutine ability is provided via the KT return branch register 1347. Every time the KR register 1346 is loaded the old contents of the KR register is transferred to the KT register 1347 every time the micro-program return is called; the contents of the KT register will transfer to the KR register. Third level nesting subroutine ability is provided by the KU register 1340; and fourth level nesting subroutine ability is provided by the KV return branch register 1349. When the E field of the control store word is set to binary 6 the next control store word addressed is equal to the present address in KS register 1337 plus 1 in incrementor 1338. When the E field is set to binary 7 the CSU 1301 enters the diagnostic mode and the next address will be the present address plus 1.
In addition to the sequencing control of branching to the next control store address described above and shown in block 1335, there is hardware generated sequence control shown in block 1336 of FIG. 13b. (Note: Blocks 1335 and 1336 are in actuality hardware registers drawn so as to depict the different forms that the microinstruction words may take.) The hardware generated branches are overriding conditions (such as errors, initialize, control store scan, etc.) which suppress the E field and force a fixed address into the control store address register KS 1337. The branch is made by forcing an interrupt line high (not shown) for one clock period and storing the address which would have been generated under the control of the E field into the KA interrupt return register 1339. A hardware generated address will be placed into the control store address register. Certain hardware/firmware generated interrupts take priority when the interrupt-block flip-flop (not shown) which prevents additional interrupts in their class from being executed until the interrupting condition has been satisfied. A firmware micro-operation exists for controlling the resetting of the interrupt-block flip-flop for those sequences which are under firmware control. Those sequences under hardware control automatically generate a reset of the block-flop at the end of the sequence. The following conditions, listed by priority, exists in this category; (a) control store load; (b) control store scan; (c) hardware error; (d) software error. The remaining hardware conditions do not set the interrupt block-flop but do cause an immediate action to occur when generated. The following conditions listed by priority, exist in this category;
(a) initialize;
(b) soft-clear;
(c) enter maintenance panel;
(d) enter maintenance panel;
(e) hardware exit.
An initialize signal causes the CSU 1301 to branch to address binary 0, clear hardware resettable errors and execute a control store load operation followed by a control store scan sequence under hardware control. It will also perform system initialize. A soft-clear signal causes the CSU 1301 to branch to address binary 0, clear hardware resettable errors and reset the interrupt block-flop. An enter maintenance panel signal causes the CSU to branch to the address preset in the CSU address switches on the maintenance panel (not shown).
An enter maintenance channel signal causes the CSU to branch to an address generated via the maintenance channel (not shown). The address loaded is from maintenance bus QMB 1344, which is part of the maintenance channel, and is right-justified. A hardware exit signal causes the CSU to branch to binary address 2. This sequence is used as a maintenance facility. At the end of the sequence a return is initiated by issuing an E field branch with the E field set to binary 4.
A control store load signal causes the CSU to branch to address binary 0. It also turns off the CSU read-cycle flop (not shown), the system clock 1320, and places the CSU in the load state. In the load state the CSU can be loaded from the control store loader CSL 1303, the IOC 1305, the main memory 102, or the maintenance panel 1355. When loaded from the CSL an automatic scan is generated at the end of the load. When loaded from any other media a scan may be issued by either generating a micro-operation signal or setting the scan switch on the maintenance panel. A control store scan signal causes the CSU to branch to an address binary 0. A control store scan is under hardware control for the duration of the sequence. During the scan the system clock 1320 is off and therefore no commands or tests are executed. At the end of the scan sequence the hardware transfers the contents of the interrupt return register KA to the address register KS, the system clock is turned on and control is returned to the firmware.
A hardware error signal causes the CSU to branch to address binary 4. In the normal processing mode a hardware error detected in any CPU functional unit will activate a hardware error line (not shown). The control store sequence generated will test the system conditions to determine the action to be taken. In the diagnostic mode, error conditions which are hardware detectable are visible to microdiagnostics. The microdiagnostics control the action to be taken. A software error signal on the other hand causes the control store to branch to address binary 1. This address is the start of the software error reporting sequence which is under micro-program control.
Referring once again to FIG. 13c the E field 1326 is a 3 bit field for the branch code as previously described. The branching and/or micro-operation field 1327 is comprised of the A, B, C, D, and L fields (also shown on block 1335 of FIG. 13b) wherein the A field is the upper 6 bits of the next address, the B field is the middle 4 bits of next address of the mask field on 64-way branch, the C field is a 6 bit test field for 1 of 64 tests, the D field is another 6 bit test field for 1 of 64 tests, and the L field is the least significant bit. The K field 1328 is a 14 bit field of which 6 bits are for the constant field, 4 bits are for a constant or steering field, and 4 bits are a steering field for a constant. The data to bus field 1329 is comprised of the QA field having 4 bits for controlling information to the QA portion of the QMB bus 1344 and the QB field has 4 bits for controlling information to the QB portion of the QMB bus 1344. The F field 1330 is a 32 bit field which is coded to generate micro-operation subcommands. The P field 1331 is comprised of 4 bits reserved for checking.
In operation the micro-instruction words are stored in the control store array 1333. During a cycle of operation, the control store array is addressed by the contents of the KS address register 1337. This causes the contents of the location specified by the address to be read into the group of read latches 1357. Portions of the word contents of the read latches are distributed or transferred to storage registers within each of the functional units in the CPU. Each functional unit includes decoding logic circuits for generating the requisite subcommands specified by the control store word under control of the system clock source. In general decoding is performed within each functional unit in the CPU rather than being performed centrally in order to minimize the decoding time and to reduce the number of cables which would be normally required for transmitting command signals if decoding were performed centrally. Additionally, the decoding is done within each unit to avoid timing problems arising from differences in cable delays. Further, by decoding subcommands with each unit, those signals which are representative of certain conditions existing within the functional unit are required for the generation of certain subcommand signals do not have to be returned to the CIA unit 1302. A typical decoder unit 1359 is shown in FIG. 13b as receiving various fields from micro-instruction words and generating micro-operation signals a, b, c, d, . . . q, r. A typical micro-operation decoder 1359 receives commands from a micro-instruction word. The field from the micro-instruction word is decoded and sets one of a plurality of lines s, t, u, . . . y, z high. A matrix is formed by having predetermined control line impedance coupled to the s-z lines at points .alpha., .beta., .gamma. . . . .gamma., .omega.. Typically then when the field from a micro-instruction is decoded one of the lines s-z goes high. Since the black dots shown in the matrix by Greek letters .alpha. through .omega. represent impedance coupling between the two sets of lines, any electrical signal propagating along any horizontal wire will be coupled through to propagate along the vertical wire a-r where an impedance coupling (black dot) is indicated. Each vertical line a-r then may be coupled as one input to one each of AND gates 1360-1365. Other input signals may also be coupled to AND gates 1360-1365 including a timing signal t.sub.s from the central timing unit. Accordingly as each timing signal t.sub.s goes high those gates which have all the other input signals high will be enabled and will provide micro-instruction signals to predetermined functional units in the CPU. For example, if a command 1341 from read latch 1357 is decoded and a horizontal line is high the a, b, c, and q vertical control lines will be high and AND gates 1360, 1361, 1362, and 1364, will be enabled as the t.sub.s timing signal is applied to these gates sequentially. Hence the combination in which the vertical control lines are coupled to the horizontal control line at different points represented by the Greek letters .alpha. through .omega. represent a permanent switching matrix for supplying micro-operation signals to the central processing unit CPU for controlling the functional units within the central processing unit by micro-instructions furnished from the control store array 1333. Thus permanent firmware having an alterability feature can be built into the machine of this invention by merely specifying the sequence of micro-operations that is required as a capability of the computer system.
Under normal conditions data is written into the control store array 1333 via the CPU write-data register also known as the local register YO 1343. A control flop (not shown) defines whether the upper half or lower half of the storage array is to be written. Data from the control and load unit CLU 1304 arrives at the CIA/CSU via the maintenance bus QMB 1344 and is buffered by the storage local register Y0 1343 before being written into the control store array 1333. The storage local register 1343 is time shared as both a read and a write local register. The multiplexor KQM 1345 may be controlled by either the maintenance panel 1355 or by microdiagnostics and provides a read out path from the registers connected to it. A compare register KP 1350 is provided for non-functional use and is usually mainly for maintenance purposes and is utilized along with compare logic 1352 and decode logic 1351.
H. DISPATCHER FIRMWARE FOR CONTROL OF PROCESSES
The dispatcher is a firmware/hardware unit whose main purpose is to manage the various queues of processes, and to switch between processes and includes the updating of the queues of processes, the process control blocks PCB's, the running process word in the system base and the register of a new process. It also delivers messages to a process which is actually waiting for it on a semaphore (after a V-operation, a simulated V-operation for the IOC or for the exception handler). It also enqueues a message on a semaphore after a P-operation which freed a message link when a process is waiting on the freelink semaphore to deliver its message.
The dispatcher unit further calls on the native mode instructions firmware after the "rolling-in" of a process executing in native mode, or after a "contest" if the current process remains running and is executing in native mode. It also calls on decor extension firmware for:
(a) a temporary call during the rolling-out of a process executing in that decor extension;
(b) a temporary call during the rolling-in of a process executing in that decor extension;
(c) a definitive call at the end of the rolling-in of a process executing in that decor extension; and,
(d) a definitive call after a contest if the current process remains running and is executing in that decor extension.
Moreover the dispatcher places the system in the idle loop when there is no running process.
There are several ways of entering or leaving the dispatcher as follows:
(1) The initialization procedure (SIP) provides entry as the last step, (See U.S. Pat. application No. 528,814, filed Dec. 2, 1974, entitled "Arrangement for Initializing a Data Processing System".)
(2) The Start and Suspend Instruction provides for the entry into the dispatcher. The Start instruction starts a process and the Suspend instruction terminates a process. (See U.S. Pat. application No. 529,253, filed Dec. 2, 1974, entitled "Process Management Instructions for a Control Processor".)
(3) The P and V operations provide for entry into the dispatcher. The P op picks up a message from a semaphore and if no message then the process goes into wait state. (See U.S. Pat. application No. 529,017, filed Dec. 2, 1974, entitled "P and V Instructions on Semaphores for Process Synchronization".)
Briefly then, the dispatcher is the main mechanism which manages the processes and accordingly the process control blocks PCB's by deciding which process is to be run and then taking the appropriate action, such as rolling-out the currently running process (i.e. write into the PCB all information relative to the currently running process contained in hardware registers, scratch pad memory, etc.), and rolling-in the new process (i.e. write from the PCB to various hardware registers, scratch pad memory, etc., all information necessary to run the new process.)
The representation of the operations in firmware (i.e. in control unit) performed by the dispatcher are shown in flow-charts FIGS. 14a-14i. For example, block 1402 of FIG. 14a is a representation of the operation performed by the dispatcher wherein a microprogram word is delivered by the control store unit, and upon decoding by decoder 1359 controls the applicable portions of the CPU via an appropriate series of micro-operation signals 1360, 1361, etc. to retrieve the IPQW from the system base in storage subsystem 102, and transfer it to scratch pad memory 1315. Simultaneously the dispatcher fetches 1404 the GO segment descriptor (see FIG. 12) from the G table of segment descriptors pointed to by the G table word GTW in the system base. Bits 16-31 of the IPQW word contain a 16-bit positive integer which is the displacement from the base of the G segment number 0, referred to as the GO segment, to the head (first byte) of the Q/PR/RDY, queue of processes ready. If bits 16-31 of the IPQW word is 0, 1403 the ready queue is considered to be empty. If the ready queue is empty it indicates that there is no process currently waiting in the Q/PR/RDY and the ready queue is empty. The next question to be decided in decision block 1405 is whether or not a process is currently running in the machine by determining whether or not the Vacant Indicator is set. If the Vacant Indicator is set (i.e. there is no process currently running) and since it was previously determined that there is no process in the ready-queue waiting to use the processor then the machine goes in the idle state 1406. However if there is a process currently running in the machine, but there is no waiting to use the machine, the current process accesses its next instruction 1407.
Returning now to decision block 1403, of the flow chart of FIG. 14a if there is a positive integer in the pointer area of the IPQW (i.e. bits 16-31) the head of the ready queue pointed to by the IPQW word in the GO segment is fetched to the scratch pad memory. (Note: To avoid repetition and in the interest of clarity the intermediate functions of the dispatcher in conjunction with the control unit and CPU will be omitted; however it is to be understood that such intermediate functions as previously described by example are present typically.) Up to this point it has been determined that there is some process waiting in the ready-queue. Before further action can be taken it is necessary to determine if there is a process currently running in the central processor. This is determined at decision block 1410 of the flow chart representation and if there is no process running in the central processor (i.e. no CJP) the head of the ready queue is run 1412. However if there is a process running in the central processor the dispatcher must determine who has priority - the currently running process or the head of the ready queue? Accordingly therefore the priority byte of the current process (CJP) which is located in the running process word of the system base PCB 400, is fetched 1413. A decision is then made 1414 as to whether or not the current running process CJP is of lower priority than the new process NJP waiting at the end of the ready queue? (See decision block 1414.) If CJP is not of lower priority than NJP, CJP remains in control of the central processor and the contest indicator is reset 1415. (The contest indicator is always set to 0 except when one or more new processes have been placed on the ready-queue since the beginning of the last instruction executed on behalf of CJP thereby creating the possibility of a conflict; under these conditions the contest indicator is set to binary 1). Before the current process CJP is permitted to continue however, and execute further instructions a determination is made whether or not the CJP is running in decor extension mode 1415. If CJP is running in decor extension mode then the next instruction is executed in emulation mode (i.e. decor extension) and if it is not running in decor extension mode then the next instruction is executed in native mode. Returning once again to decision block 1414, if the NJP at the head of the ready queue has a higher priority than the CJP (i.e its priority number is lower than CJP's priority number, the current running process CJP is "rolled-out" of the machine and the new process NJP is "rolled-in" of the machine and the new process NJP is "rolled-in" to the machine. Accordingly a firmware priority subroutine PRIQ 1418 directs the enqueueing of the current process CJP into the ready-queue by LIFO priority and by priority number by first "rolling-out" the CJP under the direction of the firmware subroutine RLLO 1419. The RLLO subroutine directs the writing of the information of the CJP that is stored in the general registers, base registers, scientific registers, T-register, status registers, and instruction counter, back into the appropriate storage areas of the process control block PCB in main memory, and it directs the updating of the RUA. Moreover the DEXT number of process main word 0 (PMWO) in PCB 400 is updated 1420.
The new process NJP is now ready to be "rolled-in." The boundary address register BAR is fetched 1422 and the running process word RPW is fetched from address BAR plus 56 of the system base. See block 1423. The name of the new process NJP is next written into the running process word RPW and since the name of the new process NJP was written in the process link PL of the Q/PR/RDY, the name in the process link PL is therefore now placed in the RPW, block 1424. Therefore NJP from the ready-queue now becomes CJP and is entitled to control the central processor and accordingly is no longer waiting in the Q/PR/RDY and must be dequeued by taking its name out of the process link PL of the Q/PR/RDY, block 1425. When this is done the queue of processes ready Q/PR/RDY is updated by the firmware subroutine UQLK, 1425a. Accordingly the JP number of the process which was just taken out of the machine is placed in a process link in the Q/PR/RDY, since it now no longer has control of the machine and must wait for it, 1426. At this point the transformation of giving this control of the central processor to the new process and placing the old process in a ready queue is accomplished and because there is a process (the new CJP) in control of the central processor, the Vacant Indicator is set to 0, 1427; if on the other hand there were no CJP in control of the central processor the Vacant Indicator would be set to 1. At this point the assignment of the processor is complete and a new process has acquired the central processor whereas the old process was placed in a ready queue; however, the new process is not ready to run yet for the hardware of the central processing unit, 1306 of FIG. 13a, such as the general registers 1307, the base registers 1308, scientific registers 1309, the T-register 1310, the status registers 1311, and the instruction counter 1312, must be supplied with control information from the process control block of the new process.
Accordingly the firmware subroutine 1430 controls the CPU and first fetches PMW 3 from the PCB (FIG. 4) to scratch pad memory 1315, and then fetches PMW 0. The MBZ field of PMW 0 is checked 1433 and if it is not binary 0 an illegal PCB exception results. However, if the MBZ field of PMW 0 is zero then PMW 1 is fetched 1434. Again the MBZ field of PMW 1 is tested to determine whether or not it is a binary 0. If it is not binary 0 there is an illegal PCB exception; whereas if it is equal to 0 the dispatcher proceeds to C.
Accordingly address space word 0 ASW 0 is fetched from the appropriate space in the PCB and the segment table word size STWSZ is tested 1437 to determine whether or not it is less than 7. If it is greater than 7 an illegal PCB results if it is less than or equal to 7, then ASW 1 is fetched from the PCB, block 1438, and its STWSZ field is tested 1439 to determine whether or not it is less than or equal to 8. If its field is greater than 8 then an illegal PCB results; however, if its STWSZ field is equal or less than 8 the exception word PCB is fetched 1440, and its MBZ field is tested to determine whether or not it is equal to 0. If its MBZ field is not equal to 0 an illegal OCB results whereas if it is equal to 0 the stack word SKW is fetched 1442, and its MBZ field is tested 1443 to determine whether or not it is equal to 0. If the MBZ field is not equal to 0 then an illegal PCB results; whereas if it is equal to 0 to the instruction counter word ICW is fetched from the PCB and placed in the instruction counter IC and its TAG field is tested to determine whether or not it is equal to 0, 1445. If the TAG field is not equal to 0 then an illegal PCB results. However if the TAG field is equal to 0 the MBZ word is fetched 1446 and its MBZ field (bits 0-31) is tested to determine whether or not it is equal to 0, 1447. If it is not equal to 0 then an illegal PCB results; whereas if it is equal to 0 stack base words 0, 1 and 2 SBW 0, 1 and 2 are fetched 1448. The contents of the 8 base registers in the base register saving area of the PCB is then fetched 1449 and stored in the machine's base registers 1308. Then the contents of the 16 general registers from the general register saving area of the PCB are fetched 1450 and stored in the machine's general registers 1307. Before fetching the contents of the scientific registers however a check is made of the capability byte of process main word 0 (PMW 0) to determine whether or not scientific mode is being utilized 1451. If scientific mode is being utilized then the contents of the scientific registers from the scientific register saving area of the PCB are fetched and stored 1452. The firmware then proceeds to make a check of the capability byte of PMW 0 to determine whether or not the accounting mode is being utilized 1453. If the accounting mode is being utilized (i.e. accounting bit of capability byte set to binary 1) the accounting words exists in the PCB and the ready time account word RTA is updated. Then the firmware proceeds to determine whether or not the DEXT number is set to 0, 1454. If it is not set to 0 it indicates that the machine may be in emulation mode (i.e. the decor extension capability is being utilized) and accordingly the DEXT number of PMW 0 is checked 1455 to determine whether or not it is greater or less than the DETSZ field of process main word 3 and if it is greater than the DETSZ field an illegal PCB exception 1456 results since the DEXT number is less than the DETSZ field but not equal to zero the machine is performing in legal emulation mode and proceeds to F. Returning to decision block 1454 if the DEXT field is binary 0 then native mode is being performed and the machine fetches STW's, 1457. The residual time out word RTO word of the PCB is fetched 1458 and the process timer is loaded, with the time limit that the CJP may spend in the running state.
Up to this point either (a) a new process NJP has been "rolled-in" to take control of the CPU when there was an old process CJP in the machine and the new process NJP was at a higher priority than the old process CJP of (b) there was no CJP in control of the CPU and the head of the ready queue was run. Briefly under condition (a) the CJP was taken out of the RPW and placed in a process link PL in the Q/PR/RDY, and the NJP in a process link PL in Q/PR/RDY was placed in the RPW thus effectively switching the positions of the 2 processes giving control to the NJP which now becomes the CJP and taking control away from the old CJP. Then the PCB of the NJP was accessed and the information required to run NJP (now the CJP) was placed in scratch pad memory or the array of registers in the ACU.
If there was no CJP in control of the CPU (condition b), then the head of the ready queue was run--i.e. the NJP became the CJP because of the dispatcher taking the NJP from the process link PL from the head of the ready queue and placing it in the RPW word. By doing this a process link PL was left empty in the Q/PR/RDY and it is required to take it out.
Accordingly beginning now at decision block 1461 the firmware determines whether or not there was a CJP in control of the CPU and if there was a free process link (FPLS) it was accessed and enqueued and the CJP was written therein. However if there was no CJP in control of the CPU state byte of PMW O of the NJP is updated 1460 and again there is a determination whether or not there was a CJP in the machine 1463. If there was no CJP in control of the processor the process link of the NJP (which was in the Q/PR/RDY and is now in control of the machine) is taken out of the Q/PR/RDY 1466 (i.e. dequeued from the Q/PR/RDY) and becomes a free link semaphore FLSP and is now enqueued in the free process link queue (805 on FIG. 9) and becomes a part of the free process link queue 1466a. The contents of the boundary address register BAR are fetched 1464 and the running process word RPW of the NJP (now the CJP) located at BAR plus 56 of the system base is updated by placing the NJP identification in the RPW, block 1465. The Vacant Indicator is set to 0 in the case where there had been no CJP. Next the Contest Indicator is set to 0, 1467 and the Segment Associator (AS 132 on FIG. 1) which is a typical content addressable memory is cleared, 1471; then the process mode is entered 1470. (A process mode indicates that exceptions are handled by the process which is operating in the processor rather than by the operating system). The firmware then continues to CAB 1480 and the asynchronous trap bit AB is checked to determine whether or not it is set to binary 1, 1481. If the AB bit is set to binary 1 then a check is made 1482 to determine whether or not the process ring number PRN is greater than or equal to the asynchronous trap bit ARN. (The AB and the ARN are located in the priority byte of the PCB of each process and is meaningful when the process is in the running state; the AB and ARN are obtained from the RPW located at BAR plus 56 of the system base). The AB and ARN in BAR plus 56 of the RPW are reset since the next step 1484 is to proceed to an asynchronous trap routine which would take care of the conditions that cause the asynchronous trap bit or the asynchronous ring number to be set in the first place, and if these were not reset than at the next pass by the firmware it would give an indication that something was wrong where actually there was nothing wrong, and hence would always proceed to the asynchronous trap routine 1484 and would never execute. Going back now to decision blocks 1481 and 1482 if the AB bit is not set or AB bit is set and PRN is not greater than ARN, then the firmware would proceed to determine in what mode the processor would run -- in the normal mode or in the emulation mode. Accodingly the DEXT number is checked to determine whether or not it is set to 0 and if it is set to 0 the normal mode of the machine is run 1487. However if the DEXT number is not set to 0 the emulation mode is run 1486.
DETAILED DESCRIPTION OF THE INVENTION
The hardware/firmware system recognizes two basic types of records which are manipulated in set operations. These two types of records are the virtual memory records illustrated in FIG. 15A and the database records illustrated in FIG. 15B. Virtual memory records are generally used internal to operating system procedures where records can be addressed by segmented addresses. Database records are more generally used by user programs which address their data records with Area-Page-Line numbers. The Area refers to the user file, the Page to a division within his data file, and the Line number to a particular record within that page of that file.
As shown in FIG. 15A the virtual memory record is composed of the following fields: the Type field 1501 is a description of the record type and is derived from this record's record descriptor (which will be described below). The D switch field 1502 of the virtual memory record describes the state of the record. The record can be in the following states: active, which means the record currently contains valid data; and logically deleted, which means the record no longer contains valid data but still occupies memory space. The Length field 1503 describes the actual number of bytes in the record. The record body 1504 contains the actual data of the record. The pointer sequence field 1505 is a portion of the record body which may contain the pointers to the next, prior, first, last and owner record, of the set in which the record is either an owner or a member.
The second major type of record recognized by the hardware/firmware system are database records as described in FIG. 15B. The Type field 1510 again describes the type of record and is derived from the record's record descriptor which will be described below. The Length field 1511 describes the length of the record in bytes. The record body 1512 contains the actual data of the record. The pointer sequence 1513 contains the pointers to the next, prior, etc., records of the set. There is also a D switch field 1604 for each record which is recorded separately and which will be described below.
FIGS. 15C and 15D further describe the format of the pointer sequence of a record (field 1505 of FIG. 15A and field 1513 of FIG. 15B). The hardware/firmware system recognizes two different pointer sequence formats, one FIG. 15C which is the sequence recognized for member records and the second FIG. 15D for when the record is an owner record. For member records (FIG. 15C), the Next Pointer field 1520 contains the address of the next member in the set. The Prior Pointer 1521 contains the address of the previous member of the present set. The Owner Pointer field 1524 contains the address of the owner of the set. For owner records the pointer sequence format recognized by the hardware/firmware is shown in FIG. 15D. The First Pointer field 1532 contains the address of the first member record of the set. The Last Pointer field 1533 contains the address of the last member of the set.
Each of the pointers described (next, prior, owner, first and last) are optional. However, for a given set only the following combinations are legal:
Case 1. No first, last, next or prior pointers for owner or member records. (Member records have owner pointers.)
Case 2. Owner record has first pointer, member records have next pointers (member records may or may not have owner pointers).
Case 3. Owner record has first and last pointers, member records have next pointers (member records may or may not have owner pointers).
Case 4. Owner record has first and last pointers, member records have next and prior pointers (member records may or may not have owner pointers).
A further characteristic of the hardware/firmware system is its recognization of four different classes or formats of pointers. Within a record these classes are referred to as class zero, which are used for virtual memory records only; class one, which are used for virtual memory records only; class two, which are used for data records only; and class three which are used for database records only.
All four pointer classes have a common meaning for their first two bits. The first bit, the EOS bit, is the End-of-Set indicator. When this bit is set to one, the pointer by definition points to an owner record. The second bit, the NINS bit, is the Record-Not-Inserted indicator. When this bit is set to one the record is not currently inserted as a member of the set being referenced.
The class zero pointer format is shown in FIG. 15E. The EOS bit 1540 and Not Inserted bit 1541 occupy the first two bit positions. The SRA field 1542 is a 14-bit offset, which is a displacement within a given segment, which points to the record located in that segment. The SRA field obtained from class zero pointers is always merged with a segment number which is generally obtained from the base register used in addressing records via class zero pointers.
The class one pointer is shown in FIG. 15F. The EOS bit 1550 and Not Inserted bit 1551 are of standard definition. The Field SEG, SRA 1552 is composed of the standard segmented address with SEG and SRA as defined previously. These pointers are used to directly address a record, with the segment number being directly supplied via the pointer.
For class two and class three pointers which are used with database records, the firmware/hardware system recognizes a convention that with each base register of the system as described previously (see FIG. 2, 202) there is an associated index register. General registers 8-15, 201 correspond to Index registers 0-7 respectively. The index register number IXR.sub.i is matched with base register BR.sub.i. For instance, for base register BR3, index register IXR3 (GR11) would contain an Area-Page-Line number pointer (see FIG. 15H) whose current SEG, SRA address would be contained in base register BR3. Thus, the user is able to address his record via either a base register with SEG, SRA address or via a database pointer as contained in the index register of the Area-Page-Line format.
The hardware/firmware instructions operating on database records implement the capability of automatically converting from Area-Page-Line pointers into SEG, SRA addresses. Hence, all actual memory references made by the database instructions use the standard hardware mechanism which addresses memory with segment and SRA number, with the conversion from Area-Page-Line as contained in an index register made automatically by the hardware if necessary.
There is a temporary one-to-one correspondence between a page in a user file (area) and a segment as recognized by the hardware/firmware. Thus, through the page descriptor mechanism to be described below, the hardware/firmware converts any given page number into a segment number.
The class two pointer format is shown in FIG. 15G. The EOS and Not Inserted bits are shown in fields 1560 and 1561. The Page number is contained in field 1562. The Line number is shown in field 1563 and represents the number of a record in a page and area. A full Area-Page-Line number pointer is obtained when using class two records by obtaining the Area number obtained from the index register which would be referenced by the database instruction.
The class three pointer formats are shown in FIG. 15H. The EOS and Not Inserted bits are shown in field 1570 and 1571. The Area number is shown in field 1572. This refers to the user file number. The Page number 1573 and the Line number 1574 address a particular record in the user file.
FIG. 16A illustrates the database page which is a portion of a user file (area) as recognized by the hardware/firmware system. Database pages contain the database records as described in FIG. 15B previously. As said previously, there is a one-to-one correspondence between a database page and a segment at the time when the database page is resident in main memory.
The page header 1601 contains certain information relevant to the page in which it is contained. For example, it would describe the length of the page in bytes and also the number of records (lines) contained in the page. It would also contain information such as the write bit which would be set upon the writing into the page when it was contained in main memory. Following the page header, the next major portion of the database page is the line offset array 1602. This is an array of 16-bit elements which correspond on a one-to-one basis with valid line numbers for the page. For each element of the line offset array there is a two bit D-switch 1604 and a 14-bit offset 1603. The D-switch describes the state of the record as inactive, logically deleted, physically deleted, or active. The offset is a 14-bit pointer to the record which is a relative displacement from within the beginning of the page. It can be seen that hardware is able to address a database record in this page by using the offset concatenated with the segment number corresponding to this page. The method of obtaining the corresponding segment number will be described below. The remaining portion of the database page is composed of the actual database records as shown in record 1610 and record 1612. These records may be located in any portion of the page (segment) and are not necessarily in the same order as their position in the line offset array. If the D switch describes the record state as inactive or physically deleted, then the offset will be set to zero and the record will not exist.
The actual database page is addressed by a page descriptor as shown in FIG. 16B. The Segment Number 1625 of the page descriptor contains the segment number corresponding to this page number after it is loaded in main memory. The Area Number 1622 contains the area number (file) of this page. The Page Number 1624 is the actual page number. The Last Page Indicator 1626 is equal to one for the highest page number of a given area. The Shift Count 1623 contains the number of bits of the page number. The hardware/firmware system recognizes a variable length page number when utilizing Area-Page-Line pointer formats. The Next Descriptor 1620 is used to point to the next page descriptor in a chain of page descriptors. The Prior Descriptor 1621 points to the previous descriptor in the page descriptor chain. The use of these page descriptor chains will be described below.
The page descriptor chain is the hardware/firmware mechanism used to indicate which pages of files are currently located in the main memory of the computer system. For each page present in memory a page descriptor is located in a single system recognized chain, which is pointed to by the Integrated Access Control pointer shown in FIG. 16C. The Integrated Access Control pointer represents a one word extension to the System Base described previously. The IAC pointer is located at an address BAR plus 92, which is one word past the end of the System Base. The format of the IAC pointer contains a Must Be Zero field 1630, a G-number 1631, and a Displacement 1632. The G-number is a number of a G-segment as described previously. The Displacement is a displacement within that G-segment where the beginning of the page descriptor ring begins. The page descriptors of all of the pages contained in main memory are then linked together in the traditional chain format. The next descriptor and prior descriptor fields form the link.
FIG. 17 shows the hardware/firmware flow chart for implementing the location of a database page in main memory. This firmware is used to take an Area-Page-Line number pointer and determine firstly if the page is in main memory, and, secondly, to deliver the page descriptor of that page if it is found to be present in main memory. The firmware starts as shown in 1701.
The first firmware action occurs as shown in 1702 where a main memory fetch of the IAC pointer is made at location BAR plus 92. (The IAC pointer is incorporated in the System Base as shown in FIG. 6). As a result of this memory fetch, memory access exception 1703 may occur. Examples of memory access exceptions would be out of physical memory or a memory read error. The next step taken by the firmware is shown in 1704 where the MBZ field is checked to be zero. (Reference FIG. 16C). If the field is found not to be zero, then a system check 1705 occurs. Upon the occurrence of a system check, the system goes into a diagnostic state.
If the MBZ field is zero, block 1706 is next executed. The G-number from the IAC field is transferred into temporary register G. The displacement field is transferred into temporary register D. The displacement is also transferred into scratchpad memory of a location referred to as "first pointer." Block 1707 is next executed. The fetch of main memory is made at the address G, D to fetch a page descriptor (see FIG. 16B). This fetch is made according to the convention of G, D addressing as described previously. G, D access exception 1708 may occur as a result of this memory fetch (e.g. out of segment, illegal G-D segment descriptor). Step 1709 is next executed by the firmware. The area number and page number of the Area-Page-Line number being checked by the firmware subroutine is compared against the Area Number field 1622 and the Page number field 1624 of the page descriptor for a match. If the area and page numbers match, block 1710 is executed in which the firmware routine ends with the page descriptor just fetched from main memory being loaded into scratchpad memory.
If the area or page number of the current page descriptor is not equal to the area and page number of the Area-Page-Line pointer being checked, block 1711 is executed. The Next Descriptor field 1620 of the page current page descriptor is checked against the contents of temporary scratchpad location "first pointer." If these two values are not equal, block 1713 is executed in which the temporary register D is loaded with the Next Descriptor field the current page descriptor. Following block 1713 a branch by the firmware is made to block 1707 where the new page descriptor (which was addressed by the Next Descriptor) is now fetched and will be subsequently checked.
Going back to block 1711, if the Next Descriptor is equal to the contents of the "first pointer" temporary scratchpad location, this indicates that the entire ring of page descriptors describing all pages present in memory has now been exhausted without finding the area-page being searched for by the firmware. In this case, a paging exception occurs 1712, indicating that the desired page is not located in main memory. Following the exception, appropriate software action will occur resulting in the eventual moving of this desired page to main memory.
Now referring to FIG. 18, there is shown a block diagram representation on the hardware required in order to implement a mechanism for locating a database page in main memory. This mechanism is activated by setting the activate locate page flip-flop 1851, which is located in the auxiliary memory 1317A of the arithmetic logic unit 1317 of the central processing unit 104. Before setting the activate locate page flip-flop 1851, the Area-Page number whose page descriptor is to be located is loaded in the Area-Page register 1852. The contents of the Area-Page register will then be used to detect when the proper Area-Page descriptor has been located.
The setting of the activate locate page flip-flop 1851 to a logical one enables AND gate 1854, which allows the contents of the Boundary Address Register 1853 to be input to the adder 1856. The other input to the adder is a constant value of 92, which is stored in a hardware register 1855. The adder 1856 is located in the arithmetic logic unit 1317 of the central processing unit 104. The output of the adder 1856 is coupled to AND gate 1857. AND gate 1857 is enabled by the activate locate page flip-flop 1851. The enabling of AND gate 1857 allows the contents of adder 1856 to be transferred to the memory address register 1858 of the memory system 1859. Thus an address of BAR plus 92 is transferred into the memory address register 1858. As described supra, this address is the address of the integrated access control pointer located in the System Base. The IAC pointer will be read from the memory system 1859. The output signal from the activate locate page flip-flop 1851 is inverted by the inverting amplifier 1886 to a logical zero which is in turn used to set the read/write flip-flop 1887 of the memory system to a logical zero (memory read operation). Thus, after the memory system detects the loading of the memory address register 1858, a memory read operation is initiated. As a result of the memory read operation, memory access exceptions may occur. As described previously, memory access exceptions cause the activation of the exception handler mechanism. The exception handler mechanism is activated by the setting of the memory access exception flip-flop 1860 if such exceptions are detected by the memory system. If the memory operation completes normally, the memory operation complete flip-flop 1861 is set to logical one and the contents of the IAC pointer read from the memory are transferred to the memory data register 1862. The memory operation complete flip-flop 1861 then enables the transfer of the contents of the memory data register through AND gate 1863. These contents, which represent the IAC pointer, are of the format as shown in FIG. 16C.
The MBZ field 1630 of the IAC pointer is coupled to a comparator 1865, located in the arithmetic logic unit 1317. The comparator 1865 compares the MBZ field with a register 1864 containing a value of binary 0. If a not equal condition is detected, a system check flip-flop 1866 is set to a value of 1.
If the comparator 1865 detects an equal condition, the equal signal enables the transfer of the G number 1631 and the displacement field 1632 of the IAC pointer through AND gate 1867 into the G register 1873 and the D register 1874. The logic circuits for the transfer into the D register 1874 will be described infra.
The setting of the active locate page flip-flop 1851 in turn causes the setting of a first time flip-flop 1869. This flip-flop is set to a value of 1 to indicate that the D register 1874 is being loaded for the first time. Thus, the output of the first time flip-flop 1869 is coupled to AND gate 1871 along with the output of AND gate 1867, which contains the D displacement field of the IAC pointer. Through AND gate 1871, the IAC pointer's displacement field is transferred via OR gate 1872 into the D register 1874. The output of the first time flip-flop 1869 is also coupled to AND gate 1868 along with the output of AND gate 1867 (which contains the displacement field of the IAC pointer). Thus, via AND gate 1868 the first pointer register 1870 is loaded with the initial displacement value obtained from the pointer. The use of the first pointer register 1870 will be described infra. It can also be noted that the output of the first time flip-flop 1869 is coupled to the reset input of the first time flip-flop itself. Thus, after the first time flip-flop has been set to a logical one and allowed the first pointer register 1870 and D register 1878 to be loaded, the first time flip-flop is then reset to a logical zero value.
Once the G register 1873 and the D register 1874 have been loaded, the G, D access mechanism 1875 is activated. This mechanism makes a fetch of main memory at the address given by G and D registers to fetch a page descriptor (see FIG. 16B). This mechanism makes the main memory fetch according to the convention of G, D addressing as described previously. G, D access exceptions may occur as the result of this memory fetch (e.g., out of the segment, illegal G-D segment descriptor). If such exceptions are detected, the G, D access exception flip-flop 1876 is set to a logical one value which is turn activates the exception handler mechanism. Otherwise, upon completion of the G, D access, the mechanism 1875 transfers the data fetched into the page descriptor register 1877. The data transferred into the page descriptor register 1877 is of the format as shown in FIG. 16B.
After the loading of the page descriptor register 1877, the area number 1622 and page number 1624 are input to a comparator 1878 located in the arithmetic logic unit 1317. At this point the area page number located in the Area-Page register 1852, loaded at the initiation of the locate page mechanism, is also input to the comparator 1878. If the comparator finds an equal comparison, the desired page descriptor has been located and the mechanism has completed its function. Thus, the equal compare line of the comparator 1878 is coupled to the locate page complete flip-flop 1879. This signal sets this flip-flop to a state of logical one, signalling completion of the locate page mechanism.
If comparator 1878 signals a not equal condition, the not equal signal which is coupled to AND gate 1880 enables the transfer of the next descriptor 1620 from the page descriptor register 1877 to comparator 1883 and also to AND gate 1885. Comparator 1833 compares the next descriptor 1620 with the first pointer register 1870. If an equal compare condition is detected, the entire pointer chain of page descriptors has been searched and the desired page descriptor has not been located. Under these conditions, the desired area page is not in main memory and thus the equal of comparator 1833 is used to set the paging exception flip-flop 1884. The exception handler mechanism is then activated by the setting of flip-flop 1884.
The output of AND gate 1880, containing the next descriptor 1620 from page descriptor register 1877, is also coupled to AND gate 1885. This AND gate is enabled by the not equal signal of comparator 1883. The not equal condition occurs when the end of the page descriptor chain of pointers has not been reached. Thus, when the not equal sign is a logical one, the next descriptor field is transferred from AND gate 1883 to AND gate 1882. The other input to AND gate 1882 is a signal from an inverting amplifier 1881. This signal from AND gate 1881 represents the inverted output of the first time flip-flop 1869. Thus, the signal output by an inverting AND gate 1881 is at a logical one state when the first time flip-flop 1869 is at a logical zero and hence AND gate 1882 is enabled to transfer the next descriptor field 1620 to OR gate 1872, which is in turn coupled to the D register 1874. Through these series of logic gates, the next descriptor field has been transferred from the page descriptor register 1877 into the D register 1874 and the G, D access mechanism is now ready to be activated again. The cycle of G, D accessing is now reactivated and a new page descriptor is fetched and loaded in the page descriptor register 1877. This operation of fetching new page descriptors is repeated until either the comparator of 1878 detects the desired page descriptor or until the comparator 1883 detects the end of the page descriptor chain.
Two more vital elements of the hardware/firmware system described here are shown in FIGS. 19A and 19B. The set descriptor, FIG. 19A, is used to describe the properties of a given set. As shown in FIG. 19A the P field 1802 is a two-bit field describing the pointer class (mode) of the record pointers in this set. All records, both owners and members, have pointers of the same pointer class for a given set. The Owner Pointer field of the set descriptor 1803 is set to one if member records contain an owner pointer to the owner record (reference FIG. 15C). The Other Pointers field 1804 describe whether owners and members have first pointers, last pointers, next pointers and prior pointers. The Set Implementation Mode field K 1805 describes the mode of set implementation being used for the current set. Only the mode of ring sets is detailed in this disclosure. However, the capability for extension to other modes of set implementation such as table array or list array exists. The Displacement field 1806 is used to indicate the offset from the beginning of the record in memory to the beginning of the pointer sequence in that record. (Reference FIGS. 15A and 15B). The set descriptor as described in FIG. 19A is always accessed by the database instruction when operating on a set to supply the hardware/firmware with a description of the referenced set.
The record descriptor as shown in FIG. 19B is used to described certain properties of record. The F field 1820 is used to describe the record format. The format of records is either virtual memory record or database record as described in FIG. 15A and 15B. The Record Type field 1821 indicates the type of record and is eventually loaded into the type field of the actual record in memory as shown in FIGS. 15A and 15B. The Record Length field 1822 indicates what the actual length the record will be in main memory and is loaded into main memory records as shown in FIGS. 15A and 15B.
The actual database instructions are of one of the six formats as shown in FIGS. 20A to 20F.
The GROP format shown in FIG. 20A contains the Operation Code 1910, the Must Be Zero field 1911, a Base Register number 1912, and a Complementary Code 1912. The Base Register contains the segmented address of a record. The Complementary Code is used for a further differentiation of the particular instruction described by the Operation Code.
The XI format shown in FIG. 20B contains an Operation Code 1920, a Complementary Code 1921 used to further differentiate the Operation Code, an Address Syllable 1922, a Must Be Zero field 1923, a Logical Delete field 1924, a Pointer Mode field 1925, and a BR field 1926. The Base Register contains a segmented address of a record. The Address Syllable 1922, for some of its usages points to a set descriptor of the set to be operated on. The Address Syllable is developed into a segmented address according to the rules for address development as described previously.
The DXDX format shown in FIG. 20C is composed of an Operation Code 1930, Complementary Code 1931 which is used to further differentiate the instruction, one Address Syllable AS1 1932, a Must Be Zero MBZ1 field 1933, a Base Register 1934, a second Must Be Zero MBZ2 field 1935, and a second Address Syllable AS2 1936. The Base Register again contains the segmented address of a record. The first Address Syllable AS1 1932 points to a set descriptor. The second Address Syllable AS2 1936 is used to address a binary integer.
The BRX format shown in FIG. 19D contains an Operation Code 1940, a Type field 1941 which is used to further differentiate the instruction, a Base Register field 1942, and an Address Syllable 1943. The Base Register contains the segmented address of a record. The address Syllable is used to address a set descriptor.
The DXGR format shown in FIG. 19E contains an Operation Code 1950, a Type Field 1951 which is used to further differentiate the instruction, a first Base Register number BR1 1952, an Address Syllable 1953, a Must Be Zero MBZ1 field 1954, second Base Register number BR2 1955, a Before-After-First-Last field 1956 and a second Must Be Zero MBZ2 field 1957. The two base registers are used to address two different records located in memory. The Address Syllable is used to address the set descriptor. The Before-After-First-Last field describes the desired positioning of a record within the set.
The OPDD format shown in FIG. 19F contains an Operation Code 1960, a Primitive field 1961 used to describe a particular database operation, a Type field 1962 used to further differentiate the instruction, a P field 1963 used to describe the pointer field, and the First-Last-Next-Prior pointer field 1965 which describes the other pointer of owner and member records, the Displacement field 1966 describes the offset to the beginning of the pointer sequence, and a BR field 1967 which contains the number of a base register. The base register contains the segmented address of a record in main memory.
The find owner database instruction is a firmware/hardware instruction which fetches a set descriptor, which along with a base register BB, accesses the owner pointer of the member record. The owner pointer is converted into a segmented address according to its pointer class, and then the segmented address is loaded into the base register BR. If the pointer is a part of a database record, the pointer is also loaded into an index register. The find owner instruction is of the XI format shown in FIG. 20B.
The firmware flow chart for the find owner instruction is shown in FIGS. 21A through 21E. Operation 2001 of the firmware flow chart checks the format of the instruction. Then operations 2003 through 2005 fetch a set descriptor pointed to by the address syllable of the instruction and do certain preliminary checks on that set descriptor. Operation 2007 fetches a pointer which is addressed by the base register BR 1926 of the instruction, indexed by the displacement 1806 which is obtained from the set descriptor (which locates the pointer sequence of the record - see FIGS. 15A, 15B and 19A). Operation 2009 determines the pointer mode from the set descriptor (see FIG. 19A) and follows specialized actions according to the pointer mode.
Looking at FIG. 21A in more detail first in operation 2001 the MBZ field 1923 of the instruction (reference FIG. 20B) is checked to be zero. This check for zero is made by transferring the instruction from the instruction fetch unit (reference FIG. 13A, IFU 1318) to a register in the arithmetic logic unit 1371. If the hardware check made in this register finds the MBZ not zero, the firmware makes a branch to the exception handler as shown in FIG. 21A, 2002. This exception is called an illegal format field exception. If the MBZ is zero, the firmware proceeds to operation 2003 where a fetch to main memory of 3 bytes is made at an address determined by the address syllable AS 1922 of the instruction. The development of the address syllable into a segmented address is described in the patents Segment Address Development and Address Development Technique Utilizing a Content Addressable Memory. This address development is performed in the address control unity (reference FIG. 13A, ACU 1319). As a result of the fetch to main memory, memory access exceptions may occur as shown in FIG. 21A, 2004. Some examples of memory access exceptions are out of segment, segment not present or out of main memory. The 3 bytes fetched constitute a set descriptor, as described in FIG. 19A.
The next step shown in FIG. 21A is a check of the K bit 1805 of the set descriptor (reference FIG. 19A) to see that the K bit is equal to zero. This check is made by transferring the set descriptor which was originally fetched from main memory and transferred to the data management unit (reference FIG. 13A, 1321) to the arithmetic logic unit 1317. If the K bit portion of the set descriptor is found to be non-zero, an unavailable set feature exception occurs 2006.
If the K bit is zero, the firmware proceeds to operation 2007 as shown in FIG. 21A where a fetch to main memory is made at an address given by the contents of the base register BR 1926 found in the instruction format (reference FIG. 20B) plus the displacement 1806 of the set description (reference FIG. 19A). This address at which the fetch is made is the address of the owner pointer in the pointer sequence of the record referenced by the instruction (see FIG. 15C). As a result of this main memory fetch, memory access exceptions 2008 may occur. The owner pointer fetched is stored in scratch pad location "X". The addition of the displacement field (1806, FIG. 19A) to the contents of the base register is performed in the address control unit (reference 1319 FIG. 13A).
The firmware proceeds to operation 2009 as shown in FIG. 21A where the pointer mode of the record being referenced is determined. This determination is made by examining the P field 1802 of the set descriptor fetched in operation 2003 (reference 1802 of FIG. 19A). This check is made in the arithmetic logic unit 1317 of FIG. 13A. For class zero pointers, a branch is made to 2013 of FIG. 21B. For class one pointers, a branch is made to 2011 of FIG. 21D. For class 3 pointers, a branch is made to 2012 of FIG. 21E.
In FIG. 21B the handling of class zero pointers is described. Operation 2014 develops the effective address of the record pointed to by the pointer stored in scratch pad memory location "X" fetched in operation 2007 of FIG. 21A. Operations 2015 through 2019 perform a check of the status of the record pointed in scratch pad memory location "X". This pointer points to the owner record of the set. The format for a class zero pointer is described in FIG. 15E. If the record pointed to by the owner pointer is found to be in the active state, then the SRA portion of that pointer (reference 15E) is loaded into the base register and the instruction is complete.
Looking at the details of FIG. 21B, in operation 2014 the effective address of the owner record is developed in the address control unit (reference 1319 of FIG. 13A) by obtaining the segment number from the base register BR and obtaining the SRA of the segmented address from the pointer X fetched in operation 2007. In operation 2015 this segmented address formed in operation 2014 is used to fetch the D-switch of the record from main memory (reference FIG. 15A for a description of the D-switch 1502 of a record). As a result of this main memory fetch, memory access exceptions 2016 such as out of segment or out of physical memory may occur.
The 2-bit D-switch fetched from main memory is transferred from the data management unit (reference 1321 of FIG. 13A) to the arithmetic logic unit 1317. This transfer is accomplished under control of the firmware using micro-instructions to effect the transfer from the register in the data managment unit to the register in the arithmetic logic unit.
In operation 2019 the D-switch, which is now located in the arithmetic logic unit 1317, is checked to see if it is equal to zero. If this is true, then the firmware branches the exception handler 2020, reporting a record deleted exception.
Otherwise, the D-switch must be equal to 1, the record active state, and the firmware branches to operation 2021. In this operation the SRA portion of the owner pointer (reference FIG. 15E) is transferred to the offset portion of the base register (reference 202, FIG. 2). This transfer is a 15-bit transfer of the right most 15 bits of the pointer stored in scratch pad memory location "X". Only 15 bits are transferred since the owner pointer (reference FIG. 15E) has the EOS bit (1540) equal to 1, since the owner pointer by definition always has the EOS bit set. A zero is desired in the first bit position of the SRZ field 202 of the base register and thus the hardware/firmware forces this bit to zero while transferring the other 15 bits of the pointer. The next operation is 2022, where the instruction is now complete and a branch is made to the next instruction by the firmware.
In FIG. 21C the handling of class one pointers is described. Operation 2023 develops the effective address of the record pointed to by the owner pointer stored in scratch pad location "X" fetched in operation 2007 of FIG. 21A. Operation 2024 through 2029 check the status of the record pointed to by the pointer stored in scratch pad memory location "X". This pointer points to the owner record of the set. The format for class one pointers is described in FIG. 15F. If the record pointed to by the owner pointer is found to be in the active state, then the SEG, SRA portion that pointer is loaded into the base register and the instruction is complete.
Looking at the details of FIG. 21C, in operation 2023 the effective address of the owner record is developed in the address control unit (reference 1319 in FIG. 13A) by obtaining the segment number and SRA from the pointer fetched in operation 2007 and stored in scratch pad memory at the location "X". In operation 2024 this segmented address formed in operation 2023 is used to fetch the D-switch of the record from main memory (reference FIG. 15A for a description of the D-switch of a record). As a result of this main memory fetch, memory access exceptions 2025 such as out of segment or out of physical memory occur.
The 2-bit D-switch fetched from main memory is transferred from the data management unit (reference 1321 of FIG. 13A) to the arithmetic logic unit 1317. This transfer is accomplished under the control of the firmware using micro-instructions to effect the transfer from the register in the data management unit to the register in the arithmetic logic unit.
In operation 2028 the D-switch which was loaded in the arithmetic logic unit 1317 is checked to see if it is equal to zero. If this is true, then the firmware branches to the exception handler 2029, reporting a record deleted exception.
Otherwise, the D-switch must be set to the record active state and the firmware branches to operation 2030. In operation 2030 the right most 31 bits of the pointer stored in scratch pad memory location "X" fetched from main memory are loaded in the right most 31 bits of the base register BR reference FIG. 20B, field 1926). Only 31 bits are transferred since the owner pointers EOS bit 1551 is (reference FIG. 15F) equal to one since the owner pointer by definition has the EOS bit set and it is actually desired that the 1st (leftmost) bit of the base register be left zero. The hardware/firmware forces the 1 st bit of the base register to D. The next operation is 2031 where the instruction is now complete and a branch is made to the next instruction by the firmware.
In FIGS. 21D and 21E the handling of class 2 and class 3 pointers is described. In operations 2032 and 2033 the Area-Page-Line number address of the record referenced by the instruction is formed from the pointer located in scratch pad memory location "X", which was fetched in operation 2007, and also the third through the tenth bit of the index register in the case of class 2 pointers. Operation 2034 fetches the page descriptor (reference FIGS. 16B) of the page whose number is given in Area-Page-Line number. The line number is then converted into a segmented address in operations 2036 through 2043, according to the mechanism described previously with reference to FIG. 16A. The D-switch of the line offset array item (reference 1602 of FIG. 16A) is checked in operations 2047 through 2050 for the state of the line (record). If the line is in the active state, the segmented address corresponding to this line number is then loaded in the base register whose number is given in the instructions format (reference field 1926 of FIG. 20B). In operations 2053 through 2057, the index register corresponding to the number given in the base register field 1926 of the instruction format is also loaded with an Area-Page-Line number of Page-Line number, according to the pointer class. The instruction is then complete.
Looking at the details of FIGS. 21D and 21E, in 2011 the case of a class two pointer is handled. The firmware branches to operation 2032 for class two pointers, where the Area number for the Area-Page-Line number is fetched from the index register bits 2 through 9. The Page-Line number is fetched from the scratchpad memory location "X". The Area number is concatenated with the Page-Line number and is then loaded into a temporary register referred to as Area-Page-Line. This register is located in the arithmetic logic unit 1317.
In 2012 the case of a class 3 pointer is handled. The firmware branches to operation 2033 where the contents of scratchpad memory location "X" are transferred into the temporary register Area-Page-Line.
Both operations 2032 and 2033 branch to operation 2034 where the page descriptor corresponding to the page number given by the temporary register Area-Page-Line is fetched. This fetch is made by the locate page firmware subroutine described in FIG. 17. As a result of this firmware subroutine, a paging exception 2035 may occur. If the page descriptor is successfully fetched, the firmware moves to operation 2036 where the line number from the temporary register Area-Page-Line is transferred into another temporary register W, located in the arithmetic logic unit (1317 of FIG. 13A). This transfer of the line number to register W is a transfer of a number of bits given by the shift count field of the page descriptor (reference Field 1623 of FIG. 16B).
In operation 2037 the firmware fetches the segment descriptor of the SEG number obtained from the page descriptor (reference FIG. 16B, Field 1625). As a result of this memory fetch, memory access exceptions 2038 may occur. The segment descriptor fetched in operation 2037 is used in operation 2039 to obtain the base address of that segment. As previously described with reference to FIG. 16A, the beginning of a database page corresponds to the beginning of the equivalent segment. Thus, the base address of the segment is used in operation 2039 as the address of the page header (reference 1601 of FIG. 16A) to fetch the maximum line number. This maximum line number fetched is transferred to a temporary register Z in the arithmetic logic unity 1317. As a result of the memory fetch in operation 2039, memory access exceptions 2040 may occur.
In operation 2041 the validity of the line number W is tested by checking that the absolute value of W is less than the maximum line number Z. If W is not less than Z, a branch is made by the firmware to the exception handler, where an invalid page format exception 2042 occurs. Otherwise, the firmware moves to operation 2043 where the 16-bit line offset array item 1602 is fetched at an address given by the segment base plus the length of the page header 1601 (81 bits) plus the line number W times 16 bits (these 16 bits representing the length of a single line offset array item). As a result of this memory fetch, memory access instructions 2044 may occur.
In operation 2045 the D-switch 1604 of the line offset array item is transferred into a register in the arithmetic logic unit 1317. The firmware then branches to 2046, FIG. 21E.
Operation 2046 moves to operation 2047 where the D-switch which is now located in arithmetic logic unit 1317 is checked to see if it is equal to zero. If this is true, then the firmware branches to the exception handler 2048, reporting a line not in use exception. Otherwise, in operation 2049 the D-switch is checked to see if it is equal to one or three. If either of these conditions are true, a branch is made to the exception handler 2050, with a line deleted exception being reported.
Otherwise, the D-switch must be equal to 2, the record active state, and the firmware branches to operation 2051. In operation 2051 the segment number SEG of the current database page, obtained from the page descriptor (reference FIG. 16B, Field 1625), is loaded into the base register BR whose number is given in Field 1926 BR of the instruction format shown in FIG. 20B. The segment number is transferred into the base register at bits 4 through 15. The next operation executed is 2052 where the offset portion of the line offset array item 1603 is transferred into the SRA portion of the base register BR (Field 202 of FIG. 2).
In operation 2053 the pointer mode P of the set descriptor fetched in operation 2003 (reference 1802 of FIG. 19A) is examined. If the mode is 3, operation 2054 is executed in which the right most 30 bits of the contents of scratch pad memory location "X" (starting at bit 2) are transferred into the right most 30 bits of the index register IXR, starting at bit 2. Following operation 2054, Operation 2056 is executed in which the instruction is complete and the firmware branches to the next instruction. Going back to operation 2053, if the pointer mode is found by the arithmetic logic unit to be 2, the microinstruction flow branches to operation 2055 in which the right most 22 bits of the pointer stored in scratch pad memory location "X" (starting at bit 2 of the pointer) are transferred into the right most 22 bits of the index register IXR, starting at bit 10 of the index register. Following operation 2055, operation 2057 is executed in which the instruction is complete and the firmware branches to the next instruction.
Now referring to FIGS. 22A through 22D, there is shown a block diagram representation of a hardware implementation of the find owner database instruction of the present invention. FIGS. 22A through 22C shows the hardware logic which actually stores data and performs various operations on the data in order to implement the find owner instruction. FIG. 22D shows the control logic used to sequence transfers and operations on the data in implementing the find owner instruction. The control logic shown in FIG. 22D is often referred to as cycle counter logic.
Briefly summarizing the operation of the control logic shown in FIGS. 22D to facilitate an understanding of the hardware logic in FIG. 22A through 22C, first it can be seen that flip-flops cycle 1 through cycle 7 2401 through 2407 define a series of 7 sequential time periods. Cycle A0 through cycle A5 2411 through 2416 define a 6-cycle control sequence which is used for controlling the operations for implementing the find owner database instruction in the case where a virtual memory record, pointer mode type 0 record is being operated on. Cycle B0, cycle B1, and cycle B4, in conjunction with the A cycles (as will be explained below), define a cycle control sequence which is used in implementing the hardware operations for the find owner database instruction in the case where a virtual memory record, pointer mode type 1 record is being operated on. Cycle C0 through cycle C12 2431 through 2443 define a 14-cycle control sequence which is used in controlling the hardware operations for implementing the find owner database instruction in the case where a database record, pointer mode type 2 record is being operated on. Cycle D1 2451 and cycle D11 2452, in conjunction with the C cycles, define a control sequence which is used in controlling the hardware operations implementing the find owner database instruction in the case where a database record, type 3 pointer record is being operated on.
Looking at FIGS. 22A through 22C, in more detail, upon receipt of a find owner instruction as indicated by the find owner instruction detector 2201, shown in FIG. 22A, the instruction is loaded in the instruction buffer 2202. The instruction buffer is located in the instruction fetch unit 1318 of the central processing unit 104. As noted supra, the find owner instruction transferred to the instruction buffer 2202 is of the XI format shown in FIG. 20B. The MBZ field 1923 is immediately compared with the 0 bits 2204 by means of comparator 2203. If the comparator 2203 gives a not equal signal, an illegal format field exception is detected and the illegal format field flip-flop 2205 is set, thereby causing activation of the exception handler mechanism. Execution of the find owner instruction is then complete. If the comparator 2203 indicates an equal compare, then the execution of the find owner instruction continues as described below. It can be noted that the equal signal of comparator 2203, which is raised to a logical one value if the MBZ field 1923 is found equal to 0, is input to the set input of the cycle 1 flip-flop 2401 shown in FIG. 22D. Thus, the equal compare initiates the cycle sequence cycle 1 through cycle 7.
AND gate 2206 is enabled by the cycle 1 signal to transfer the address syllable 1922 from the instruction buffer 2202 to the address control unit 2207 (see FIG. 22B). This transfer is made via OR gate 2217 to which AND gate 2206 is coupled. When supplied with an address syllable, the address control unit 2207 translates that address syllable into a memory address as described in the patent application Segmented Address Development. The memory address developed by the address control unit 2207 is transferred to the memory address register 2209. Since OR gate 2218 has as one of its inputs the cycle 2 signal, at cycle 2 the AND gate 2219 to which OR gate 2218 is coupled is enabled to transfer the memory address in the memory address register 2209 to OR gate 2220. OR gate 2220 is in turn coupled to the memory address register 2210 of the memory system 2213.
The find owner instruction detector 2201 is also coupled to inverting AND gate 2211, which is in turn coupled to the memory system read/write flip-flop 2212. The find owner instruction detector signal being a logical one results in the output of gates 2211 being a logical zero, thereby resulting in the read/write flip-flop 2212 being set to a value of 0. When the memory system 2213 has detected that the memory address register 2210 has been loaded and that the read/write flip-flop 2212 is at a logical zero value, a memory read operation is initiated. Operation of a memory system is described in the patent application entitled Segmented Address Development. As the result of a memory operation, memory access exceptions 2214 may occur as described in the patent application entitled Segmented Address Development. If such exceptions occur, the memory access exception flip-flop 2214 will be set to a logical one value. The exception handler, as described in the patent application entitled Exception Handling, will be activated. Otherwise, the memory operation completes normally and the memory operation complete flip-flop 2215 will be set to a logical one. Upon the transition of the memory operation complete flip-flop 2215 to a logical one state, the data read from the memory system 2213 has been transferred to the memory data register 2216 (shown in FIG. 22C). The transition of the memory operation complete flip-flop 2215 to a logical one thus indicates that the set descriptor addressed by the address syllable of the find owner instruction (see FIG. 19A) has been placed in the memory data register 2216.
At this point it can be noted that the output of cycle 2 flip-flop 2402 of FIG. 22D is also coupled to AND gate 2481, which is enabled by the memory operation complete signal from the memory operation complete flip-flop 2215 of FIG. 22B. Thus, at the completion of the memory operation reading the set descriptor addressed by the find owner instruction, cycle 3 of the cycle sequence in initiated.
The K field 1805 of the set descriptor located in the memory data register 2216 is coupled to AND gate 2221, which is enabled by the cycle 3 signal as is shown in FIG. 22C. The output of AND gate 2221 is in turn input to the comparator 2222. The other input to comparator 2222 is a set of 0 bits 2223. If comparator 2222 finds the K field 1805 not equal to 0, then the not equal signal of comparator 2222 is raised to a logical one and the unavailable set feature exception flip-flop 2224 is set to a logical one. The exception handler, as described in the patent application entitled Exception Handling, will then be activated and the instruction will be complete. If the K field 1805 is found to be 0, the equal signal of comparator 2222, which is coupled to the AND gate 2482 of FIG. 22B will be raised to a logical one thus enabling the output of the cycle 3 flip-flop 2403 to set the cycle 4 flip-flop 2404.
The P field 1802 of the set descriptor contained in the memory data register 2216 is coupled to AND gate 2225 which is enabled by the cycle 4 signal. Thus, at cycle 4 the P field 1802 is transferred via AND gate 2225 into the P register 2226 to which AND gate 2225 is coupled.
The displacement field 1806 of the set descriptor contained in the memory data register 2216 is coupled to AND gate 2227, which is also enabled by the cycle 4 signal as is shown in FIG. 22B. Thus, in cycle 4 the displacement field 1806 is transferred into the displacement register 2228.
It can also be noted that the cycle 4 signal is one of the inputs to OR gate 2270, which is coupled to AND gate 2271. Thus, in cycle 4 AND gate 2271 to which the BR field 1926 of the instruction is coupled is enabled and the output of AND gate 2271 is transferred to the BR base register input 2208 of the address control unit 2207.
When the address control unit 2207 is supplied with a base register number in its BR base register input 2208, the resulting action is the readout of the contents of that base register whose number was inputted. This operation is a typical scratchpad memory read operation. The base register contents output from the address control unit are outputted to the address control unit's base register/output register 2230. The base register output register 2230 comprises one of the two inputs to adder 2229. The other input to adder 2229 is the displacement register 2228, which was previously loaded. The output of adder 2229, which constitutes the base register BR with its offset field (see FIG. 2, 2020) incremented by the displacement contents of register 2228 is coupled to AND gate 2231 as can be seen in FIG. 22A. AND gate 2231 is enabled by the cycle 5 signal. The output of AND gate 2231 is in turn input to OR gate 2217 which is coupled to the address control unit. The address control unit, when supplied with a base register's contents (see FIG. 2), translates those contents into a memory address as described in the Segmented Address Development patent. Thus, the output of the address control unit 2207 is again an address transferred to the memory address register 2209. Since another of the inputs to OR gate 2218 is the cycle 6 signal as can be seen in FIG. 22B, at cycle 6 the address in the address register 2209, which is coupled to AND gate 2219 which is enabled by OR gate 2218, is transferred via OR gate 2220 to the memory system's memory address register 2210.
Again, when the memory system 2213 detects that its memory address register 2210 has been loaded with a new address and that the read/write flip-flop 2212 is at a logical zero vale, a memory read operation is initiated. Operation of a memory system is as described in the patent application entitled Segmented Address Development. As the result of a memory read operation, memory access exceptions 2214 may occur as described in the patent application Segmented Address Development. If such exceptions occur, the memory access exception flip-flop 2214 will be set to a logical one state. The exception handler, as described in the patent application entitled Exception Handling, will be activated. Otherwise, the memory operation completes normally and the memory operation complete flip-flop 2215 will be set to a logical one value (the memory operation complete flip-flop 2215 is reset to a logical zero value upon the initiation of any new memory operation). At the completion of the memory operation, the data read from the memory system, which represents a database pointer (eee FIGS. 15E, 15F, 15G and 15H), is transferred to the memory data register 2216. In FIG. 22D it can be seen that AND gate 2483, to which the output of the cycle 6 flip-flop is coupled, is enabled by the memory operation complete signal from the memory operation complete flip-flop 2215. Thus, at cycle 6 after the memory operation is completed, AND gate 2483 which is coupled to the set input of the cycle 7 flip-flop 2407 initiates cycle 7.
Looking back at FIG. 22C, it can be seen that the P register 2226 is coupled to a series of AND gates and 4 flip-flops entitled AS 2241, BS 2240, CS 2239 and DS 2238. The purpose of this particular logic is to detect and store in flip-flops A 2245, B 2244, C 2243, and D 2242, the pointer mode of the record being dealt with (specifically whether the pointers are of type 0, 1, 2 or 3 which will be respectively the flip-flops A, B, C and D). To accomplish the decoding of the pointer mode, bit No. 0 (left most bit) of the P register 2226 is coupled to inverting AND gate 2232. The bit No. 1 (right most bit) of the P register 2226 is also coupled to an inverting AND gate 2233. AND gates 2234 through 2237 serve to decode the 2 bits of the P register 2226. AND gate 2237 has as its input the two inverted bit values of the P register from inverting AND gates 2232 and 2233. Thus, AND gate 2237 is raised to a logical one value if the value in the P register is a 0 (binary 00). In this case the cycle 7 signal would enable AND gate 2237 to set the AS flip-flop 2241. It can be noted on FIG. 22D that the AS flip-flop 2241 is used to initiate the A cycle sequence, cycle A0 2411 through cycle A5 2416. The AS flip-flop 2241 also has its output coupled to the A flip-flop 2245. The A flip-flop 2245 stores the fact that the P register 2226 has a value of 0 (i.e., virtual memory record, pointer mode type 0). The AS flip-flop 2241 also has its output coupled to its reset input. Thus, after setting the A flip-flop 2245 and initiating the A cycle sequence, the AS flip-flop is reset to a 0 value.
AND gate 2236 has the inverted P bit No. 0 and the non-inverted P bit No. 1 coupled to it. Thus, in cycle 7, which enables AND gate 2236, the BS flip-flop 2240 is set to a logical one value if the value in the P register is -1 (binary 01). Analagous to the pointer mode type 0 case, the BS flip-flop 2240 sets the B flip-flop 2214 and initiates the B cycle sequence. The BS flip-flop 2240 resets itself after accomplishing these operations.
AND gate 2235 has the non-inverted P bit No. 0 from P register 2226 and the inverted P bit No. 1 coupled to it. Thus, in cycle 7, AND gate 2235, which is enabled by the cycle 7 signal, sets the CS flip-flop 2239 if the value in the P register is 2 (binary 10). Thus, analagous to the previous cases, the CS flip-flop 2239 would set the C flip-flop 2243 (which stores the fact that a database record, pointer type 2 mode record) is being operated on. The CS flip-flop 2239 also initiates the C cycle sequence. The CS flip-flop 2239 also resets itself after setting the C flip-flop 2243 and initiating the C cycle sequence.
AND gate 2234 has coupled to it the non-inverted P bit No. 0 and P bit No. 1. Hence, in cycle 7, which enables AND gate 2234, the DS flip-flop 2238 would be set to a logical one value if the P register 2226 contains a value of 3 (binary 11), indicating a database record, pointer mode type 3 record. After being set to a logical one value, the DS flip-flop 2238 initiates the D cycle sequence and also sets the D flip-flop 2242 to store the fact that a database record, pointer type 3 is being dealt with. The DS flip-flop 2238 also has its output coupled to its reset input thus resetting itself after accomplishing the above operations.
Looking at FIG. 22D, it can be noted that in the B cycle has fewer cycle periods than the A cycle and that in several instances the output of a B cycle flip-flop is coupled with the output of an A cycle flip-flop to an OR gate to set another cycle flip-flop. This is because of the commonality in the A cycle (pointer type 0) and B cycle (pointer type 1) operations. In those cases where the pointer type 0 and pointer type 1 instruction operations require the same control sequence, the cycle A signal is set by either the preceding A cycle signal or the preceding B cycle signal. An example of this is shown where the cycle A1 flip-flop 2412 and the cycle B1 flip-flop 2422 are both coupled to OR gate 2484 which sets the cycle A2 flip-flop 2413. After a sequence of common A and B cycle actions, at which time the pointer mode type 0 and pointer mode type 1 conditions require different actions, separate cycle A or cycle B flip-flops will again be set. An example of this is following cycle A3 2414 where the output of the A3 flip-flop 2414 is coupled to AND gate 2486, which is enabled by the A signal from flip-flop 2245 (pointer mode type 0 indicator) to set the cycle A4 flip-flop 2415. The output of the cycle A3 flip-flop 2414 is also coupled to AND gate 2487, which is enabled by the B signal from flip-flop 2244 (pointer mode type 1 indicator) to set the cycle flip-flop 2423.
FIG. 22D also shows that the C cycle sequence (pointer mode type 2) and D cycle sequence (pointer mode type 3) share many cycle sequences together again because of the commonality in the C cycle and D cycle operations. The mechanism of indicating when separate C cycle and D cycle operations are required is the same as is employed with the cycle A and cycle B signals. Note that since pointer mode type 2 and pointer mode type 3 start out with common operations, the CS flip-flop 2239 and the DS flip-flop 2238 are both coupled to an OR gate 2489, which is in turn coupled to the set input of the cycle CO flip-flop 2431. Cycle CO is thus the initial cycle for both and C and D cycle sequences.
Now returning to the logic operations in FIG. 22A through 22C, it was described supra how following cycle 7, the A, B, C, or D cycle sequences would be initiated. Looking first at the operation of the A and B cycle sequences, it can be noted that the SRA field of the pointer in the memory data register 2216 (1542 for a class 0 pointer or field 1552 for a class 1 pointer) is coupled to AND gate 2248 in FIG. 22A. The cycle AO signal and the cycle BO signal are coupled to OR gate 2247, which in turn enables AND gate 2248. Thus, in either cycle AO or cycle BO, AND gate 2248 is enabled to transfer the SRA portion of the pointer read from memory to the SRA register 2249. It can also be noted that the SEG field 1552 of the pointer (this field is meaningful only if a class 1 pointer is being operated on) is coupled from the memory date register 2216 to AND gate 2250. AND gate 2250 is enabled by the cycle BO signal, thus transferring the SEG field 1552 to the SEG register 2316 in cycle BO.
In cycle B1 the SRA register 2249 which is coupled to AND gate 2253, which is enabled by the cycle B1 signal, transfers the SRA register's contents via OR gate 2255 into the offset field of the EAX register 2257 (the format of this register is the same as shown for a base register in FIG. 2, 202). The cycle B1 signal also enables AND gate 2254, to which the SEG register 2316 is coupled, to transfer that register via OR gate 2256 into the SEG portion of the EAX register 2257 (the SEG portion of the EAX register is the STN, STE field shown in FIG. 2, 202).
If the pointer mode being operated on is a type O pointer, the cycle A1 signal enables the transfer of the SRA register 2249 via AND gate 2252 through OR gate 2255 into the offset portion of the EAX register 2257. The SEG (or equivalents, STN, STE) of the base register output register 2230, which was previously loaded as described above, is coupled to AND gate 2251, which is enabled by cycle A1. Thus, in cycle A1 the base register's segment number is transferred via OR gate 2256, to which AND gate 2251 is coupled, into the SEG portion of the EAX register 2257.
After the EAX register 2257 has been loaded, the contents of this register, which comprise a segmented address of the format shown in FIG. 2, 202, are transferred via OR gate 2217 into the address control unit 2207 shown in FIG. 22B. Again, the address control unit 2207, when supplied with a segmented address (of the format show in FIG. 2, 202), translates that address into a memory address as described in the Segmented Address Development patent. Thus, the output of the address control unit 2207 is again transferred to the memory address register 2209. Since another one of the inputs to OR gate 2218, which enables AND gate 2219, is the cycle A2 signal (which follows either cycle A1 or cycle B1), the address in the address control unit's address register 2209 is then transferred via AND gate 2219 through OR gate 2220 into the memory address register 2210 of the memory system 2213.
Again, when the memory system 2213 detects that its memory address register 2210 has been loaded with a new address and that the read/write flip-flop 2212 is at a logical zero value, another memory read operation is initiated. As the result of a memory read operation, memory access exceptions 2214 may occur. If such exceptions occur, the memory access exception flip-flop 2214 will be set to a logical one state and the exception handler mechanism activated. Otherwise, the memory operation completes normally and the memory operation complete flip-flop 2215 will be set to a logical one value. At the completion of the memory operation, the data read from the memory system, which represents the portion of a virtual memory record containing the D field (or "D-switch") 1502 as shown in FIG. 15A, is transferred to the memory data register 2216.
Looking at FIG. 22D, it can be seen that the output of the cycle A2 flip-flop 2413 is coupled to AND gate 2485, which is enabled by the memory operation complete signal. Thus, following the completion of the memory operation, AND gate 2485 is enabled to set the cycle A3 flip-flop 2414.
In cycle A3, AND gate 2258, which is enabled by the cycle A3 signal, transfers the D field 1502 of the virtual memory record from the memory data register 2216 into one of the two inputs of comparator 2260. The other input to comparator 2260 is a set of 0 bits 2259. If comparator 2260 finds the D field 1502 equal to 0, the equal signal of comparator 2260 is raised to a logical one, thus setting the record deleted exception flip-flop 2261 to a logical one vale. The exception handler mechanism is then activated and the instruction is complete. Otherwise, the not equal signal of comparator 2260 is raised to a logical one value. It can be noted on FIG. 22D that the not equal signal of comparator 2260 is coupled to AND gate 2486 and 2487. Thus, under the not equal condition either AND gate 2486 is enabled if the A signal 2245 indicates a pointer type 0 operation or else AND gate 2487 is enabled if the B signal 2244 indicates a pointer type 1 operation. AND gate 2486, if enabled by the A signal and the not equal signal, sets the cycle A4 flip-flop 2415 following cycle A3. AND gate 2487, if enabled by the B signal and the not equal signal from comparator 2260, sets the cycle B4 flip-flop 2423 following cycle A3.
Since OR gate 2263 on FIG. 22B has as its inputs the cycle A4 signal and the cycle B4 signal, in either of these cycles AND gate 2313 is enabled to transfer the SRA register 2249 through OR gate 2264 to which AND gate 2313 is coupled into the offset field of the BR base register input register 2267 (the BR input register 2267 is of the format as shown in FIG. 2, 202). If a record of pointer mode type 1 is being operated on, the cycle B4 signal enables AND gate 2265 to transfer the SEG register 2316 via OR gate 2266 into the SEG portion of the BR input register 2267 (SEG is equivalent to the STN, STE field as shown in FIG. 2, 202).
Since the cycle A4 and cycle B4 signals are input to OR gate 2270, which enables AND gate 2271, in either of these cycles AND gate 2270 is enabled to transfer the BR field 1926 of the instruction buffer 2202 to the BR section 2208 of the address control unit 2207. When the address control unit 2207 is supplied with a BR register number in its BR section 2208 and the BR input register 2267 is loaded with a new value, the address control unit writes the value in the BR input register 2267 into that base register by means of a normal scratchpad memory type write operation. Thus, the base register whose base register BR number is given in the instruction field 1926 has now been updated with a segmented address value which is the address of the owner record of the record originally pointed to by the contents of that same base register BR.
Looking at FIG. 22D again, it can be seen that the cycle A4 flip-flop 2415 and the cycle B4 flip-flop 2423 both have their outputs coupled to the OR gate 2488, OR gate 2488 thus sets the cycle A5 flip-flop 2416 following either cycle A4 or cycle B4. The cycle A4 signal, which is input to OR gate 2272, is used to set the instruction complete flip-flop 2246 as can be seen in FIG. 22C. Setting the instruction complete flip-flop 2246, as well as notifying the central processor of the completion of the instruction, also resets the series of flip-flops A 2245, B 2244, C 2243 and D 2242, since each of these flip-flops reset input has the instruction complete signal coupled to it as can be seen in FIG. 22C. Note that only one of these four flip-flops would have actually been set to a logical one value since the P value would have caused the original setting of only one of the flip-flops.
Looking in more detail at the C and D cycle sequences for the cases of pointer mode types 2 and 3 records, as previously noted the C and D cycle sequences both begin with the cycle CO signal from flip-flop 2431 on FIG. 22D, flip-flop 2431 being set via OR gate 2489 which has coupled to it the CS flip-flop 2239 and the BS flip-flop 2238. In the cycle CO, referring back to FIG. 22A the 1 bit 2317 coupled to AND gate 2274, which is enabled by the cycle CO signal, is transferred to the left most bit of the scratchpad memory address register 2275. The BR field 1926 of the instruction buffer 2202 is coupled to AND gate 2273, which is enabled by the cycle CO signal to transfer the BR number from the instruction buffer 2202 to the right most 3 bits of the scratchpad memory address register 2275. Hence, in cycle CO the address of an index register which corresponds to a base register BR in the manner previously described, is loaded into the scratchpad memory address register 2275. It can be noted that the scratchpad memory read/write flip-flop 2277 was previously set to a 0 value when the find owner instruction detector 2201 was raised to a logical one, thus lowering to a logical zero the output of inverting AND gate 2211 which is coupled to OR gate 2278. The output of OR gate 2278 which is in turn coupled to the scratchpad memory read/write flip-flop 2277 thus would have been initially set to a 0 value. The scratchpad memory 2276 initiates a scratchpad memory read operation of the address contained in the scratchpad memory address register 2275 upon detecting that the scratchpad memory address register 2275 has been loaded with an address and that the scratchpad memory read/write flip-flop 2277 is set to a logical zero value. Thus, the scratchpad memory would read out the index register corresponding to the BR base register number contained in the instruction buffer 2202 following the loading of the scratchpad memory address register 2275 in cycle CO. At the completion of the scratchpad memory operation, the index register read out from the memory is transferred to the scratchpad memory data register 2318.
In cycle C1, which occurs only if the pointer mode is type 2 as can be seen in FIG. 22D, flip-flop 2432, the area field 1572 (as shown in FIG. 15H) of the index register is loaded into the area portion of the area page-line number register 2281. This transfer is accomplished via AND gate 2319, which is enabled by the cycle C1 signal. Also in cycle C1, the page-line number portion of the pointer contained in the memory data register 2216 which was previously read out from the memory system 2213 is loaded in the page-line number portion of the area-page-line number register 2281. This transfer is accomplished via AND gate 2279, which is enabled by the cycle C1 signal.
In cycle D1, which corresponds to the pointer mode type 3 operation only as can be seen in FIG. 22D, flip-flop 2451, the complete area-page-line number as shown in FIG. 15H is transferred from the memory data register 2216, where the pointer was previously loaded after a memory read operation, into the entire area-page-line number register 2281. This transfer is accomplished via AND gate 2280, which is enabled by the cycle D1 signal.
Looking at FIG. 22D, it can be seen that following either the cycle C1 signal or the cycle D1 signal, the cycle C2 follows. This is accomplished by coupling the output of the cycle C1 flip-flop 2432 and the cycle D1 flip-flop 2451 to OR gate 2492, which is in turn coupled to the set input of the cycle C2 flip-flop 2433.
In cycle C2, AND gate 2282 is enabled allowing the transfer of the area-page-line register 2281 into the locate page mechanism 2284. The operation of the locate page mechanism has been described supra and a hardware implementation for that mechanism is shown in FIG. 18. Activation of the locate page mechanism involves the setting of the activate locate page flip-flop 2283, as is accomplished by the cycle C2 signal, and the loading of the area-page register 2285, into which the area-page portion of the area-page-line number register 2281 are transferred via AND gate 2282, which is enabled by the cycle C2 signal. The activate locate page flip-flop 2283 corresponds to flip-flop 1851 as shown in FIG. 18. The area-page register 2285 corresponds to register 1852 in FIG. 18. As described supra, execution of the locate page mechanism 2284 may result in paging exceptions, in which case the paging exception flip-flop 2286 will be set and the exception handler mechanism will be activated. The paging exception flip-flop 2286 corresponds to flip-flop 1884 in FIG. 18. If a paging exception does not occur, the page descriptor corresponding to the page number given in the area-page register 2285 will be loaded in the page descriptor register 2289 (which corresponds to register 1877 in FIG. 18) and the locate page complete flip-flop 2287 will be set (which corresponds to flip-flop 1879 in FIG. 18). The format of a page descriptor as loaded in the page descriptor register 2289 is shown in FIG. 16B and has been described previously.
Note on FIG. 22D that the locate page complete flip-flop 2287 being set to a value of 1 along with cycle C2 flip-flop 2433 being at a logical one enables AND gate 2493 which in turn initiates cycle C3 of the C cycle sequence.
The cycle C3 signal enables AND gate 291, which transfers the shift count field 1623 of the page descriptor into the shift count register 2292. This shift count will be used to take the area-page-line number from the area-page-line register 2281 and shift out the line number portion of that number and then load that line number into the W register 2296. Also in cycle C3 the segment number field 1625 of the page descriptor is transferred via AND gate 2290, which is enabled by the cycle C3 signal, into the address control unit 2207. As described in the patent application entitled Segmented Address Development, the address control unit 2207, when supplied with a segment number, outputs the base address of that segment into the address register 2209 of the address control unit 2207. Looking at FIG. 22B, it can be seen that in cycle C4, the segment base address outputted from the address control unit 2207 is transferred via AND gate 2231, which is enabled by the cycle C4 signal, into the segment base address register 2322.
The segment base address register 2322 is coupled as one input to the adder 2325. The other input to adder 2325 is the register 2323, containing a value of 8. This value of 8 corresponds to the displacement from the beginning of the segment base of the maximum line number field as found in the page header 1603, as shown in FIG. 16A. The maximum line number field contains the value which is the highest allowed line number to be used when referencing the particular page whose number is given in the area-page register 2285. In cycle C5, the output of adder 2325 representing the address of the maximum line number field is transferred via AND gate 2324 through OR gate 2220, to which AND gate 2324 is coupled, into the memory address register 2210 of the memory system 2213. The memory system 2213, upon detecting that its memory address register 2210 has been loaded with a new value and that the read/write flip-flop 2212 is set to a logical zero value, initiates a memory read operation. As the result of the memory operation, memory access exceptions 2214 may occur as described in the patent application entitled Segmented Address Development. Such memory access exceptions cause the setting of the memory access exception flip-flop 2214 and the activation of the exception handler mechanism. Otherwise, the memory operation completes normally and the memory operation complete flip-flop 2215 will be set to a logical 1 value. Note in FIG. 22D that the transition of the memory operation complete signal to a logical one value along with the cycle C5 signal from flip-flop 2436 being a logical one enables AND gate 2294 to set the cycle C6 flip-flop 2437 to a logical one since AND gate 2494 is coupled to the set input of the cycle C6 flip-flop 2437. The transition of the memory operation complete flip-flop 2215 to a logical one indicates that the addressed maximum line number field has been transferred from the memory system 2213 to the memory data register 2216. In cycle C6, AND gate 2300 is enabled to transfer the maximum line number field from the memory data register 2216 into the Z register 2301.
Looking back at other actions caused by the cycle C4, it can be seen in FIG. 22A that the area-page-line register 2281 is input to the shifter 2294 via AND gate 2293, which is enabled by the cycle C4 signal. The value previously stored in the shift count register 2294 is also input to the shifter count field input of the shifter 2294 via AND gate 2320, which is enabled by the cycle C4 signal. Looking at FIG. 22B, the output of shifter 2294 is coupled to AND gate 2295, which is enabled by the cycle C5 signal. Thus, in cycle C5 the output of the shifter, representing a line number obtained from the area-page-line register 2281, is transferred via AND gate 2295 into the W register 2296.
The Z register 2301 is one input to comparator 2297. The other input to comparator 2297 is the W register 2296. If comparator 2297 finds the value in the W register greater than or equal to the value in the Z register, the W greater than or equal to Z signal, which is coupled to AND gate 2298, along with the cycle C7 signal enables the setting of the invalid page format exception flip-flop 2299. If the invalid page format exception flip-flop 2299 is set to a 1 value, the exception handler mechanism will be activated and the instruction will be complete. If comparator 2297 finds the W value less than the Z value, the W less than Z signal is coupled to AND gate 2332 and will be used to enable that gate.
The W register 2296 is coupled to multiplier 2328 as one input to that multiplier. That other input to multiplier 2328 is register 2327 which contains the value of 2. The multiplier 2328 is a typical hardware logic implemented multiplier. Thus, the line number W is multiplied by a value of 2, which in this case represents two 8-bit bytes of the memory system 2213. Two bytes constitutes the length of a line offset array item such as 1604-1603 in the line offset array 1602 of FIG. 16A. The multiplying of the W line number by the size of the line offset array item thus indexes into an address location the proper line offset array item for line W. The output of multiplier 2328 is coupled to AND gate 2329, which is enabled by the cycle C6 signal. AND gate 2329 is in turn coupled to one of the adder inputs of adder 2330. The other input to adder 2330 is a value of 10, as stored in register 2331. The value of 10 represents the offset address in 8-bit bytes of the beginning of the line offset array 1602, as shown in FIG. 16A. Thus, the output of adder 2330 addresses the relative location of the line number W's line offset array item in the data base page as shown in FIG. 16A and previously described. The output of adder 2330 is coupled to AND gate 2332, which is enabled by the cycle C7A signal and the W less than Z signal from comparator 2297, which would be at a logical one if the line number W was found to be less than the maximum line number Z from register Z 2301.
The output of AND gate 2332, representing the segment relative offset address of line number W's line offset array item, is coupled as one input to adder 2333. The other input to adder 2333 is the segment base address register 2322. Thus, the output of adder 2333 represents the absolute address of the desired line offset array item of line number W. The output of adder 2333 is coupled to AND gate 2334, which is enabled by the cycle C7 signal. The output of AND gate 2334 is transferred via OR gate 2220 into the memory address register 2210. When the memory system has detected that the memory address register 2210 has again been loaded and that the read/write flip-flop 2212 is set at a logical zero value, a memory read operation is again initiated. If memory access exceptions occur as a result of the memory read operation, the memory access exception flip-flop 2214 will be set to a logical one value and the exception handler mechanism will be activated. Otherwise, the memory operation completes normally and the memory operation complete flip-flop 2215 will be set to a logical one. It can be seen in FIG. 22D that cycle C7 and the raising of the memory operation complete signal enable AND gate 2495, which is coupled to the set input of cycle C8 flip-flop 2440, thus initiating cycle C8. The raising of the memory operation complete signal also indicates that the desired line offset array item has been transferred to the memory data register 2216.
Cycle C8 enables the transfer of the D field (or "D-switch"), as shown in FIG. 16A field 1604, of the line offset array item, via AND gate 2302 into comparator 2303 as can be seen in FIG. 22C. The other input to comparator 2303 is register 2304, which contains the value of 0. If comparator 2303 finds the D-switch of the line offset array item of the line number W equal to a value of 0, the equal signal of comparator 2303 will set the line not in use exception flip-flop 2305 to which the equal signal of comparator 2303 is coupled. Setting of flip-flop 2305 will activate the exception handler mechanism and the instruction will be complete. Otherwise, the not equal signal of comparator 2303 will be raised to a logical one value.
The output of AND gate 2302 containing the D-switch of the line offset array item of the line number W is also coupled to comparator 2306. The other input to comparator 2306 is register 2308, which contains a value of 2. If comparator 2306 finds the D-switch not equal to a value of 2, the not equal signal of comparator 2306 is raised to a logical one. It can be seen that the not equal signal of comparator 2303 and the not equal signal of comparator 2306 are coupled to AND gate 2309. If the D-switch is not equal to a value of 0 or 2, then it must be equal to a value of 1 or 3, either of which constitute a line deleted exception. Thus, the two not equal signals of comparators 2303 and 2306 are coupled to AND gate 2309, which is enabled during cycle C9, to set the line deleted exception flip-flop 2310 if the D-switch is equal to a value of 1 or 3. If the line deleted exception flip-flop 2310 is set to a logical one value, the exception handler mechanism is activated and the instruction is complete. If comparator 2306 finds the D-switch of the line offset array item of the line number W equal to a value of 2, neither the line deleted exception flip-flop 2310 nor the line not in use exception flip-flop 2305 will be set to a logical one value and hence instruction execution will continue.
The cycle C10 signal is used to transfer the line offset portion of the line offset array item (see field 1603 of FIG. 16A) corresponding to line W via AND gate 2312, which is enabled by cycle C10, into the base register BR input register 2267 via OR gate 2264 as can be seen in FIG. 22B. The line offset of the line offset array item is transferred into the SRA portion of the BR input register 2267, as shown in FIG. 2, 202. The cycle C10 signal is also used to enable AND gate 2311 to transfer the segment number field 1625 from the page descriptor register 2289 via AND gate 2311 through OR gate 2266 into the BR input register 2267. The segment number 1625 is transferred into the STN, STE portion of the base register input register as shown in FIG. 2, 202.
Since the cycle C10 signal is another input to OR gate 2270 which enables AND gate 2271, in cycle C10 the BR field 1926 of the instruction buffer 2202 is input to the BR section 2208 of the address control unit 2207. When the address control unit 2207 is supplied with a BR register number in its BR section 2208 and the BR input register 2267 is loaded with a new value, the address control unit writes the value contained in the BR input register 2267 into that base register whose number is input by means of a normal scratchpad memory type write operation. Thus, the base register whose base register number is given in the instruction field 1926 has now been updated with a segmented address value which is the address of the owner record pointed by the contents of the index register corresponding to that base register BR.
In FIG. 22D, it can be seen that following cycle C10 flip-flop 2442, either the cycle C11 flip-flop 2443 or the cycle D11 flip-flop 2252 is set according to whether the record pointer mode is type 2 or type 3, as indicated by either the C flip-flop 2243 being set to a logical one or the D flip-flop 2242 being set to a logical one value, respectively. The setting of the cycle C11 flip-flop 2443 is accomplished via AND gate 2496 and the setting of the cycle D11 flip-flop 2452 is accomplished via AND gate 2497.
In cycle C11, the page-line-number portion of the area-page-line register 2281 is transferred via AND gate 2315, which is enabled by the cycle C11 signal, into the page-line portion (field 1573 and field 1574 of FIG. 15H) of the scratchpad memory data register 2318 as can be seen in FIG. 22A. If the pointer mode is type 3, then in cycle D11, the entire area-page-line register 2281 is transferred via AND gate 2314, which is enabled by the cycle D11 signal, into the entire scratchpad memory data register 2318.
In either cycle C11 or cycle D11, since both of these signals are inputs to OR gate 2278 which is coupled to the scratchpad memory read/write flip-flop 2277, the scratchpad memory read/write flip-flop 2277 will be set to a logical one value, indicating that a scratchpad memory write operation is to be initiated. The address contained in the scratchpad memory address register 2275 is at this point still the address of the index register corresponding to the BR base register number 1926 in the instruction buffer 2202. The scratchpad memory 2276 writes a new area-page-line number into this index register after the cycle C11 or D11 signal has caused the scratchpad memory data register 2318 to be loaded and the scratchpad memory read/write flip-flop 2277 to be raised to a logical one value. The new area-page-line number is the address of the owner record of the number record referenced by the base register BR of the instruction.
Looking at FIG. 22D, it can be seen that the cycle C11 flip-flop 2243 and the cycle D11 flip-flop 2452 both have their outputs coupled to OR gate 2498, which in turn has its output coupled to the set input of cycle C12 flip-flop 2444. Thus, cycle C12 follows either cycle C11 or cycle D11.
It can also be noted in FIG. 22C that the cycle C12 signal is coupled to the set input of the instruction complete flip-flop to a logical one, indicating the termination of the find owner database instruction.
FIG. 22D shows the detailed logic for the cycle counter control logic of the find owner instruction hardware implementation shown in FIGS. 22A through 22C. Cycle C1 through cycle C7, flip-flops 2401 through 2407, constitute the beginning cycle sequence of the control logic. Cycle A0 through cycle A5, flip-flops 2411 through 2416, constitute the A cycle sequence, which implements the portion of hardware operation specific to a pointer mode type O, virtual memory record. Cycle B0 through cycle B4, flip-flops 2421 through 2423, constitute the B cycle sequence, which implements the portion of the hardware operation specific to a pointer mode type 1, cirtual memory record. In certain instances, A cycle sequences are used to implement operations for cycle B (type 1 pointer mode) because the commonality between type 0 and type 1 operations. Cycle C0 through cycle C12, flip-flops 2431 through 2444, constitute the C cycle sequence, which implements the hardware operation specific to a pointer mode type 2, data base record. Cycle D1 through cycle D11, flip-flops 2451 through 2452, constitute the D cycle sequence, which implements the hardware operation specific to a pointer mode type 3, data base record. In several instances, C cycles are shared by D cycles because of the commonality between operations for type 2 and type 3 records.
Each flip-flop in FIG. 22D is a synchronous flip-flop. Thus, a clocking system, as described in reference 17 of Appendix I, is used to trigger the logical state changes in each of these flip-flops. The clocking signal would have a clock signal connected to the clock input of each of these flip-flops. Each of the flip-flops in this control counter logic also has its output signal connected to its reset input. Hence, a cycle flip-flop being set to a one value results in the flip-flop being reset to a zero value one clock period later. In the case where the next sequential clock cycle is dependent on a logic condition other than just the previous clock cycle signal being a logical one, e.g., the memory operation complete signal being raised a logical one, the output of the AND gate doing the logic detection of the appropriate conditions - not the direct output signal - is coupled to the previous clock cycle's reset input.
The equal signal from comparator 2203, FIG. 22A, is coupled to the set input of the cycle 1 flip-flop 2401. Therefore, after the MBZ field 1923 of the find owner instruction has been verified to be a value of zero, cycle 1 is initiated. The cycle 1 flip-flop 2401 has its output coupled to the set input of the cycle 2 flip-flop 2402. The output of the cycle 2 flip-flop 2402 is coupled to AND gate 2481. AND gate 2481 is enabled by the memory operation complete flip-flop signal from the memory operation complete flip-flop 2215 shown in FIG. 22B. Thus, the output of AND gate 2481 is raised to a logical one value after the memory operation has completed, at which time the find owner instruction is ready to progress to the next step of its execution. The output of AND gate 2481 is coupled to the set input of the cycle 3 flip-flop 2403.
The output of the cycle 3 flip-flop 2403 is coupled to AND gate 2482. AND gate 2482 is enabled by the equal signal from comparator 2222, FIG. 22C. Thus, the output of AND gate 2482 is raised to a logical one value if the comparator 2222 finds the K field 1805 of the set descriptor addressed by the find owner instruction to be equal to a value of 0. The output of AND gate 2484 is coupled to set input of the cycle 4 flip-flop 2404.
The output of the cycle 4 flip-flop 2404 is coupled to the set input of the cycle 5 flip-flop 2405. The output of the cycle 5 flip-flop 2405 is coupled to the set input of the cycle 6 flip-flop 2406.
The output of the cycle 6 flip-flop 2406 is coupled to AND gate 2483. AND gate 2483 is enabled by the memory operation complete signal from the memory operation complete flip-flop 2215. The output of AND gate 2483 is coupled to the set input of the cycle 7 flip-flop 2407.
As was described previously, following cycle 7, one of the following flip-flops will be set: AS 2241, BS 2240, CS 2239, or DS 2238 (see FIG. 22C). These signals will initiate respectively the A cycle sequence, the B cycle sequence, the C cycle sequence, or the D cycle sequence.
The cycle A0 flip-flop 2411 is set by the AS flip-flop 2241. The output of the cycle A0 flip-flop 2411 is coupled to the set input of the cycle A1 flip-flop 2412. The cycle B0 flip-flop 2421 is set by the BS flip-flop 2240. The output of the cycle B0 flip-flop 2421 is coupled to the set input of the cycle B1 flip-flop 2422. The output of both the cycle A1 flip-flop 2412 and the cycle B1 flip-flop 2422 are coupled to OR gate 2484. The output of OR gate 2484 is in turn coupled to the set input of the cycle A2 flip-flop 2413. Thus, cycle A2 follows either cycle A1 or cycle B1.
The output the cycle A2 flip-flop 2413 is coupled to AND gate 2485. AND gate 2485 is enabled by the memory operation complete signal. The output of AND gate 2485 is coupled to the set input of the cycle A3 flip-flop 2414.
The output of the cycle A3 flip-flop 2414 is coupled both to AND gates 2486 and 2487. These two AND gates are used to select continuation of either an A cycle or a B cycle, depending on whether the pointer mode is type 0 or type 1. Both AND gates 2486 and 2487 also have as an additional enabling input the not equal signal from comparator 2260 of FIG. 22C. This signal is used to indicate that the virtual memory record has a D-switch not equal to a 0 (record deleted) value. The final enabling input to AND gate 2486 is the A signal from flip-flop 2245. Thus, if the pointer mode is type 0 and henceforth the A signal 2245 is a logical one value, AND gate 2486 is raised a logical one value and the cycle A4 flip-flop 2415 to whose set input AND gate 2486 is coupled is set to a logical one. If the pointer mode is of type 1 and thus the B signal of flip-flop 2244 is a logical one, the AND gate 2487 is raised to a logical one value and since AND gate 2487 is coupled to the set input of the cycle B4 flip-flop 2423, the cycle B4 is initiated.
The outputs of both the cycle A4 flip-flop 2415 and the cycle B4 flip-flop 2324 are coupled to OR gate 2488. Thus, OR gate 2488 has its output raised to a logical one value following either cycle A4 or cycle B4. The output of OR gate 2488 is coupled to the set input of the cycle A5 flip-flop 2416. Following cycle A5, the instruction complete flip-flop 2246 will be set.
Both flip-flop CS 2239 and flip-flop DS 2238 have their outputs coupled to OR gate 2489. OR gate 2489 is coupled to the set input of the cycle C0 flip-flop 2431.
The output of the cycle C0 flip-flop 2431 is coupled to both AND gates 2490 and 2491. These two AND gates are used to select continuation of either the C cycle sequence or D cycle sequence depending on whether the pointer mode is type 2 or type 3. Thus, the second enabling input to AND gate 2490 is the C signal from flip-flop 2243 (see FIG. 22C). If the pointer mode is type 2 and henceforth the C signal 2243 is a logical one value, AND gate 2490 is raised to a logical one value and the cycle C1 flip-flop 2432 to whose set input AND gate 2490 is coupled, is set to a logical one. If the pointer mode is of type 3 and thus the D signal of flip-flop 2242 is a logical one, the AND gate 2491 is raised to a logical one value and, since AND gate 2491 is coupled to the set input of the cycle D1 flip-flop 2451, the cycle D1 is initiated.
The outputs of both the cycle C1 flip-flop 2432 and the cycle D1 flip-flop 2451 are coupled to OR gate 2492. Thus, OR gate 2492 has its output raised to a logical one value following either cycle C1 or cycle D1. The output of OR gate 2492 is coupled to the set input of the cycle C2 flip-flop 2433.
The output of the cycle C2 flip-flop 2433 is coupled to AND gate 2493. AND gate 2493 is enabled by the locate page complete signal from the locate page complete flip-flop 2287 shown in FIG. 22B. The output of AND gate 2493 is coupled to the set input of the cycle C3 flip-flop 2434. The output of the cycle C3 flip-flop 2434 is coupled to the set input of the cycle C4 flip-flop 2434. The output of the cycle C4 flip-flop 2435 is coupled to the set input of the cycle C5 flip-flop 2436.
The output of the cycle C5 flip-flop 2436 is coupled to AND gate 2494. AND gate 2494 is enabled by the memory operation complete signal from the memory operation complete flip-flop 2215. The output of AND gate 2494 is coupled to the set input of the cycle C6 flip-flop 2437.
The output of the cycle C6 flip-flop 2437 is coupled to the set input of the cycle C7A flip-flop 2438. The output of the cycle C7A flip-flop 2438 is coupled to the set input of the cycle C7 flip-flop 2439.
The output of the cycle C7 flip-flop 2439 is coupled to AND gate 2495. AND gate 2495 is enabled by the memory operation complete signal. The output of AND gate 2494 is coupled to the set input of the cycle C8 flip-flop 2440.
The output of the cycle C8 flip-flop 2440 is coupled to the set input of the cycle C9 flip-flop 2441. The output of the cycle C9 flip-flop 2441 is coupled to the set input of the cycle C10 flip-flop 2442.
The output of the cycle C10 flip-flop 2442 is coupled to both AND gates 2496 and 2497. These two AND gates are used to select continuation of either a C cycle or a D cycle, again depending on whether the pointer mode is type 2 or type 3. The second enabling input to AND gate 2496 is the C signal from flip-flop 2243. Thus, if the pointer mode is of type 2 and henceforth the C signal from flip-flop 2243 is a logical one value, AND gate 2496 is raised to a logical one value and the cycle C11 flip-flop 2443, to whose set input AND gate 2496 is coupled, is set to a logical one. If the pointer mode is of type 3 and thus the D signal of flip-flop 2242 is a logical one, the AND gate 2497 is raised to a logical one value and, since AND gate 2497 is coupled to the set input of the cycle D11 flip-flop 2452, the cycle D11 is initiated.
The outputs of both the cycle C11 flip-flop 2443 and the cycle D11 flip-flop 2452 are coupled to OR gate 2498. Thus, OR gate 2498 has its output raised to a logical one value following either cycle C11 or cycle D11. The output of OR gate 2498 is coupled to the set input of the cycle C12 flip-flop 2444. Following the cycle C12, the instruction complete flip-flop 2246 will be set as is shown in FIG. 22C.
Having shown and described one embodiment of the invention, those skilled in the art will realize that many variations and modifications can be made to produce the described invention and still be within the spirit and scope of the claimed invention. Thus, many of the steps may be altered or replaced by different steps which will provide the same result and fall within the spirit of the claimed invention. It is the invention therefore to be limited only as indicated by the scope of all of the claims.
APPENDIX I I
The following information is provided as background information to better understand the invention, although such information is not necessary to practice the invention.
FURTHER INFORMATION WITH RESPECT TO FIG. 1:
(1) Emulators (112)
(a) Emulators are found in the IBM System/370. See page 265 of a book entitled Computer Organization and the System/370, by Harry Katzan, Jr., in 1971 by VanNostrand Reinhold Company of New York, New York.
(b) Emulators are also described in the following U.S. Pat. Nos.
3,374,466 issued 3/19/68;
3,543,245 issued 11/24/70;
3,698,007 issued 10/10/72;
3,721,961 issued 3/20/73.
(2) COMPUTATION UNIT (111)
(a) Computational units are well known in the art and are also known as Arithmetic and Logic Unit (ALU). See the following U.S. Pat. Nos.:
3,400,371 issued 9/3/68;
3,404,378 issued 11/1/68;
3,238,508 issued 3/1/66;
3,201,762 issued 8/17/65.
(3) CONTROL UNIT (130)
(a) Typical control units are described in a book entitled, Microprogramming: Principles and Practices, by Samir S. Husson, published in 1970 by Prentice-Hall Inc., of Englewood Cliffs, New Jersey; see also a book entitled, Computer Organization and Microprogramming, by Yao-Yaohan Chu, published in 1972 by Prentice-Hall Inc., Englewood Cliffs, New Jersey. Typical state of the art control units are disclosed in the following U.S. Pat. Nos.:
3,400,371 issued 9/3/68;
3,370,274 issued 2/20/68;
3,380,025 issued 4/23/68;
3,268,872 issued 8/23/66;
3,302,183 issued 1/31/67;
3,391,394 issued 7/2/68;
3,302,183 issued 1/31/67;
3,477,063 issued 11/4/69;
3,391,394 issued 7/2/68;
3,646,522 issued 2/29/72.
(4) BUFFER STORE (110)
(a) See reference 1, page 2 of this application.
(b) See also pages 296-311 of the above referenced book on Computer Organization and Microprogramming, by Yao-Yaohan Chu.
(c) Typical buffer stores are also disclosed in the following U.S. Pat. Nos.:
3,411,142 issued 11/12/68;
3,609,665 issued 9/28/71;
3,508,220 issued 4/21/70.
(5) MAIN MEMORY SYNCHRONIZER (109)
(a) See reference 4, page 2, of this application.
(b) See also U.S. Pat. No.:
3,449,723 issued 6/10/69.
(b) ASSOCIATIVE MEMORY (132)
(a) Associative memories are well known in the prior art, see pages 273-284 of the above-referenced book on Computer Organization and Microprogramming, by Yao-Yaohan Chu; see also the following U.S. Pat. Nos.:
3,648,254 issued 3/7/72;
3,456,243 issued 7/15/69;
3,253,265 issued 5/24/66;
3,248,704 issued 4/26/66;
3,241,123 issued 3/15/66;
3,170,142 issued 2/16/65.
(7) ADDRESS CONTROL UNIT (ACU) 131
(a) See reference 6, page 2, of this application.
(8) INPUT/OUTPUT CONTROL UNIT (105)
(a) Typical I/O control units are disclosed in the following U.S. Pat. Nos.:
3,559,187 issued 1/26/61;
3,593,299 issued 7/13/71;
3,251,040 issued 5/10/66;
3,573,741 issued 4/6/71;
3,444,520 issued 5/13/69;
3,680,054 issued 7/25/72;
3,359,543 issued 12/19/67;
3,651,480 issued 3/21/72;
3,248,701 issued 4/26/66;
3,254,330 issued 5/31/66.
(9) PERIPHERAL CONTROL UNIT (106)
(a) See Chapter 10 of the above-referenced book on Computer Organization and Microprogramming, by Yao-Yaohan Chu.
(b) Typical peripheral control units including device adapters are further disclosed in the following U.S. Pat. Nos.:
3,742,457 issued 6/26/73;
3,753,236 issued 7/14/73;
3,408,632 issued 10/29/68;
3,614,740 issued 10/19/71.
(10) DEVICE ADAPTERS (107)
(a) See reference 9, of this page. See also the following U.S. Pat. Nos.:
3,573,741 issued 4/6/71;
3,680,054 issued 7/25/72.
(11) MAIN MEMORY (102)
(a) See references 2-7, inclusive on page 2, of this application.
BACKGROUND INFORMATION RELATIVE TO FIG. 13a
In addition to the references already cited in this Appendix, the following are also included:
(12) GENERAL REGISTERS (1307-1311)
(a) Registers are well known in the computer art. Typical ones are disclosed in the following U.S. Pat. Nos.:
3,117,307 issued 1/7/64;
3,108,193 issued 10/22/63;
3,383,521 issued 5/14/68;
3,289,010 issued 11/29/66;
3,258,696 issued 6/28/66.
(13) HARDWARE CONTROL MAST REGISTER (1313)
(a) See also U.S. Pat. Nos.:
3,351,915 issued 11/7/67;
3,602,898 issued 8/31/71.
(14) INSTRUCTION COUNTER (1312)
(a) Instruction counters are well known in the computer art. See for example U.S. Pat. No.:
3,162,841 issued 12/22/64.
(15) SCRATCH PAD MEMORY (1315)
(a) Typical Scratch Pad Memories are disclosed in the following U.S. Pat. Nos.:
3,248,709 issued 4/26/66;
3,351,909 issued 11/7/67.
(16) INSTRUCTION FETCH UNIT (1319)
(a) Instruction fetch units are well known in the computer art. See, for example, pages 339-347 of the above-referenced book on Microprogramming: Principles and Practices, by Samir S. Husson.
(b) Typical instruction fetch units are also disclosed in the following U.S. Pat. Nos.:
3,609,700 issued 9/28/71;
3,614,747 issued 10/19/71.
(17) CLOCK UNIT AND TIMING CIRCUITS (1320)
(a) The computer art is replete with clock and timing circuits. The following U.S. Pat. Nos. disclose typical clock and timing circuits:
3,355,710 issued 11/28/67;
3,417,379 issued 12/17/68;
3,254,329 issued 5/31/66;
2,297,305 issued 3/1/66;
2,781,446 issued 2/12/57;
3,413,454 issued 11/26/68;
3,555,594 issued 11/28/67.
(18) DATA MANAGEMENT UNIT (1321)
(a) See the following U.S. Pat. Nos. for typical data management and control systems:
3,618,045 issued 11/2/71;
3,665,487 issued 5/23/72;
3,639,912 issued 2/1/72;
3,495,220 issued 2/10/70;
3,599,158 issued 8/10/71.
(19) CONTROL STORE UNIT (1301)
(a) Control stores are well known in the computer art. See prior reference books entitled Microprogramming: Principles and Practices, by Samir S. Husson and Computer Organization and Microprogramming, by Yao-Yaohan Chu.
(b) The following U.S. Pat. Nos. also disclose typical control stores:
3,380,025 issued 4/23/68;
3,469,247 issued 9/23/69;
3,160,858 issued 12/8/64.
(20) CONTROL STORE INTERFACE ADAPTER (1302)
(a) See the following U.S. patents:
3,636,524 issued 1/18/72;
3,353,162 issued 11/14/67;
3,868,649 issued 2/25/75;
3,611,311 issued 11/5/71.
(21) CONTROL STORE LOADER AND CONTROL AND LOAD UNIT (1303,1304)
(a) Program and microprogrammed loaders are well known in the computer art. See for example pages 284-294 of the above-referenced book on Computer Organization and Microprogramming, by Yao Yaohan Chu.
(22) Firmware Computer
(a) The following U.S. Pat. Nos. further disclose microprogrammed computer processors including microprogrammed control units with which the instant invention may be practiced:
3,400,371 issued 9/3/68;
3,656,123 issued 4/11/72.
Claims
Certificate of Correction present
The claims shown below may not include correction changes. Use the corrected PDF for authoritative text.
What is claimed is:
1. In an internally programmed data processing apparatus having a memory comprised of a plurality of segments of addressable space, each segment being associated with a segment number for addressing said associated segment, each of said segments delineated by upper and lower variable bounds with predetermined ones of said segments storing a plurality of files of database records grouped in sets of database records, each set of database records having at least one owner database record and at least one member database record, each of said database records having at least one pointer for linking predetermined ones of said database records to predetermined others of said database records and also to predetermined ones of said sets, each pointer comprised of an area, page and line address, said area address for locating a predetermined file of said database records, said page address for locating a predetermined group of said database records within said file, and said line address for locating a predetermined one of said database records, each of said database records also being associated with one each of a record descriptor for describing said associated database record, said record descriptors being stored in predetermined seconds of said segments, each of said sets also being associated with one each of a set-descriptor for describing said associated set and for providing a displacement address of said pointer in a first record of said set of associated records, said set descriptors being stored in predetermined thirds of said segments; said data processing apparatus further having a system base from which absolute addresses of said segments, database records and descriptors are referenced, said data processing apparatus also having a plurality of base registers, each base register for storing first coded electrical signals indicative of the segment number of any of said segments and also storing second coded electrical signals indicative of an offset address associated with the segment number, said offset address for addressing from the beginning of an associated segment any data within said associated segment; said data processing apparatus further having at least one index register for storing third coded electrical signals indicative of the area, page and line address of said predetermined one of said database records; said data processing apparatus further having an arithmetic and logic unit (ALU) having communication channels with said base registers, index registers and system base for performing arithmetic and logic operations of any data or address of said segments, database records, and descriptors; instruction hardware responsive to fourth coded electrical signals indicative of a find owner instruction for finding the owner record (i.e. said predetermined one of said database records) of said predetermined first of said database records, said find owner instruction having a first base register address (BR) for identifying a first of said plurality of base registers storing fifth coded electrical signals indicative of a first segmented address of said predetermined first of said database records, said first segmented address comprised of a first segment number in a first offset address of said predetermined first of said database records, and said find owner instruction further having a first address syllable for identifying a second of said base registers for providing a second segment number and second offset address of the set descriptor associated with said predetermined first of said database records, said instruction hardware comprising: (a) first means coupled for being responsive to coded electrical signals stored in said first base register for fetching said fourth coded electrical signals indicative of said first segmented address into said arithmetic and logic unit; (b) second means coupled to said first means for converting the fourth coded signals indicative of said first segmented address into seventh coded signals indicative of a first absolute address for locating said first of said database records relative to said system base; (c) third means coupled to said second means for fetching eighth coded signals indicative of said first of said database records into said arithmetic and logic unit (ALU); (d) fourth means coupled for being responsive to ninth coded signals indicative of said first address syllable for identifying said second of said base registers, said second base register storing tenth coded signals indicative of said second segment number and second offset address of said set descriptor associated with said predetermined first of said database records; (e) fifth means coupled to said fourth means for converting said tenth coded signal indicative of said second number and second offset address into eleventh coded signals indicative of a second absolute address for locating said set descriptor associated with said predetermined first of said database records; (f) sixth means coupled to said fifth means for fetching twelfth coded signals indicative of said set descriptor into said ALU; (g) seventh means coupled for being responsive to thirteenth coded signals indicative of the displacement address in said set descriptor for addressing from the beginning of said first of said database records, an owner pointer of said pointers in said first of said database records; and, (h) eighth means coupled to said seventh means for fetching fourteenth coded signals indicative of said owner pointer into said index register.
2. The apparatus as recited in claim 1 including ninth means coupled to said third coded signals in said index register for converting said third coded signals indicative of said area, page and line address of said predetermined one of said database records into fifteenth coded signals indicative of a third segmented address having a third segment number and third offset address for addressing said owner record (i.e. predetermined one of said database records).
3. The apparatus as recited in claim 2 coupled to said ninth means and said base registers and including tenth means for loading said fifteenth coded signals indicative of said third segmented address into said first base register.
4. The apparatus as recited in claim 3 wherein said group of database records are located within a page in one of said segments, said page located at a predetermined first area and first page address, and said page having at a predetermined first line-address a record-state indicator, and including eleventh means for ascertaining that said predetermined first record is located in said page.
5. The apparatus as recited in claim 4 including twelfth means responsive to sixteenth coded signals of said set descriptor associated with said predetermined first of said database records for identifying the type of pointer in said first and second database records.
6. The apparatus as recited in claim 5 wherein said pointer is of the type having an area, page and line address of said owner record.
7. The apparatus as recited in claim 6 wherein said pointer is of the type having a page and line address of said owner record.
8. The apparatus as recited in claim 7 wherein said pointer has a segmented address comprised of a segment number and an offset address of said owner record.
9. In an internally programmed data processing apparatus having a memory comprised of a plurality of segments of addressable space, each segment being associated with a segment number for addressing said associated segments, each of said segments delineated by upper and lower variable bounds with predetermined ones of said segment storing a plurality of files of database records grouped in sets of database records, each set of database records having at least one owner database record and at least one member database record, each of said database record having at least one pointer for linking predetermined ones of said database records to predetermined ones of said sets, each pointer comprised of a segment number and an offset address for locating predetermined ones of said database records, each of said database records also being associated with one each of a record descriptor for describing said associated database record, said record descriptors being stored in predetermined seconds of said segments, each of said sets also being associated with one each of a set-descriptor for describing said associated set and for providing a displacement address of said pointer in a first record of said set of associated records, said set descriptors being stored in predetermined thirds of said segments; said data processing apparatus further having a system base from which absolute addresses of said segments, database records, and descriptors are referenced, said data processing apparatus also having a plurality of base registers, each base register for storing the segment number of any of said segments and also storing an offset address associated with the segment number, said offset address for addressing from the beginning of an associated segment any data within said associated segment; said data processing apparatus further having an arithmetic and logic unit (ALU) having communication channels with said base registers, index registers and system base for performing arithmetic and logic operations on any data or address of said segments, database records and descriptors; instruction hardware responsive to first coded signals indicative of a find-owner instruction for finding the owner record of said predetermined first of said database records, said find-owner instruction having a first base register address (BR) for identifying a first of said plurality of base registers storing a first segmented address of said predetermined first of said database records, said first segmented address comprised of a first segment number and a first offset address of said predetermined first of said database records, and said find owner instruction further having a first address syllable for identifying a second of said plurality of base registers for providing a second segment number and a second offset address of the set descriptor associated with said predetermined first of said database records, said instruction hardware comprising: (a) first means coupled for being responsive to second coded signals stored in said first base register for fetching third coded electrical signals indicative of said first of said database records into said arithmetic and logic unit ALU; (b) second means coupled to said first means for fetching fourth coded signals indicative of said set descriptor into said ALU; (c) third means coupled for being responsive to fifth coded signals indicative of the displacement address in said set descriptor for addressing from the beginning of said first of said database records an owner pointer of said pointers in said first of said database records; and (d) fourth means coupled to said third means for fetching sixth coded signals indicative of said owner pointer into said ALU.
10. The apparatus as recited in claim 9 including fifth means coupled to said ALU for placing said sixth coded signals indicative of said owner pointer into said first base register.
Patent Citations (16)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3389380 | 1968-06-01 | Ashbaugh et al. | |
| US3401376 | 1968-09-01 | Barnes et al. | |
| US3533075 | 1970-10-01 | Johnson et al. | |
| US3614746 | 1971-10-01 | Klinkhamer | |
| US3656123 | 1972-04-01 | Carnevale et al. | |
| US3693165 | 1972-09-01 | Reiley et al. | |
| US3787813 | 1974-01-01 | Cole et al. | |
| US3821708 | 1975-08-01 | Casey et al. | |
| US3878513 | 1975-04-01 | Werner | |
| US3889243 | 1975-06-01 | Drimak | |
| US3891974 | 1975-06-01 | Coulter et al. | |
| US3909798 | 1975-09-01 | Wallach et al. | |
| US3916385 | 1975-10-01 | Parmar et al. | |
| US3916387 | 1975-10-01 | Woodrum | |
| US3938096 | 1976-02-01 | Brown et al. | |
| US3950730 | 1976-04-01 | Bienvenu et al. |