US 4,025,866 AGrant
Open Loop Digital Frequency Multiplier
Issue Date:1977-05-24
•6 Claims
•1 Drawing Sheets
Abstract
An open loop digital frequency multiplier with a multiplied output synchonized to low frequency clock pulses. The system includes a multi-stage digital counter which provides a pulse output as a function of an integer divisor. The integer divisor and the timing or counting cycle of the counter are interrelated to the frequency of a clock input. The counting cycle is controlled by a one-shot multivibrator which, in turn, is driven by a reference frequency input.
Metadata
Inventors
- James C. Administrator of the National Aeronautics and Space Administration, with respect to an invention of Fletcher
- Robert Clark Moore
Application Information
Application Number:US 6305830
Filing Date:1975-11-10
Priority Date:1975-11-10
Art Unit:254
Classifications
IPC:
H03K 500H03K 2132
Field of Search:
307328220 R;225 R38;129;39;48;63
Patent Drawings (1 sheets)
Description
Field of the Invention
This invention relates to a system for producing multiplied frequency pulses which are synchronized to a low frequency reference clock pulse, and, more particularly, for producing high frequency clock pulses as a multiple function of low frequency clock pulses in a stabilized operation.
Digital frequency multiplying systems are frequently made fairly complex in order to obtain a reliable control of two frequencies in synchronization. As compared to conventional phase-locked loop systems, the present invention utilizes digital circuits. It also avoids use of bulk components and has zero acquisition time. Thus, it is the purpose of this invention to provide a relatively simple straight-forward system by which a digital frequency multiplier can be synchronized to low frequency clock pulses.
Summary of the Invention
In the present invention, a digital frequency multiplier system synchronizes and multiplies low frequency clock pulses to high frequency clock pulses where the high frequency clock pulses are a multiple of the low frequency. The reset of a digital counter means is controlled by a timing period so that output frequency of the pulses from the counter means is an even multiple of the timing period. The timing period is controlled by a one-shot multivibrator which is triggered by reference frequency pulses. To obtain reliability, the digital counter means has a divider circuit which divides input high frequency clock pulses by an integer value so that its output pulses are a function of the integer value. By relating the values of the integer value and the timing period as a function of the frequency of the high frequency clock pulses, the low frequency clock pulses are synchronized to the output frequency of the digital counter means with a high degree of reliability.
Brief Description of the Drawings
FIG. 1 is a schematic representation of one embodiment of the present invention; and
FIG. 2 is a wave form representation of the timing relationship of the system.
Description of Preferred Embodiment
Referring now to FIG. 1, a digital counter means 10 has an input 11 for receiving clock pulses from a high frequency generator or oscillator 12. Built into the counter 10 is divider circuit means which divide the input frequency by a integer value "N". Thus, the output pulses are a function of the integer value N and the input frequency. The counter 10 has a reset input 13 by which a pulse input can reset the counter circuits. The reset input 13 is coupled to one-shot multivibrator 14, which, in turn, is connected to a frequency reference source 15. The frequency reference source 15 supplies a clock frequency pulse input to the one-shot multivibrator 14, which, in turn, resets the counter periodically or repetitively on the falling edge of the reference frequency source pulses.
For a more complete understanding of the interrelationship of the components, consider the desired multiplier function represented by the letter " M", an integer greater than unity, the reference frequency from the frequency reference source 15 represented by the symbol F.sub.R and the multiplied frequency at the output 16 represented by the symbol F.sub.M, then
the relationship of the frequency of the oscillator 12 clock input to the counter 10 to the output 16 is such that the frequency F.sub.O of the oscillator 12, when divided by integer value N is equal to the frequency F.sub.O, as
stated another way with respect to equations (1) and (2), the frequency F.sub.O of the oscillator 12 is also equal to the multiplier function times the integer times the reference frequency, as
the pulse width T of the output of the one-shot multivibrator 14 is predetermined and the multivibrator output signal triggers the reset of the counter 10. The output pulse width T can be defined as: ##EQU1##
The key to output frequency F.sub.M to exactly " M" full cycles, the oscillator frequency must be maintained between the following functions: ##EQU2##
For any given stability of the oscillator 12, equation (5) sets a minimum value for the divisor M.
As shown in FIG. 2, the reference frequency F.sub.R periodically occurs and triggers the multivibrator 14. The pulse output of the multivibrator 14 has a time period T during which the counter 10 is reset. The oscillator 12 supplies pulses to the counter 10 at a frequency equal to the product of the multiplier function M, the integer value N and the reference frequency F.sub.R. The counter 10 divides the oscillator frequency by the integer value N to provide the multiplied output frequency F.sub.M.
In a practical example of the foregoing system, the following relationship is exemplary:
Reference frequency F.sub.R = 1Hz
Multiplier Function M= 400
Output frequency F.sub.M = 400Hz
N= 256
t= 4.88 microseconds
F.sub.O = 102,400 Hz.+-. 64 Hz.
This means that the frequency stability of the oscillator should be better than plus or minus 0.0625 percent. It will be noted that it is convenient to make the integer N a power of either 2 or 10.
While particular embodiments of the present invention have been shown and described, it is apparent that changes and modifications may be made without departing from this invention in its broader aspects; and therefore, the aim in the appended claims is to cover all such changes and modifications as fall within the true spirit and scope of this invention.
Claims
What is claimed is:
1. An open-loop digital frequency multiplier for multiplying a low frequency of clock pulses by a desired multiple M to produce high frequency output pulses which are synchronized to low frequency reference pulses, said multiplier comprising: a source of clock pulses at a low reference frequency, a source of higher frequency clock input pulses, a multi-stage digital counter means which produces as its output said high frequency output pulses, reset means coupled to said source of reference frequency clock pulses and responsive thereto for providing to said digital counter means repetitive reset pulses having a pulse width of time duration T for repetitively resetting said counter means as periodic occurrences corresponding to said reference frequency pulse occurrences, means coupling said higher frequency clock input pulses to the digital counter means, said digital counter means including means for dividing said higher input frequency of clock input pulses by an integer value N whereby the output frequency of said output pulses produced by the digital counter means represents the product of said reference frequency and the multiplier function M and equals the ratio of said higher frequency of clock input pulses and the integer N.
2. The apparatus as defined in claim 1 wherein the frequency of said input frequency clock pulses is between the limits determined by the following equation: ##EQU3## where N= the integer value M= the frequency of said output pulses divided by the frequency of the reference input pulses F.sub.ref = the reference frequency F.sub.osc = the frequency of the input clock pulses
3. The apparatus as defined in claim 2 wherein the integer value is a power of the number two or ten.
4. The apparatus as defined in claim 3 wherein said timing period has a pulse width T equal to ##EQU4##
5. The apparatus as defined in claim 4 wherein said input pulses are at a frequency equal to MNF.sub.ref and equal to NF out.
6. The multiplier as defined in claim 1 wherein said reset means comprises a one-shot multivibrator means whereby the reset pulses are generated at instances corresponding to the falling edges of said reference frequency source pulses and said counter means is reset during said time duration T.
Patent Citations (5)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3579126 | 1971-05-01 | Paul | |
| US3657658 | 1972-04-01 | Kubo | |
| US3673391 | 1972-06-01 | Lougheed | |
| US3716794 | 1973-02-01 | Teggatz et al. | |
| US3835396 | 1974-09-01 | Demos et al. |
Non-Patent Literature (1)
- "A New Type of Digital Frequency Multiplier," by Horelick et al., Proceedings of the IEEE, Sept. 1975, [pp. 1365-1366].