Counter Using an Inverter and Shift Registers

This invention relates to a counter comprised of an inverter and shift registers and suitable for an integrated circuit using insulated gate field effect transistors.

U.S. Pat. No. 3,766,408 discloses a scale-of-n counter comprising an inverter and n-1 one-bit shift registers and adapted to produce an output having a frequency 1/n times that of clock signals to be counted. In this counter, the one-bit shift registers are connected in cascade and, each, has a data-readin half-bit shift register and data-readout shift register and the inverter is coupled between the (n-1)-th stage shift register and the first stage shift register.

Each of the 1st to (n-2)-th stage shift registers or 2nd to (n-1)-th stage shift registers has an additional or reset terminal and is operative to transfer to its output a data given to its input in response to clock signals to be counted, when the additional input is at a first voltage level, and operative to make its output at a predetermined voltage level when the additional input is at a second voltage level. If each of the 1st to (n-2)-th stage shift registers has an additional input, the output of the (n-1)-th shift register is coupled to the additional input of these shift registers and, if each of the 2nd to (n-1)-th shift registers has an additional input, the output of the inverter is coupled to the additional input of these shift registers. In the former case, the additional input of the shift registers is coupled to a data-readout half-bit shift register of the one-bit shift registers and in the latter case the additional input of the shift registers is coupled to a data-readin half-bit shift register of the one-bit shift registers.

With the above-mentioned scale-of-n counter, n-1 one-bit shift registers or 2(n-1) half-bit shift registers are required. In a scale-of-11 counter, for example, 10 one-bit shift registers and thus 20 half-bit shift registers are necessary.

Recently, a table-top type electronic calculator, etc., for example, widely utilizes high density integrated circuits and to manufacture such high density integrated circuits it is desired that the number of components in a circuit designed for one function be reduced.

It is accordingly the object of this invention to provide a counter capable of accomplishing a desired scale counting using a lesser number of shift registers.

According to one aspect of this invention there is provided a counter for counting clock signals comprising 2n+1 cascade-connected stages each having an input and output, one stage of which is an inverter and the remaining 2n stages of which are 1st to 2n-th half-bit shift registers each operative to produce at the output an output state corresponding to an input data state at the input in response to clock signals to be counted, at least one of the even-numbered stages of the 2nd to 2(n-2)-th half-bit shift register stages or at least one of the odd-numbered stages of the 3rd to (2n-3)-th half-bit shift register stages having an additional input and being operative to produce at the output an output state corresponding to an input data state on the input when the additional input is at a first voltage level and operative to make the output at a predetermined voltage level when the additional input is at a second voltage level; means for coupling the output of the final stage of said cascade connection to the input of the first stage of said cascade connection and the additional input of at least one of the half-bit shift registers; and means for applying clock signals to each of the 2n half-bit shift register stages to operate n odd-numbered half-bit shift register stages and n even-numbered half-bit shift register stages alternately.

This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram of a counter according to one embodiment of this invention;

FIG. 2 is a block diagram of a counter according to another embodiment of this invention;

FIG. 3 is a block diagram of a counter according to a further embodiment of this invention;

FIG. 4 is a block diagram of a counter according to a still further embodiment of this invention;

FIG. 5 is a block diagram of a counter according to another embodiment of this invention;

FIG. 6 is a block diagram of a counter according to a further embodiment of this invention;

FIG. 7 is a waveform diagram for explaining the operation of the counter of FIG. 3; and

FIGS. 8 to 10, each, show a circuit arrangement of a counter embodying this invention, in which complementary insulated gate field effect transistors are used.

FIG. 1 shows one embodiment of this invention. In this Figure an inverter I.sub.n and n one-bit shift registers, for example seven one-bit shift registers S.sub.1 to S.sub.7 are connected in cascade configuration, the output of the final-stage shift register (S.sub.7 in FIG. 1) being coupled to the input of the inverter I.sub.n. Each one-bit shift register consists of a data-readin half-bit shift register and a data-readout half-bit shift register and is operated to read in an input data applied to an input I in response to a writing clock signal .phi..sub.1 and to read out the input data from an output O in response to a readout clock signal .phi..sub.2. The 1st to X-th stage shift registers (X=3 in this case), each, has a reset or additional input I' coupled to the output of the final stage shift register (S.sub.7 in this case).

The shift register having the additional input I' is operative to transfer a data on the input I to the input O of the shift register in response to the clock signals .phi..sub.1 and .phi..sub.2, when the additional input I' is at a first voltage level, for example, a voltage level corresponding to logic "0," and make the output O at a predetermined voltage level, for example, a voltage level corresponding to logic "0" when the additional input I' of the shift register is at a second voltage level, for example, a voltage level corresponding to logic "1". In the arrangement shown in FIG. 1 the additional input I' of the shift register is coupled to the output stage of one-bit shift register, or the data-readout half-bit shift register. When, therefore, the additional input I' of the shift register is at the voltage level corresponding to logic "1," the output O of that shift register is forcedly brought to logic "0" state.

In the counter shown in FIG. 1, suppose that the outputs of the shift registers S.sub.1 to S.sub.7 are initially "0" state and thus the output of the inverter I.sub.n is "1" state. In this case, successive seven pairs of clock signals .phi..sub.1, .phi..sub.2 are required to bring all the outputs of the shift registers S.sub.1 to S.sub.7 to the "1" state by the output "1" of the inverter I.sub.n. When the output of the shift register S.sub.7 becomes "1," the outputs O of the shift registers S.sub.1 to S.sub.3 having the additional input I' as well as the output of the inverter I.sub.n are rendered "0," In order to bring the outputs of the shift registers S.sub.4 to S.sub.7 to the "0" state by the outputs "0" of the inverter I.sub.n and shift registers S.sub.1 to S.sub.3, next subsequent four pairs of clock signals .phi..sub.1 and .phi..sub.2 are further necessary.

It will be noted that, since the outputs of the inverter I.sub.n and shift registers S.sub.1 to S.sub.7 can be returned to the original "1" and "0" states, respectively, by arrival of the successive 11 pairs of clock signals .phi..sub.1 and .phi..sub.2, the counter of FIG. 1 acts as a scale-of-11 counter, and the frequency of each output of the inverter I.sub.n and shift registers S.sub.1 to S.sub.7 becomes one-eleventh that of the clock signals .phi..sub.1 and .phi..sub.2.

Where, among the n one-bit shift registers, the consecutive 1st to X-th stage one-bit shift registers (X=an integer from 2 to n-2) have an additional input I' coupled to the output of the n-th stage shift register, a scale-of-2n-X counter is constituted. The arrangement shown in FIG. 1 corresponds to the case where n=7 and X=3. In this embodiment, the inverter I.sub.n may be coupled between the data-readin half-bit shift register and the data-readout half-bit shift register in the first stage one-bit shift register S.sub.1.

Where the embodiment of FIG. 1 is considered as including 2n halfbit shift registers, the consecutive even-numbered stages from the 2nd stage half-bit shift register (corresponding to the data-readout half-bit shift register in the first stage one-bit shift register S.sub.1) to the 2X-th half-bit shift register (corresponding to the data-readout half-bit shift register in the X-th stage one-bit shift register) have an additional input I'.

The scale-of-11 counter shown in FIG. 1 consists of seven one-bit shift registers, which can save three shift registers as compared with a conventional counter, thus reducing the number of elements to a considerable extent. Each of the shift registers S.sub.4 to S.sub.7 may have an additional input, too. Where a voltage corresponding to logic "0" is normally applied to the additional inputs of the shift registers S.sub.4 to S.sub.7, the same scaling operation is effected. This means that all the shift registers may, each, have an additional input, and if the additional input of the shift registers required is coupled to the output of the final stage shift register, then a desired scaling operation can be effected.

FIG. 2 shows a scale-of-11 counter in which the third stage shift register S.sub.3 only has the additional input I' coupled to the output O of the final stage shift register S.sub.7. In the embodiment of FIG. 2 the inverter I.sub.n may be connected at any point between the output of a readin half-bit shift register in the third stage one-bit shift register S.sub.3 having the additional input I' and the input of readin half-bit shift register in the first stage one-bit shift register S.sub.1.

Suppose that, in this embodiment, the outputs of shift registers S.sub.1 to S.sub.7 are initially the "0" state and in consequence the output of the inverter I.sub.n is the "1" state. In this case, successive five pairs of clock signals .phi..sub.1, .phi..sub.2 will be required to bring the outputs of the shift registers S.sub.3 to S.sub.7 to the "1" state by the output "1" of the inverter I.sub.n. When the output of the final stage shift register S.sub.7 becomes "1," the output of the third stage shift register S.sub.3 becomes "0." In order to bring the outputs of the shift registers S.sub.4 to S.sub.7 to the "0" state by the output "0" of the shift register S.sub.3, the next subsequent four pairs of clock signals .phi..sub.1, .phi..sub.2 are further required. At the time when the output of the shift register S.sub.7 becomes "0," the outputs of the shift registers S.sub.1 and S.sub.2 are "1." In order to bring the outputs of the shift registers S.sub.1 and S.sub.2 to the "0" state, the next subsequent two pairs of clock signals .phi..sub.1, .phi..sub.2 are further required. As will be understood from the above, the outputs of the shift registers S.sub.1 to S.sub.7 are all returned to the original "0" state upon arrival of the 11 pairs of clock signals .phi..sub.1, .phi..sub.2 and thus a counter of FIG. 2 effects counting on the basis of a scale-of-11 as in the case of the counter of FIG. 1.

Suppose that, in the embodiment of FIG. 2 n number of shift registers is used. If, in this case, an X-th shift register has an additional input I' coupled to the output of the n-th stage shift register, counting is effected on the basis of a scale-of-2n-X, in which X is an integer from 1 to n/2, if n is an even number, and 1 to (n-1)/2 if n is an odd number. In the embodiment of FIG. 2 in which n=7, any shift registers S.sub.1 to S.sub.3 may have an additional input I'. Where, for example, the shift register S.sub.1 has an additional input I', a scale-of-13 (2.times.7-1=13) counting is carried out. Where, on the other hand, the shift register S.sub.2 has an additional input I', a scale-of-12 (2.times. 7- 2=12) counting is conducted. In the former case, the inverter I.sub.n should be coupled to the input or output of the readin half-bit shift register in the shift register S.sub.1 and, in the latter case, the inverter I.sub.n should be coupled between the input of the readin half-bit shift register in the shift register S.sub.2 and the output of the readout half-bit shift register in the shift register S.sub.1.

If the embodiment of FIG. 2 is considered as a counter having 2n number of half-bit shift registers, only the data-readout half-bit shift register in a 2X-th stage may have an additional input, provided that X is an integer from 1 to n/2, if n is an even number, and 1 to (n-1)/2 if n is an odd number.

FIG. 4 shows another embodiment of this invention. In this embodiment, one-bit shift registers S.sub.2 to S.sub.4, each, have an additional input I'. An inverter I.sub.n is coupled to the output of a final stage shift register S.sub.7 and the output of the inverter I.sub.n is coupled to the input of the first stage shift register S.sub.1 and the additional inputs I' of the shift registers S.sub.2 to S.sub.4. In this embodiment, the additional input I' of the shift registers S.sub.2 to S.sub.4 is coupled to the input stage or the readin half-bit shift register thereof. When the additional input I' of the shift registers S.sub.2 to S.sub.4 is, for example, at the voltage level "1," each of the shift registers S.sub.2 to S.sub.4 transfers a data on the input I of the shift registers S.sub.2 to S.sub.4 to the output O of the shift registers S.sub.2 to S.sub.4 in response to clock signals .phi..sub.1 , .phi..sub.2. When, on the other hand, the additional input I' of the shift registers S.sub.2 to S.sub.4 is at the voltage level "0," each of the shift registers S.sub.2 to S.sub.4 is operative to bring the output O to a predetermined voltage level, for example, a voltage level corresponding to logic "0." If all the outputs of the shift registers S.sub.1 to S.sub.7 are initially "0" state and in consequence the output of the inverter I.sub.n is "1" state, then successive seven pairs of clock signals, .phi..sub.1, .phi..sub.2 are required to bring the outputs of the shift registers S.sub.1 to S.sub.7 to the "1" state by the "1" output of the inverter I.sub.n. When the output of the shift register S.sub.7 becomes "1" and in consequence the output of the inverter I.sub.n becomes "0," the output of the shift registers S.sub.2 to S.sub.4 becomes "0" in synchronism with the next readout signal .phi..sub.2. In order to bring the output of the shift registers S.sub.5 to S.sub.7 to the "0" state by the output "0" of the shift registers S.sub.2 to S.sub.4, i.e., return all the outputs of the shift registers S.sub.1 to S.sub.7 to the original "0" state, the next subsequent three pairs of clock signals .phi..sub.1, .phi..sub.2 are further necessary. As will be evident from the above, since all the outputs of the shift registers S.sub.1 to S.sub.7 are returned to the original state by arrival of successive 11 pairs of clock signals .phi..sub.1, .phi..sub.2, a scale-of-11 counting is carried out.

Where n one-bit shift registers are provided, the consecutive 2nd to X-th stage shift registers (x=an integer from 3 to n-1) may have an additional input I'. In this case, a scale-of-2n-(X-1) counting is effected. The embodiment of FIG. 4 shows the case where n=7 and X=4. The inverter I.sub.n may be connected at any point between the output of the readin half-bit shift register in the X-th stage one-bit shift register and the output of the n-stage one-bit shift register. Assume that the embodiment of FIG. 4 has 2n half-bit shift registers. In this case, the odd-numbered stage half-bit shift registers (data-readin half-bit shift registers) from the third stage half-bit shift register (corresponding to the data-readin half-bit shift register in the 2nd one-bit shift register S.sub.2) to the (2X-1) stage half-bit shift register (corresponding to the data-readin half-bit shift register in the X-th stage one-bit shift register) has an additional input. The inverter I.sub.n may be connected to output of either one of the (2X-1)-th to 2n-th stage half-bit shift registers.

FIG. 5 shows a scale-of-11 counter in which a fourth stage one-bit shift register S.sub.4 alone has an additional input I' and the inverter is connected between S.sub.4 and S.sub.5. Suppose that all the outputs of shift registers S.sub.1 to S.sub.7 are, at first, "0" and thus the output of the inverter I.sub.n is "1." In this case, successive three pairs of clock signals .phi..sub.1, .phi..sub.2 are required to bring the output of the registers S.sub.5 to S.sub.7 to the "1" state by the output "1" of the inverter I.sub.n. The output of the shift registers S.sub.1 and S.sub.4 becomes "1" upon arrival of the next fourth pair of clock signals .phi..sub.1, .phi..sub.2 and in consequence the output of the inverter I.sub.n becomes 0. In order to bring the output of the shift registers S.sub.5 to S.sub.7 to the "0" state by the output "0" of the inverter I.sub.n, the next subsequent three pairs of clock signals .phi..sub.1, .phi..sub.2 are further required. At this time, the output of the shift registers S.sub.1 to S.sub.4 is "1." In order to bring the output of the shift registers S.sub.1 to S.sub.4 to the "0" state, the next subsequent four pairs of clock signals .phi..sub.1, .phi..sub.2 are further necessary. That is, the output of each shift register is returned to the original state "0" upon arrival of the successive 11 pairs of 100.sub.1, .phi..sub.2. As a result, a scale-of-11 counting is carried out.

Suppose that the embodiment of FIG. 5 has n one-bit shift registers. Where n is an even number, any one of the 2nd to (n+2)/2-th stage one-bit shift register may have an additional input I'. Where, on the other hand, n is an odd number, any one of the 2nd to (n+1)/2-th stage one-bit shift registers may have an additional input I'. If the X-th stage one-bit shift register has an additional input I', a scale-of-2n-(X-1) counting can be effected. The embodiment of FIG. 5 shows the case where n=7 and X=4.

Consider the embodiment of FIG. 5 as having 2n half-bit shift registers. In this case, the (2X-1)-th stage half-bit shift register (corresponding to the data-readin half-bit shift register in the X-th stage one-bit shift register) may have an additional input I'. The inverter I.sub.n may be coupled to the output of either one of the (2X-1)-th to 2n-th half-bit shift registers.

FIG. 3 shows an embodiment of a scale-of-11 counter according to the type of FIG. 1. In this embodiment, each one-bit shift register uses, as its data-readin half-bit shift register, a clocked inverter 10 operative to invert an input data by application of complementary clock signals .phi..sub.1, .phi..sub.1, and as its data-readout half-bit shift register a clocked NOR circuit 20 fundamentally including a clocked inverter operated by complementary clock signals .phi..sub.2, .phi..sub.2. To the clocked NOR circuit 20 of one-bit shift registers S.sub.1 to S.sub.3 are applied the output of the clocked inverter 10, the output of the final stage one-bit shift register S.sub.7 and a clear signal on a clear signal line 1. When the clear signal and the output of the shift register S.sub.7 are both at the voltage level "0," the clocked NOR circuits 20 act as a clocked inverter. When, on the other hand, either the clear signal or the output of the shift register S.sub.7 is the voltage level "1," the clocked NOR circuits are operative to make their outputs at the voltage level "0" irrespective of the output of the corresponding clocked inverter 10. The output of the clocked inverter 10 and clear signal on the clear signal line 1 are applied to the clocked NOR circuit 20 in the shift registers S.sub.4 to S.sub.7.

The operation of the counter shown in FIG. 3 will now be explained by referring to FIG. 7.

By a clear signal with a voltage level of "1," the outputs A to G of the shift registers S.sub.1 to S.sub.7 are made at the voltage level "0" and in consequence the output G of the inverter I.sub.n is made at the voltage level "1." When the clear signal becomes "0" at time t.sub.3, the output A of the shift register S.sub.1 is made at the "0" state. By the output A with the voltage level "1," the outputs B to G of the shift registers S.sub.2 to S.sub.7 are sequentially brought to the "1" state in response to the clock signals .phi..sub.1 and .phi..sub.2. At time t.sub.9, the output G of the final stage shift register S.sub.7 becomes "1," and the outputs A to C of the shift registers S.sub.1 to S.sub.3 become "0." Subsequently, the outputs D to G of the shift registers S.sub.4 to S.sub. 7 are sequentially made at the "0" state. At time t.sub.14, the output A of the shift register S.sub.1 becomes "1." This means that the outputs of the shift registers S.sub.1 to S.sub.7 and the output of the inverter I.sub.n are all returned to the original state. As will be evident from the waveform of FIG. 7 the outputs of the shift registers S.sub.1 to S.sub.7 and inverter I.sub.n, all, have a period 11 times that of the clock signals .phi..sub.1, .phi..sub.2.

FIG. 6 shows an embodiment of a scale-of-11 counter of the type shown in FIG. 4. In this embodiment, each one-bit shift register uses a clocked NAND circuit 30 as a data-readin half-bit shift register and a clocked inverter 40 as a data-readout half-bit shift register.

While, in the embodiments shown in FIGS. 3 and 6, the clear signal is supplied to each one-bit shift register, application of the clear signal is not always necessary. The clear signal may be delivered to at least one one-bit shift register. Where, in the embodiments of FIGS. 3 and 6, the inverter I.sub.n is coupled between the data-readin half-bit shift register and the data-readout half-bit shift register in a one-bit shift register, the clocked NOR circuit and clocked NAND circuit may be replaced by the clocked NAND circuit and clocked NOR circuit, respectively.

FIG. 8 shows a circuit arrangement of a scale-of-8 counter using five one-bit shift registers S.sub.1 to S.sub.5 according to the type of FIG. 3. An inverter I.sub.n includes complementary insulated gate field effect transistors 61.sub.P, 62.sub.N whose source-drain paths are series connected between a VDD (or clock signal .phi..sub.2) supply line 5 and a VSS (or clock signal .phi..sub.2) supply line 6. The gate electrodes of transistors 61.sub.P and 62.sub.N are coupled to the output of the final stage one-bit shift register S.sub.5. A first stage one-bit shift register S.sub.1 has a clocked inverter 10 as a date-readin half-bit shift register and a clocked NOR circuit 20 as a data-readout half-bit shift register. The clocked inverter 10 has complementary inverting transistors 12.sub.P and 13.sub.N and complementary switching transistors 11.sub.P and 14.sub.N. The source-to-drain paths of these transistors 11.sub.P, 12.sub.P, 13.sub.N and 14.sub.N are serially connected between a VDD (or clock signal .phi..sub.1) supply line 4 and a VSS (or clock signal .phi..sub.1) supply line 7. The gate electrodes of the inverting transistors 12.sub.P and 13.sub.N are connected to the drain electrodes of the transistors 61.sub.P and 61.sub.N in the inverter I.sub.n. Clock signals .phi..sub.1 and .phi..sub.1 are applied respectively through clock lines 2 and 9 to the gate electrodes of switching transistors 11.sub.P and 14.sub.N. The clocked NOR circuit 20 includes complementary inverting transistors 22.sub.P and 23.sub.N and complementary switching transistors 21.sub.P and 24.sub.N. The source-drain paths of these transistors 21.sub.P, 22.sub.P, 23.sub.N and 24.sub.N are serially connected between the VDD supply line 5 and the VSS supply line 6. The gate electrodes of the inverting transistors 22.sub.P and 23.sub.N are connected to the drain electrodes of the inverting transistors 12.sub.P and 13.sub.N in the clocked inverter 10. Clock signals .phi..sub.2 and 100.sub.2 are applied respectively through clock lines 3 and 8 to the gate electrodes of the switching transistors 21.sub.P and 24.sub.N. The source-to-drain path of an N channel transistor 25.sub.N is connected between the VSS supply line 6 and the drain electrodes of the inverting transistors 22.sub.P and 23.sub.N, and the gate of transistor 25.sub.N is coupled to the output of the final stage shift register S.sub.5. Other one-bit shift registers S.sub.2 to S.sub.5 are constructed like the shift register S.sub.1, but the gate electrode of each transistor in shift registers S.sub.3 to S.sub.5 which corresponds to the transistor 25.sub.N in the shift register S.sub.1 is coupled to the clear signal line 1.

FIG. 9 shows a circuit arrangement of a scale-of-11 counter according to the type of FIG. 2, though different in the connecting position of an inverter I.sub.n. Among 14 stage half-bit shift registers S'.sub.1 to S'.sub.14, only the sixth stage half-bit shift register S'.sub.6 corresponding to the data-readout half-bit shift register of the third stage one-bit shift register S.sub.3 is composed as a clocked NOR circuit.

FIG. 10 shows a circuit arrangement of a scale-of-11 counter according to the type of FIG. 5, though different in the connecting position of an inverter I.sub.n. Among 14 stage half-bit shift registers S'.sub.1 to S'.sub.14, only the seventh stage half-bit shift register S'.sub.7 corresponding to the data-readin half-bit shift register in the fourth stage one-bit shift register S.sub.4 is composed as a clocked NOR circuit. The reason for this is that the inverter I.sub.n is coupled between the data-readin half-bit shift register S'.sub.13 and the data-readout half-bit shift register S'.sub.14 in the seventh stage one-bit shift register S.sub.7.

Although the counters shown in FIGS. 8 to 10 use complementary insulated gate field effect transistors, each counter may be constituted using either p- or n-channel type insulated gate field effect transistors only. While the above-mentioned embodiments uses dynamic shift registers, static shift registers can also be used. Further, in the invention, a clocked bistable circuit comprised of two cross-coupled NAND/NOR gates can be used as a half-bit shift register. In this case, an inverter stage is connected between two one-bit shift register stages.