X-Y to Range-Bearing Converter

Most prior art hardware approaches for converting an X-Y position voltage into corresponding range and bearing readings have employed modulators to produce signals that yield a phase angle from which the bearing can be determined. These approaches have generally been exclusively analog, relying on conventional clamping and chopper circuits to obtain bearing output. A number of these techniques have utilized successive approximation methods requiring numerous feedback and comparison networks which slow down and complicate the converter circuitry. Further, such prior art analog approaches have lacked the versatility, reliability, and adaptability which a digitally designed converter would provide.

It is, therefore, an object of the present invention to convert analog rectangular coordinate inputs into digital range and bearing (polar) form in a simple, highly reliable fashion without using valuable computer time.

It is a further object of the present invention to examine the operational signs of the analog inputs to determine into which quadrant the bearing belongs and to provide multiplexing circuitry for appropriately channeling angle information to produce a bearing output located in the proper quadrant.

The present invention is divided into two sections: one for range, R, and the other for bearing, .theta.. Range, R, is determined by sending x- and y- inputs into a vector module, converting the analog output to digital, and processing the digital readout. The bearing calculation is accomplished by checking the signs of x and y and determining a trigonometric value derived from x and y (including R = .sqroot.x.sup.2 + y.sup.2) which can be fed into a Read Only Memory (ROM) and selective adder that convert the trigonometric value into an angle .alpha.', ranging between 0.degree. and 90.degree.. The signs of x and y indicate in which quadrant the angle .alpha.' is. If x and y are positive, for example, .alpha.' is in the first quadrant. If x is positive and y is negative .alpha.' is in the second quadrant and so on. Multiplexing circuitry is employed which adds to or subtracts from .alpha.' the appropriate number of degrees to give .theta.. For example, if .alpha.' = 15.degree. and x and y are negative (.alpha.' is in the third quadrant) the multiplexing circuitry will cause 180.degree. to be added to .alpha.' to give .theta. = 15.degree. + 180.degree. = 195.degree..

FIG. 1 is a block diagram representation of the present invention;

FIGS. 2A, 2B, and 2C are graphic representations showing two separate positions on a radar display;

FIGS. 3A and 3B are a truth table for coding the Read Only Memory provided in the invention; and

FIG. 4 is a circuit diagram showing elements which can comprise the Multiplex control of the present invention.

Referring to FIG. 1, two rectangular coordinate analog voltage inputs, an x input 2 and a y input 4, are shown. In determining range, R, a conventional vector module 6 is employed which operates on x input 2 and y input 4 to produce a voltage equal to .sqroot.x.sup.2 + y.sup.2. This output voltage represents R in analog form. By sending the output voltage through an analog-to-digital (A/D) converter 8, R is transformed into digital form. A/D converter 8 converts the output voltage from vector module 6 into a 12-bit binary code with the least significant bit being equal to about one-eighth (1/8) of a mile. The 12-bit binary is then converted into four decades of Binary Coded Decimal (BCD) by a Binary-to-BCD converter 10. R is then displayed on a range read-out display 12 which may be of the light-emitting diode (LED) variety.

In determining bearing, .theta., according to the preferred embodiment, the x input 2 and y input 4 are fed into an absolute-value-of-x circuit 14 and an absolute-value-of-y circuit 16, respectively. The absolute value circuits of each produce a sign output (labelled SIGN x and SIGN y in FIG. 1) and a magnitude (or absolute value) output (labelled .vertline.x.vertline. and .vertline.y.vertline. in FIG. 1). The magnitude output .vertline.x.vertline. from the absolute-value-of-x circuit 14 is compared to the magnitude output .vertline.y.vertline. from the absolute-value-of-y circuit 16 in a voltage comparator 18. The output from voltage comparator 18 is the lesser of the two magnitude input .vertline.x.vertline. and .vertline.y.vertline.. An analog switch 20, receiving .vertline.x.vertline. and .vertline.y.vertline. as inputs, is connected to the output of voltage comparator 18 which causes analog switch 20 to pass through the lesser magnitude output .vertline.x.vertline. or .vertline.y.vertline.. The lesser magnitude output .vertline.x.vertline. or .vertline.y.vertline. is then fed to an analog divider 22 where it is read as the dividend input. The divisor input to analog divider 22 is the output voltage equal to .sqroot.x.sup.2 + y.sup.2 coming from vector module 6. The output of analog divider 22 is either .vertline.x.vertline./.sqroot.x.sup.2 + y.sup.2 or .vertline.y.vertline./.sqroot.x.sup.2 + y.sup.2, whichever is less. This output may be viewed trigonometrically as sin .alpha., where .alpha. .ltoreq. 45.degree.. The sin .alpha. output is digitized by an A/D converter 24 which transforms the analog voltage representing sin .alpha. into a corresponding digital value. The digital value of sin .alpha. is then fed into a Read Only Memory (hereafter referred to as ROM) 26 which performs the inverse sine function yielding an output .alpha. = Sin.sup..sup.-1 (.vertline.x.vertline./.sqroot.x.sup.2 + y.sup.2) where .vertline.x.vertline.<.vertline.y.vertline. and .alpha. = Sin.sup..sup.-1 (.vertline.y.vertline./.sqroot.x.sup.2 + y.sup.2) where .vertline.y.vertline..ltoreq..vertline.x.vertline.. As shown in FIGS. 2A, 2B and 2C the value of .alpha., according to the preferred embodiment is always within the limits 0 < .alpha. < 45.degree.. In FIG. 2A, .vertline.x.vertline. < .vertline.y.vertline. and analog switch 20 passes through .vertline.x.vertline. with analog divider 22 producing an output .vertline.x.vertline./.sqroot.x.sup.2 + y.sup.2 ; angle .alpha. = Sin.sup..sup.-1 .vertline.x.vertline./.sqroot.x.sup.2 + y.sup.2) is less than 45.degree. as illustrated. In FIG. 2B .vertline.y.vertline. < .vertline.x.vertline. and analog switch 20 passes through .vertline.y.vertline. thereby producing an output .vertline.y.vertline./.sqroot.x.sup.2 + y.sup.2 from analog divider 22; .alpha. = Sin.sup..sup.-1 (.vertline.y.vertline./.sqroot.x.sup.2 + y.sup.2) in this case is again less than 45.degree.. Finally, in FIG. 2C .vertline.y.vertline. < .vertline.x.vertline. and angle .alpha. is again shown to be less than 45.degree..

The purpose for limiting .alpha. to 45.degree. is related to the hardware involved. As the trigonometric sine approaches 90.degree., the resolution in the conversion is greatly diminished. Referring to the table of FIG. 3, the analog sin .alpha. output to A/D converter 24 (of FIG. 1) is shown with a corresponding .alpha. shown in binary and in degrees. The addresses (available in the ROM) are shown in decimal and binary notation, thereby describing the manner in which the ROM is wired according to the preferred embodiment. From the table it can be seen that between 0.degree. and 45.degree. small increments (decrements) of sin .alpha. result in very small increments (decrements) in .alpha.. That is, a one bit (i.e., .039 volt) increment (decrement) in the sin .alpha. output results in a 1/5 to 1/3 of 1.degree. increment (decrement) in .alpha.. On the other hand, examining the extension to the table of FIG. 3 showing .alpha. ranging up to 90.degree., it is readily apparent that small changes in sin .alpha. cause comparatively large changes in .alpha. when .alpha. approaches 90.degree.. Instead of the 1/5 of 1.degree. increment (decrement) in .alpha. per one bit (0.039 volt) increment (decrement) of sin .alpha. in the 0.degree. to 45.degree. range, there is (near 90.degree.) a 3.degree. increment (decrement) per one bit increment (decrement) in sin .alpha.. This loss of resolution creates an unacceptable margin of error among the higher .alpha. values. To overcome the above-described loss of resolution, .alpha. was limited to the range between 0.degree. and 45.degree. by evaluating the sine as the lesser value .vertline.x.vertline./.sqroot.x.sup.2 + y.sup.2 or .vertline.y.vertline./.sqroot.x.sup.2 + y.sup.2. It should, however, be noted that ROM 26 has the capacity to handle a range of from 0.degree. to 85.degree. as seen in FIG. 3. It is for the sake of maximizing resolution that the 45.degree. limit is imposed.

From ROM 26, the binary value of .alpha. is transmitted along two paths. Along the first path, the binary value of .alpha. is sent through an inverter 28 and then an adder 30 wherein the binary equivalent of 90.degree. is added to the inverted value of .alpha.. The output of adder 30 is then (90.degree. - .alpha.). The (90.degree. - .alpha.) signal and the second path of the binary value of .alpha. enter a multiplexer (MUX) 32. MUX 32 receives a third input from voltage comparator 18 which informs MUX 32 of which magnitude input .vertline.x.vertline. or .vertline.y.vertline. is smaller. If .vertline.x.vertline. is smaller, MUX 32 produces a first angle output .alpha.' = .alpha.; if .vertline.y.vertline. is smaller than or equal to .vertline.x.vertline., MUX 32 produces a first angle output .alpha.' = (90.degree. - .alpha.). MUX 32 output .alpha.' thus measures an angle ranging between 0.degree. and 90.degree..

The output of .alpha.' is then fed (as a positive (+) first angle output .alpha.') into another multiplexer (MUX) 34. The .alpha.' output is also fed into an inverter 36 which inverts .alpha.' thereby producing a negative (-) first angle output, - .alpha.', and feeds - .alpha.' as the second input to MUX 34. MUX 34 produces a signal .alpha.' or - .alpha.'. Which of these two values is selected is determined by a multiplex (MUX) control 38. MUX control 38 receives the aforementioned operational sign outputs, SIGN x and SIGN y, from the x and y absolute value circuits 14 and 16, respectively. The values of SIGN x and SIGN y determine in which quadrant the bearing is located. (Referring to FIGS. 2A, 2B, and 2C the quadrants are shown with the first quadrant, I, representing the 12 o'clock to 3 o'clock quadrant; the second quadrant, II, representing 3 to 6; the third quadrant, III, representing 6 to 9; and the fourth quadrant, IV, representing 9 o'clock to 12 o'clock quadrant. This clockwise numbering of the quadrants starting at 12 o'clock corresponds to the normal radar sweep). If SIGN x and SIGN y indicate positive values for x and y, the bearing is "placed" in the first quadrant. If SIGN x indicates a positive x value while SIGN y indicates a negative y value, the bearing is "placed" in the second quadrant. A negative SIGN x and negative SIGN y indication "places" the bearing in the third quadrant. Finally, a negative SIGN x value and a positive SIGN y value indication "places" the bearing in the fourth quadrant.

To "place" the bearing in the proper quadrant the MUX control 38 performs two operations. First, if SIGN x and SIGN y values indicate bearing in the first or third quadrant, MUX 34 has an output equal to .alpha.'; if the bearing is in the second or fourth quadrant, MUX 34 has a - .alpha.' output. The output from MUX 34 enters an adder 40. Second, MUX control 38 also controls another multiplexer 42 which has input wires corresponding to 180.degree. (in binary) and 360.degree. (in binary). MUX control 38 also has a SELECT line which turns ON the 180.degree. wire when a bearing in the second or third quadrant is indicated and turns ON a 360.degree. wire when a fourth quadrant bearing is indicated; an INHIBIT line is also provided which can suppress both the 180.degree. wire and the 360.degree. wire and inhibits the output of MUX 42 when a first quadrant bearing is indicated. The output from MUX 42 (if there is one) enters adder 40 together with the output from MUX 34 to produce a final binary bearing output. This binary bearing output can be fed into a binary-to-BCD converter 44 to be read out on some output display 46.

By way of example, the range and bearing of the X-Y coordinate position shown in FIG. 2C will be determined with reference to the apparatus in FIG. 1. Letting the maximum .vertline.x.vertline. and .vertline.y.vertline. input voltages be +10 volts and, for this example, letting x = -5 .sqroot.3 volts and y = 5 volts, a comparison in voltage comparator 18 of .vertline.x.vertline. and .vertline.y.vertline. indicates that .vertline.y.vertline. < .vertline.x.vertline.. ROM 26, thereafter, finds .alpha. = 30.degree. from Sin.sup..sup.-1 5/.sqroot.[5.sup.2 + 25(3)] = Sin.sup..sup.-1 (1/2). MUX 32, which receives inputs corresponding to .alpha. and (90.degree. - .alpha.), selects the (90.degree. - .alpha.) value as its output due to the signal received by MUX 32 from voltage comparator 18, i.e., .vertline.y.vertline. < .vertline.x.vertline.; .alpha. ' is selected as (90.degree. - 30.degree.) = 60.degree.. At this point, MUX control 38 determines that the bearing is in the fourth quadrant because SIGN x indicates a negative value for x while SIGN y indicates a positive value for y. MUX 32 passes - .alpha.', or - 60.degree., (in binary) to adder 40 while MUX 42 passes 360.degree. (in binary) to adder 40. The output from adder 40 is 360.degree. (in binary) plus minus 60.degree. (in binary) or 300.degree. which an inspection of FIG. 2C verifies.

The elements comprising the present invention are conventional components and integrated circuit (IC) chips available commercially. For example, ROM 26 may be of the INTERSIL IN 5623 CDS type comprising an EJM-1-ROM connected to an EJM-2-ROM. A/D converters may be of the DATEL ADC-EH-1 type while the MUX's may comprise SN 74157 IC chips. MUX control 38 may comprise a simple INVERTER-AND-OR network of elements as shown in FIG. 4.

As previously mentioned the present invention extends beyond the preferred embodiment sine mode and includes trigonometric modes such as the cosine, tangent, and other related angle functions, all of which require only slight modifications which may be readily fashioned once an understanding of the preferred embodiment is acquired. To be sure, the invention using the cosine mode would be only a trivial variation of the described preferred embodiment. Using the tangent function might require more hardware memory to obtain resolution comparable to the sine embodiment and would require a comparison of .vertline.y.vertline. to .vertline.x.vertline. (rather than the less of .vertline.x.vertline. or .vertline.y.vertline. to R); however, the basic features of the present invention would remain unchanged.

The invention further contemplates the adaptation of the circuitry and principles of the present invention in three dimensional applications where height angle may be determined in the manner employed in determining bearing.

The remaining elements comprising the present invention are conventional and well-known in the art.

Various other modifications, adaptations and alterations are, of course, possible in light of the above teachings. Therefore, it should be understood that, within the scope of the appended claims, the invention may be practiced otherwise than as specifically described.