Unmatched Field Effect Transistors Providing Matched Voltage-Controlled Resistances

This invention relates to voltage-controlled resistors and more particularly to unmatched field effect transistors (FET's) providing matched voltage-controlled resistances.

The use of a single FET as a voltage-controlled resistor is described in the article, "FET's As Voltage-Variable Resistors" by Carl D. Todd, Electronic Design, Sept. 13, 1965, pp. 66-69. In such applications, the FET drain-to-source voltage is restricted to be less than the pinch-off voltage such that it operates in the so-called triode region below the knee of the performance characteristics of the FET (I.sub.D vs. V.sub.DS, with V.sub.GS constant). The pinch-off voltage V.sub.GSO may be defined as the gate-to-source voltage that reduces the drain current to 0.01 of its zero bias value, the drain being maintained at a positive potential with respect to the source which is greater than the magnitude of the pinch-off voltage. The FET performance characteristics are generally symmetrical through the origin. The relationship between drain current I.sub.D and drain-to-source V.sub.DS is approximately linear over a limited range of this current and voltage, where the channel pinch-off conditions are not too closely approximated and the gate-to-source channel is reverse biased. Thus, the FET operates in this limited region as a voltage-controlled variable resistor to a small AC signal that is applied across the drain-to-source channel thereof.

A cascaded attenuator using a pair of FET's as variable resistors is described in a Siliconix application note, "FET's As Voltage-Controlled Resistors" by Dave Capella and carrying the date February 1973. The circuit including the cascaded attenuator there is purely resistive, i.e., it does not include any reactive elements. This prior-art attenuator circuit is similar to the circuit in FIG. 1, except that the elements in the boxes 3 and 4 are purely resistive and that it does not include the other resistors in FIG. 1. Although this prior-art attenuator provides a variable resistance which is a function of a control voltage, the resistances provided by individual FET's there are not matched and need not be matched for proper operation of the circuit. More specifically, the FET's do not normally each present the same drain-to-source channel resistance for the same control voltage over a range of control voltages. In a circuit such as in FIG. 1 which includes reactive elements in the boxes 3 and 4, it is desirable that the resistances provided by the FET's be matched, i.e., that each FET present the same drain-to-source resistance for a given control voltage. The matching is necessary in this instance to provide a predictable family of circuit responses by applying the appropriate control voltage. Since the characteristics of FET's vary considerably between units, FET's having similar characteristics must be individually selected for use in such applications. Such a selection process is time consuming and expensive. Although pairs of selected FET's that are matched within 5% over a range of resistances are commercially available, such a matched pair of FET's may cost an order of magnitude more than unmatched FET's.

An object of this invention is the provision of matched voltage-controlled resistors with unmatched FET's.

Matched voltage controlled resistances are provided across the drain-to-source channels of a pair of FET's, each of which has a source of DC control voltage connected across one of its gate-to-source and gate-to-drain channels. One FET has its gate electrode connected to the voltage source through a control resistor and to the one of its source-and-drain electrodes not associated with the voltage source through a feedback resistor. The ones of the FET source-and-drain electrodes which are not associated with the voltage source are preferably capacitively coupled to input and output terminals, respectively. The resistance of the control resistor is adjusted to have a value which causes the net drain-to-source resistance of the one FET to be equal to the net drain-to-source resistance of the other FET for a particular control voltage. These net drain-to-source resistances of the two FET's are closely matched over a range of control voltages.

FIG. 1 is a schematic circuit diagram of an embodiment of this invention;

FIG. 2 is graphs of typical drain-to-source resistances of a pair of unmatched FET's as a function of control voltage V.sub.C ; and

FIG. 3 is graphs of the parallel combination of drain-to-source resistances of the unmatched FET's yielding the curves in FIG. 2 and associated limiting resistors 17 and 18 when the FET's are connected in the embodiment of this invention in FIG. 1.

Referring now to FIG. 1, a circuit embodying this invention comprises input and output ports having one terminals 1A and 2A electrically connected together through impedance elements 3 and 4 and having other terminals 1B and 2B directly electrically connected together. The impedance elements 3 and 4, which are not part of this invention, may each comprise the series combination of an inductor and a resistor in an adjustable filter network embodying this invention. Since the loss in such a filter network is reactive and therefore not the same at all frequencies, it is desirable to present variable resistances between nodes 6 and 7 and nodes 8 and 9, which are closely matched over a range of resistances in order that the network have a predictable loss for an appropriate control voltage. Randomly mismatched variable resistances would not assure that a particular desired response could be achieved at any control voltage. An FET operating in the so-called triode or non-saturation region provides a drain-to-source resistance which varies as a function of a control voltage that is applied to the gate-to-source channel thereof. A pair of FET's have matched drain-to-source resistances where the drain-to-source resistance of one FET is substantially equal to the drain-to-source resistance of the other FET over a range of control voltages.

In accordance with this invention, variable resistances between nodes 6 and 7 and nodes 8 and 9 are provided by the circuit in FIG. 1 comprising a pair of FET's Q1 and Q2 which are shown here for illustrative purposes as N channel devices. Each FET has a source electrode electrically connected to the positive terminal of a source 10 of DC control voltage V.sub.C, has a gate electrode electrically connected through an associated one of the control resistors 11 and 12 to the negative terminal of the DC voltage source, and has a drain electrode electrically connected to its gate electrode through an associated one of the feedback resistors 13 and 14. DC circuits are provided across the drain-to-source channels of Q1 and Q2 by associated resistors 17 and 18. The resistors 11 - 14 reduce distortion in the FET circuits which is caused by the fact that the drain current versus drain-to-source voltage (for constant gate-to-source voltage) characteristics of the FET's are neither perfectly linear in the triode region nor perfectly symmetrical in the first and third quadrants of representations thereof. The resistances of the feedback and control resistors 13 and 11 in conventional circuits are normally quite large, in the order of 500 kilohms. Although these resistors may have the same values of resistance, this is not essential. The resistances of resistors 17 and 18 are preferably much less than that of resistors 11 - 14, e.g., in the order of 4 kilohms. These resistors 17 and 18 limit the maximum value of the net resistance presented between nodes 6 and 7 and nodes 8 and 9, respectively. In order to prevent external circuitry that is connected to input and output terminals from connecting a DC path across nodes 6 and 7 or nodes 8 and 9 and loading the FET circuit, the Q1 and Q2 drain electrodes are preferably capacitively coupled to input terminal 1A and output terminal 2A through DC blocking capacitors 23 and 24, respectively.

Considering only the FET Q1 and associated elements in FIG. 1, for example, the drain-to-source resistance R.sub.DS between the drain and source electrodes of an FET varies as a function of the gate-to-source voltage V.sub.GS thereof and is representable as ##EQU1## where R.sub.DSO is a constant which is the minimum drain-to-source resistance for a gate-to-source voltage of 0 volts, and V.sub.GSO is a constant which is the pinch-off voltage of the FET. The resistors 11, 13, and 17 are essentially electrically connected in series across the DC voltage source 10. Since the resistance of resistor 17 is much less than that of resistors 11 and 13, the voltage drop across the drain-to-source channel of Q1 is very low. This means that the drain electrode of Q1 is essentially at the same potential as its source electrode. The resistors 11 and 13 therefore essentially divide down the DC control voltage V.sub.C of source 10 such that ##EQU2## where R.sub.C represents the resistance of control resistor 11 and R.sub.F represents the resistance of feedback resistor 13. Assuming that resistors 11 and 13 both have the same values of resistance, the gate-to-source voltage of Q1 is representable as

substituting equation (3) in equation (1) reveals that the drain-to-source resistance R.sub.DS of an FET is a function of the control voltage V.sub.C.

For the same type of FET, the constants V.sub.GSO and R.sub.DSO of particular transistors vary greatly from device to device. This causes different FET's of the same type to have different values of drain-to-source resistance R.sub.DS for the same value of control voltage V.sub.C. FIG. 2 is a plot of the drain-to-source resistance R.sub.DS defined by equations (1) and (3) for two different FET's. Curve 25 corresponds to an FET having an R.sub.DSO = 64 ohms and a V.sub.GSO = -2 volts. Curve 26 corresponds to an FET having an R.sub.DSO = 47 ohms and a V.sub.GSO = -3 volts. These curves in FIG. 2 provide an indication of the degree of mismatch between the drain-to-source resistances R.sub.DS of particular FET's of the same type. There is considerable difference between the drain-to-source resistances of these two FET's, particularly for control voltages between -3 volts and -6 volts.

The resistances R.sub.N1 and R.sub.N2 between nodes 7 and 21 and nodes 9 and 22, respectively, are equal to the parallel combinations of particular FET drain-to-source resistances and associated resistances R.sub.P of resistors 17 and 18. In accordance with this invention, the resistance R.sub.C = R12 of control resistor 12 is selected to make the two FET's Q1 and Q2 provide the same resistances R.sub.N1 and R.sub.N2 between nodes 7 and 21 and between nodes 9 and 22 for some value of control voltage V.sub.C. Proper selection of the resistance R12 then yields closely matched values of the resistances R.sub.N1 and R.sub.N2 over a range of control voltages. This result occurs because the proper resistance of resistor 12 causes a particular value of control voltage V.sub.C to present different gate-to-source bias voltages on Q1 and Q2. This effectively causes the curve 26 in FIG. 2, for example, to be shifted to the left until curves 25 and 26 coincide for a particular value of drain-to-source resistance R.sub.DS and control voltage V.sub.C.

The value of the control voltage V.sub.C for which the net resistances R.sub.N1 and R.sub.N2 associated with Q1 and Q2 are the same value may be computed by substituting equation (3) in equation (1), selecting a desired value of the net resistance R.sub.N1 = R.sub.DS1 .vertline..vertline.R.sub.P, and solving for V.sub.C, to obtain the relationship ##EQU3## where R.sub.P = R17 = R18. The required resistance R12 of resistor 12 that is needed to make the resistances R.sub.N1 and R.sub.N2 associated with Q1 and Q2 the same value is computed by substituting equation (2) in equation (1) and solving for the control resistance R.sub.C = R12 to obtain the relationship ##EQU4## where R.sub.P = R17 = R18, and R.sub.F = R14. Combining equations (5) and (6) provides an expression for the desired value of the resistance R12 of resistor 12. In practice, the net resistance R.sub.N1 associated with Q1 is measured and set to a predetermined value by varying the control voltage V.sub.C. The resistance of resistor 12 is then varied to make the net resistance R.sub.N2 associated with Q2 equal to the predetermined value of resistance R.sub.N1 for the corresponding value of control voltage.

The curves 27 and 28 in FIG. 3 are plots of the net resistances R.sub.N1 and R.sub.N2 where the FET devices associated with curves 25 and 26 correspond to the elements Q1 and Q2, respectively, in FIG. 1. The resistances R.sub.P of resistors 17 and 18 in this example are 4 kilohms. The resistance R.sub.C of control resistor 12 is selected here to make the node resistances R.sub.N1 and R.sub.N2 both equal to 700 ohms, which is on the vertical portion of the curves in FIG. 3. The curves 29 and 30 are similar plots of the node resistances R.sub.N1 and R.sub.N2 with the devices related to curves 25 and 26 as being switched, i.e., where the FET element associated with curves 25 and 26 corresponds to Q2 and Q1, respectively. The node resistances R.sub.N1 and R.sub.N2 in FIG. 3 are closely matched over a range of control voltages.