Modulated Passband Signal Generator

This invention relates to data communication apparatus and, more particularly, to apparatus for digitally generating bandpass signals.

Data transmission over voice frequency channels is generally accomplished by modulating a baseband data signal onto a carrier signal, developing thereby a bandpass signal, and then transmitting the modulated signal to a distant receiver wherein the signal is demodulated. The transmitter's modulation process generally includes low pass filtering to insure that the baseband signal is of a finite known bandwidth, modulating onto a carrier by means of any of a variety of modulation schemes, and bandpass filtering to insure that the transmitted signal occupies a finite known frequency band.

With the present trend of semiconductor technology toward large scale integration, a number of attempts have been made to implement the transmitter functions by digital techniques in a fashion that lends itself to integration. In an article entitled "In-Band Generation of Synchronous Linear Data Signals," IEEE Trans. on Comm., Vol. COM 21 No. 10, Oct. 1973, page 1116, Kalet and Weinstein describe a bandpass signal generator employing a finite number of fixed filters which, in combination, develop bandpass signals. In an article entitled, "Microcoded Modem Transmitters," IBM J. Res. Develop., July 1974, pp. 338-351, Choquet et al described a transmitter design employing a digital finite impulse response filter and programmable, cyclically modified, filter coefficients to obtain the desired bandpass signal. Both the Kalet and the Choquet apparatus are useful only when the ratio of the desired carrier frequency to the filters' processing rate is a rational number.

It is an object of this invention to provide a bandpass signal generator which is not limited to rational number ratios of carrier frequencies to a filter's processing rate.

This and other objects are achieved by multiplying a sampled applied input signal by a particularly defined precessing phasor signal and by convolving the product with a fixed low pass filter. More particularly, incoming symbol signals, which may comprise real and imaginary components, are sampled at a preselected rate. The sampled signals are multiplied by a time precessing phasor of unit magnitude, and the complex product signals are applied to a complex low pass filter. The low pass filter convolves the applied complex product signals with a particularly defined fixed impulse response and develops the real part of the convolved signals as the desired bandpass signal.

FIG. 1 depicts a schematic block diagram of a prior art bandpass signal generator;

FIG. 2 illustrates a general block diagram of the signal generator in accordance with the principles of this invention;

FIG. 3 is a block diagram of the generator illustrated in FIG. 2 suitable for signals available in cartesian coordinates;

FIG. 4 depicts the generator illustrated in FIG. 2 suitable for generating Phase Shift Keying modulated signals; and

FIG. 5 is a block diagram of a particular embodiment of element 50 of FIG. 2 which is suitable for implementations which generate Differential Phase Shift Keying modulated signals.

In general, a bandpass signal generated by a data communication transmitter can be represented by ##EQU1## where a.sub.n and b.sub.n are the symbols to be transmitted, h(t) and g(t) are Nyguist pulses, T is a symbol period and .omega..sub.c is the carrier's radian frequency. A Nyguist pulse g(t) is an analog signal having the property g(t-nT) = 0 for t = mT when m .noteq. n, and g(0) = 1.

A more compact representation of equation (1) is obtained by using complex signals. Thus, equation (1) can be represented by ##EQU2## where

and

in accordance with prior art teachings, the z(t) expression of equation (2) can be rewritten as ##EQU3## where .delta.(t-nT) is the standard delta function (.delta.(t)= 0 for all t.noteq.0 and .intg..delta.(t)dt about 0 is 1), and where the symbol "*" designates convolution. A perusal of equation (5) indicates that signal z(t) can be computed by sampling the C.sub.n signals, by convolving the sampled signals in a filter whose impulse response is e.sup.j.sup..omega..sbsp.cnT R(t) e.sup.j.sup..omega..sbsp.ct, and by summing the filter's output signals for all values of n. This is basically the approach taken by Kalet and Choquet as described in the aforementioned articles. From equation (2) it may be seen that the desired bandpass signal is obtained by evaluating the real part of z(t). Accordingly, substituting equations (3) and (4) into equation (5) and taking the real part thereof yields ##EQU4##

Equation (6) indicates that the bandpass signal s(t) may be implemented by combining the output signals of four circuits. In each one of the circuits, a predetermined symbol signal (a.sub.n or b.sub.n) is sampled and is applied to a filter having a predetermined impulse response (e.g., g(t)cos .omega..sub.c (nT+t)). It should be noted that all of the filters specified by equation (6) have an impulse response which is different for different values of n. Therefore, as n changes with time, so must the impulse response of the filters. It can be said, therefore, that implementation of the signal s(t) in accordance with the teachings of equation (6) requires the use of time varying filters.

If .omega..sub.c /2.pi. and T are not related by a rational number, the impulse responses required by equation (6) change in a noncyclical manner. Under such circumstances, the impulse response of the filters must be computed anew for each n=0,1,2, . . . .infin.. Such computations require a substantial amount of hardware. If, on the other hand, .omega..sub.c /2.pi. and T are related by a rational number, then the necessary impulse responses repeat cyclically, permitting the use of impulse responses which are modified by the contents of a read-only-memory.

The cyclical repetition of the required impulse responses is the reason behind the "rational number" requirement of the Kalet and Choquet apparatus mentioned above.

In order to more fully appreciate the improvements comprising this invention, FIG. 1 is presented to illustrate an implementation of a prior art bandpass signal generator characterized by equation (6) and having .omega..sub.c /2.pi. related to T by a rational number. The symbol signals a.sub.n and b.sub.n are applied, in FIG. 1, to samplers 10 and 11, respectively, which may simply comprise controllable analog gates. The output signal of sampler 10 is applied to filters 20 and 21, and the output signal of sampler 11 is applied to filters 22 and 23. Associated with filters 20 and 21 are read-only-memory (ROM) units 30 and 31, respectively. Filter 20 in combination with ROM unit 30 is arranged to possess an impulse response g(t)cos .omega..sub.c (nT+t), which is variable with respect to n under control of ROM unit 30. Filter 21 in combination with ROM unit 31 is arranged to possess an impulse response h(t)cos .omega..sub.c (nT+t), which, as in the filter 20-ROM 30 interconnection, is variable with respect to n and is under control of ROM unit 31. Associated with filters 22 and 23 are ROM units 32 and 33, respectively. As in the filter 20-ROM 30 interconnection, each of filters 22 and 23 with its associated ROM unit possesses an impulse response which is variable with n and which is controlled as to this variability by the associated ROM unit. In accordance with equation (6), filter 22 is arranged to possess an impulse response characterized by h(t)sin .omega..sub.c (nT+t), and filter 23 is arranged to possess an impulse response characterized by g(t)sin .omega..sub.c (nT+t).

Element 40 of FIG. 1 develops the bandpass signal s(t) by arithmetically combining the output signals of filters 20, 21, 22 and 23. More specifically, signal s(t) is developed by summing the output signals of filters 20 and 22 with the negative of the output signals of filters 21 and 22. Element 40 may be an adder/subtractor circuit implemented in accordance with the teachings of I. Flores, The Logic of Computer Arithmetic, Prentice-Hall Inc., 1963, Chapter 4.

As illustrated, the bandpass signal generator implementation of FIG. 1 requires extensive use of read-only-memories. Additionally, the FIG. 1 circuit requires the carrier frequency .omega..sub.c /2.pi. to be related to the symbol period T by a rational number.

These disadvantages have been eliminated in view of the discovery that the z(t) expression of equation (2) may be rewritten as ##EQU5## A perusal of equation (7) reveals that terms which vary with respect to n appear only on the left side of the convolution equation--which defines the applied signal--and not on the right side of the convolution equation--which defines the impulse response of the filter. Therefore, no time varying filters are necessary for developing the z(t) signal of equation (7). However, since the left hand side of equation (7) now has the e.sup.j.sup..omega..sbsp.cnT term, a time variation requirement is introduced on the sampled C.sub.n signals (which are, of course, time varying).

On first blush, it appears that the time variation requirement by the e.sup.j.sup..omega..sbsp.cnT signal of equation (7) is identical to the filters' time variation requirement of equations (5) and (6) and that, therefore, no savings are realized. Upon a closer look, however, it can be seen that it is considerably easier to accurately multiply the C.sub.n values by arbitrary phasors than it is to multiply whose sets of filter coefficients. First, there are fewer values to multiply (C.sub.n signals generally take on only a small set of values), and second, for many applications, the relevant C.sub.n signals lie on a unit circle. With such C.sub.n signals (as will be shown below), multiplication by the phasor e.sup.j.sup..omega..sbsp.cnT takes the form of the simple addition of phase angles.

FIG. 2 is a block diagram of a circuit which in, accordance with the principles of this invention, is capable of developing the complex bandpass signal z(t) as defined by equation (7). In FIG. 2, the complex symbol signals C.sub.n are sampled in sampler 70 and are multiplied in complex multiplier 50 by the time precessing phasor e.sup.j.sup..omega..sbsp.cnT which is increasing in phase with increasing n. If C.sub.n is available in polar coordinates, multiplier 50 may be implemented with an adder which adds the phase angle of each C.sub.n signal to the phase angle .omega..sub.c nT. If C.sub.n is available in cartesian coordinates, multiplier 50 may be implemented with a circuit for converting the applied cartesian coordinate C.sub.n signals to polar coordinate C.sub.n signals. Alternatively, multiplier 50 may comprise a plurality of multipliers for calculating the desired produce signals directly in cartesian coordinates. One embodiment of such a multiplier is described below in reference to FIG. 3.

The multiplied output signals of multiplier 50 of FIG. 2 are applied to filter 60. In accordance with equation (7), filter 60 possesses an impulse response characterized by R(t) e.sup.j.sup..omega..sbsp.ct, where R(t) is as defined by equation (4). Filter 60 may, generally, be a recursive or a nonrecursive filter. Its specific embodiment, however, is dependent on the characteristics of the incoming signal (polar or cartesian) and on the user's preference. When the C.sub.n e.sup.j.sup..omega..sbsp.cnT signal is available in cartesian coordinates, it is generally found easier to perform the filtering process entirely in cartesian coordinates -- particularly since only the real part of the signal z(t) is desired as indicated by equation (2).

To characterize the hardware implementation of equation (7) in cartesian coordinates, it is necessary to substitute equations (3) and (4) into equation (7) and take the real part thereof, yielding ##EQU6##

Equation (8) is similar in format to equation (6) in that both indicate the use of four filters. However, unlike the filters of equation (6), the impulse responses of the filters of equation (8) are not dependent on the variable n, and are therefore time invariant.

FIG. 3 depicts a block diagram schematic for the cartesian coordinate implementation of the FIG. 2 circuit in accordance with equation (8).

In FIG. 3, signals a.sub.n and b.sub.n are sampled at a rate of 1/T by sampling circuits 71 and 72, respectively. Like samplers 10 and 11 of FIG. 1, samplers 71 and 72 may comprise controllable analog gates. The sampled a.sub.n and b.sub.n symbol signals are applied, as in FIG. 2, to multiplier 50 wherein the sampled symbol signals are multiplied by the variable phasor e.sup.j.sup..omega..sbsp.cnT. Within multiplier 50, multiplier unit 51 multiplies the sampled a.sub.n signal by an applied cosine signal, cos .omega..sub.c nT, and multiplier unit 52 multiplies the sampled a.sub.n signal by an applied sine signal, sin .omega..sub.c nT. Similarly with respect to the b.sub.n signal, multiplier unit 53 multiplies the sampled b.sub.n signal by the applied sine signal, sin .omega..sub.c nT, and multiplier unit 54 multiplies the sampled b.sub.n signal by the applied cosine signal, cos .omega..sub.c nT. In subtractor 55, the output signal of multiplier unit 53 is subtracted from the output signal of multiplier unit 51 to develop the signal (a.sub.n cos .omega..sub.c nT-b.sub.n sin .omega..sub.c nT).delta.(t-nT). In adder 56, the output signal of multiplier unit 52 is added to the output signal of multiplier unit 54 to develop the signal (b.sub.n cos .omega..sub.c nT+a.sub.n sin .omega..sub.c nT).delta.(t-nT). The output signals of subtractor 55 and adder 56 are applied to filter block 60.

Within filter 60, the output signal from subtractor 55 is applied to filters 61 and 62 which respectively convolve their input signals with impulse responses g(t)cos .omega..sub.c t and h(t)sin .omega..sub.c t. Similarly, the output signal from adder 56 is applied to filters 63 and 64 which respectively convolve their input signals with impulse responses h(t)cos .omega..sub.c t and g(t)sin .omega..sub.c t. Also within filter 60, the output signals of filters 62, 63 and 64 are subtracted from the output signal of filter 61 in summing network 65, providing thereby an output signal for filter 60 which is equal to the desired signal s(t) of equation (8). Summing network 65 may be implemented in a manner similar to the implementation of network 40 of FIG. 1.

Filters 61-64 may be of any construction. They may be recursive filters or nonrecursive (transversal) filters. In some situations, however, transversal filters are preferable because of their linear phase characteristics and because of their ease of implementation. For example, a transversal filter may simply comprise a shift register with signal taps at every stage of delay, means for multiplying the output signal of each tap by a filter coefficient, and means for adding the multiplied signals. Another advantage of non-recursive filters relates to the case of specifying a selected impulse response. As is well known, a transversal filter may be made to possess a selected impulse response simply by specifying the tap signal multiplication coefficients to be the sampled values of the desired impulse response.

Of course, the sampled values of the desired impulse response are not obtained by sampling the impulse response at the symbol rate of sampling signals a.sub.n and b.sub.n (which is at the rate of 1/T seconds). Rather, the impulse response is sampled at a rate that relates to the digital realization of the bandpass signal s(t) in the digital transversal filters. In accordance with well-known sampling theorems, since the signal s(t) is centered about a carrier .omega..sub.c, the filter realization must proceed at a sampling rate that is at least equal to 2(.omega..sub.c +B) where B is half the bandwidth of s(t). That is the sampling rate which is used to obtain the transversal filters coefficients.

Since the circuit of FIG. 3 implements the expression of equation (8), it can be appreciated that the FIG. 3 circuit is capable of generating signals having the form of equation (1). A number of specific modulation approaches, however, have characteristic forms which may be classified as subsets of equation (1). For example, the familiar expressions for Quadrature Amplitude Modulation (QAM) and Differential Phase Shift Keying modulation (DPSK) can be obtained by letting h(t)=0 in equation (1). Similarly, the expression for Single Sideband modulation may be obtained by lettering b.sub.n = 0. From the above, it may be realized that for specific modulation approaches, the implementation of the FIG. 2 circuit is simpler than shown in FIG. 3. The following are some of the more unusual examples.

A PSK signal can be written as ##EQU7## yielding a signal z(t) equal to ##EQU8## where e.sup.j.sup..phi..sbsp.n defines the signal constellation C.sub.n (on the unit circle). In accordance with equation (7), the z(t) signal of equation (10) may be rewritten, yielding ##EQU9## Interestingly, the phasor multiplication of element 50 degenerates to a simple addition of the angles .phi..sub.n and .omega..sub.c nT.

FIG. 4 is a block diagram of a PSK modulator characterized by equation (11). Contained in multiplication block 50 of FIG. 4 is an adder 57 and a read-only-memory (ROM) 58. Adder 57 sums the symbol signal .phi..sub.n (sampled by sampler 70) with the precessing angle .omega..sub.c nT, and ROM 58, in response to adder 57, develops the sine and cosine values of the summed angle (.phi..sub.n + .omega..sub.c nT) on output leads 41 and 42, respectively.

Since adder 57 sums angles, it must perform the summation in modulo 2.pi.. If ROM 58 contains the sine and cosine tables from 0 to 2.pi. in 2.sup.k memory locations, then adder 57 has to operate in modulo 2.sup.k. This, of course, is not a difficult requirement on adder 57 since all binary adders naturally do add in modulo 2.sup.k, where k is the number of addition stages. Therefore, adder 57 may simply be a binary adder having k addition stages, and ROM 58 may be a memory having 2.sup.k addresses -- storing in these addresses the values of the sine and cosine functions over the range of 0-2.pi.. To those skilled in the art, it will be apparent that in employing a small amount of logic circuitry, various trigonometric relationships of the sine and cosine function may be utilized to reduce the size of ROM 58.

Within filter block 60 of FIG. 4, filter 66 convolves the cosine signal on lead 42 with an impulse response g(t)cos .omega..sub.c t, and filter 67 convolves the sine signal on lead 41 with an impulse response g(t) sin .omega..sub.c t. The output signal of filter 67 is subtracted from the output signal of filter 66 in unit 68, developing thereby an output signal of filter 60. It can be shown that the output signal of unit 68 is equal to the real part of the z(t) of equation (11), which is the desired s(t) signal.

In DPSK Modulation, the transmitted signal has the form of equation (9) but the transmitted symbol is contained in a differential angle .DELTA..phi..sub.n = .phi..sub.n - .phi..sub.n.sub.-1. To obtain the (.phi..sub.n + .omega..sub.c nT) signal required at the input terminal of ROM 58 of FIG. 4, it is only necessary to replace the precessing .omega..sub.c nT signal applied to adder 57 with a fixed .omega..sub.c T signal, and to interpose an accumulator 59, as depicted in FIG. 5, between adder 57 and ROM 58. By applying the symbol signal .DELTA..phi..sub.n to adder 57 together with the fixed .omega..sub.c T signal, the accumulated output signal developed by accumulator 59 is ##EQU10## which is equal to .phi..sub.n + .omega..sub.c nT as required by equation (9).

Interestingly, adder 57 may be simplified for special values of .omega..sub.c nT. In the extreme, if .omega..sub.c T is equal to 2.pi., adder 57 may be completely eliminated since it adds in modulo 2.pi. and is, therefore, insensitive to input signals which equal to 2.pi..