Voltage Compensated Timing Circuit

In the field of high-speed printing devices which are especially suitable for use in connection with electronic business systems, the wire matrix type of printer has come into increasing use. In this type of printer, letters, numbers and symbols are formed from a series of dots produced by the impact of the ends of a plurality of wire elements on record media, most customarily in combination with an ink ribbon which provides the ink needed to produce a mark on the record medium being printed upon.

Customarily each of the individual wire printing elements of a wire matrix printer is driven by a solenoid which is energized when a printing stroke of that wire is required. Since all of the solenoids are normally coupled to a single power supply, and since the number of solenoids driven to produce a print for a particular character or portion of a character may differ substantially from one time to the next, it will be understood that some variation in the voltages applied to the solenoids from the power supply may result. If not corrected in some way, this variation of voltage is likely to result in variation of the energy applied to the wire elements by energization of the solenoids, with the consequence of a non-uniform appearance in the printing on the record medium.

The purpose of the present invention is to provide means for maintaining the energy derived from a solenoid actuation nearly constant when the voltage applied to the solenoid is varied. Broadly speaking, this is accomplished by controlling the duration of time that the circuit applies power to the solenoid.

According to the invention, an electrical circuit comprises a multi-state device having first and second inputs and at least one output, with said output constituting the output for the circuit; input means for applying an input signal to a first one of said inputs of said multi-state device; first and second signal translating devices having a corresponding first electrode of each coupled together and to a reference potential over an impedance, and having a corresponding second electrode of each coupled over an impedance to a source of potential; a third signal translating device having a first electrode coupled to a reference potential, a second electrode coupled to a control electrode of said first signal translating device, and a control electrode coupled to the output of said multi-state device; variable charging means coupled to the control electrode of said first signal translating device, to a source of circuit potential, and to said reference potential; fixed biasing means coupled to a control electrode of said second signal translating device to provide a fixed bias thereto; a fourth signal translating device having a first electrode coupled to a source of potential, a second electrode coupled to a second input of said multi-state device, and a control electrode coupled to the second electrode of the second signal translating device; and time delay means included in the path coupling the output of the multi-state device to the control electrode of the third signal translating device; whereby said multi-state device is caused to assume a first state by application of an input signal to said first input thereof, and is caused to assume a second state by application of a signal to said second input thereof, thereby controlling the pulse width of the output signal of said multi-state device in accordance with the magnitude of the voltage of said source of circuit potential.

One advantage of the present invention is that the energy output of a solenoid or other load is relatively insensitive to supply voltage variations.

Another advantage is that a single voltage sensing means may be used to control a number of identical solenoids or other loads.

A third advantage is that pulse width control of energy applied to solenoids or other loads makes the use of saturated switching drivers feasible, thus reducing power dissipation and circuit complexity of the driver.

An additional advantage is that different circuit energy levels can easily be selected by controlling timing circuit parameters, and time constants and scale factors can be adjusted to compensate for non-linearities of the system.

Finally, good thermal stability of the circuit is achieved by use of a differential amplifier configuration for the voltage sensing means.

It is therefore an object of the invention to provide an improved solenoid operating circuit.

An additional object is to provide an operating circuit capable of accurately controlling the energy derived from a solenoid actuation.

An additional object is to provide means for operating a saturating driver in which the control variable is the duration of the drive time.

Another object is to provide a circuit which provides a timed output pulse that is a function of the applied circuit voltage.

With these and other objects, which will become apparent from the following description, in view, the invention includes certain novel features of construction and combinations of parts, one form or embodiment of which is hereinafter described with reference to the drawing which accompanies and forms a part of this specification.

FIG. 1 is a schematic diagram of a circuit embodying the invention.

FIG. 2 shows a series of wave forms illustrating the relationship between output pulse duration and supply voltage in the circuit of FIG. 1 utilizing various component adjustments.

Referring now to the illustrated embodiment shown in FIG. 1, an input signal having a duration t.sub.2 -t.sub.1 is applied to one input 8 of a NAND gate 10, the output of which is applied to one input of a second NAND gate 12, the two NAND gates 10, 12 together forming a latch. The remaining input of the NAND gate 12 is connected to a circuit node 14. One circuit branch extends from the node 14 through a resistor 16 to a base reference potential, shown here as ground, while a second branch extends through a resistor 18 to the collector of a PNP-type transistor 20.

The output of the NAND gate 12 is connected to a second input of the first NAND gate 10, as well as being connected to an output terminal 22, and to a conductor 24, which in turn is connected to one end of a resistor 26. At its other end, the resistor 26 is connected through parallel combination of a resistor 28 and a capacitor 30 to a base reference potential, shown as ground, as well as to the base electrode of an NPN-type transistor 32, having its emitter connected to said base reference potential.

The collector of the transistor 32 is connected through a resistor 34, a node 36, a resistor 38, a variable resistor 40, a node 42 and a resistor 44 to a source 46 of supply potential. From the node 42, a first path extends through a resistor 48 to base reference potential or ground, and a second path extends through a resistor 50 to a switch 52, one side of which is connected to base reference potential or ground, and the other side of which is open.

From the node 36, a first path extends through a capacitor 54 to base reference potential, or ground, and a second path extends to the base of an NPN transistor 56, having its emitter connected over a resistor 58 to base reference potential, or ground, and also being coupled to the emitter of an NPN transistor 60. The collector of the transistor 56 is connected through a resistor 62 to the source 46 of supply potential. Similarly, the collector of the transistor 60 is connected through a node 64 and a resistor 66 to the source 46. The base of the transistor 60 is biased to a reference voltage of 4.6 volts by a voltage divider path extending from the source 46 through a resistor 68, a node 70, a variable resistor 72 connected to the base of the transistor 60, and a resistor 74, to base reference potential, or ground. The node 70 is connected through a 5.6 voltage zener diode 76 to base reference potential, or ground.

The emitter-coupled transistors 56 and 60 function as a differential amplifier for comparing the capacitor voltage of capacitor 54 applied to the base of the transistor 56 with the bias voltage applied to the base of the transistor 60. Connection of the base of the driver transistor 20 to the node 64 in the collector circuit of transistor 60 provides control of said driver transistor in accordance with the condition of the capacitor 54.

In operation, a low-going input signal, such as the signal 78 shown in FIG. 1, typically having a duration of two microseconds, is applied to the input 8 of the NAND gate 10. This sets the NAND gate latch 10, 12, causing the output signal, such as the signal 80 shown in FIG. 1, to go low, and causes the timing circuit of FIG. 1 to commence operation.

The output signal 80, shown in FIG. 1 as having a duration of 700 microseconds, indicated as the difference between t.sub.3 and t.sub.1, normally will be applied through additional circuitry (not shown) to energize a matrix print wire solenoid, although it is obviously also susceptible of other uses.

When the pulse 80 goes low as a result of the input pulse 78, this signal is applied over the conductor 24 and a time delay network comprising the resistors 26, 28 and the capacitor 30 to the base of the transistor 32, turning off said transistor. The time delay caused by the time delay network during this phase of circuit operation is insignificant.

Termination of conduction of the transistor 32 causes the capacitor 54 to be charged by the resistive network which includes resistors 38, 40, 44 and 48, as well as resistor 50 when the switch 52 is positioned appropriately. After a time period which is dependent upon the voltage at the source 46 and the resistance values of the resistive network previously mentioned, the voltage on the capacitor 54 reaches the reference voltage placed on the base of the transistor 60, the transistor 56 begins to conduct, and captures the emitter current from the transistor 60, causing it to be turned off.

Since the base current for the transistor 20 is supplied through the transistor 60, its turning off causes the transistor 20 also to be turned off, from its saturated state of conduction. This allows the resistor 16 to pull down the input of the NAND gate 12 of the latch, which forces the output voltage high (as at time t.sub.3) and resets the latch, terminating the output pulse 80. The transition to the higher level of the output signal is transmitted through the conductor 24, and the time delay network comprising the resistors 26, 28 and the capacitor 30, to the base of the transistor 32. After a time delay of approximately 2.5 microseconds, the transistor 32 is turned on, which causes the discharge of the capacitor 54 through the resistor 34. The time delay is provided to assure that the capacitor 54 can charge to a potential slightly beyond the actual turn-on threshold of the transistor 56, which provides more than the minimum base current required for conduction to the base of the transistor 56 and assures the turning off of the transistor 60. Also this time delay assures that the latch has ample time to reset.

In the illustrated embodiment, the discharge of the capacitor 30 is 99% accomplished in 25 milliseconds. The transistor 56 turns off, the transistors 60 and 20 turn on, with transistor 20 going to a saturated condition, and the circuit is now ready for another input pulse 78.

Movement of the switch 52 from one contact to the other changes the time required to charge the capacitor 54. In this manner, the output energy of the solenoid operated by the output pulse 80 can be set at two different levels.

With the switch 52 open, and a reference voltage at the base of the transistor 60 of 4.6 volts, the output pulse has a duration T.sub.on given by the expression: ##EQU1## in which V equals the circuit supply voltage at source 46 and the terms "R" and "C" followed by numbers represent the resistance and capacitance values of the respective resistors and capacitor bearing corresponding reference characters in FIG. 1.

With the switch 52 closed, and a reference voltage at the base of the transistor 60 of 4.6 volts, the output pulse 80 has a duration T.sub.on given by the expression: ##EQU2## in which V equals the circuit supply voltage at source 46 and the terms "R" and "C" followed by numbers represent the resistance and capacitance values of the respective resistors and capacitor bearing corresponding reference characters in FIG. 1.

FIG. 2 shows the relationship between supply voltage and output pulse duration in the illustrated embodiment for various settings of the adjustable resistor 40, with switch 52 in both positions for each value of resistor 40. The versatility of the present circuit is thus clearly demonstrated.

Presented below are component values for the various circuit components included in the illustrated embodiment of FIG. 1. It will, of course, be recognized that these values are merely exemplary, and that the selection of other component values to achieve desired circuit parameters would be well within the ability of one skilled in the art.

Although the invention has been described and illustrates in detail, it is to be clearly understood that the same is by way of illustration and example only, and is not to be taken by way of limitation, the spirit and scope of the invention being limited only by the terms of the appended claims.