Data Acquisition and Transfer System

The present invention relates to a digital data communication system and more particularly to a digital data communication system using a self-clocking technique for transmitting and receiving data over a single coaxial cable.

The present invention provides for a self-clocking asynchronous digital data communication system wherein each bit of any data stream is divided into four time periods. The incoming data is converted from parallel to serial data and by means of the four time periods and logic circuitry the data is coded along with the clock signal to provide a self-clocking continuous stream of data which can be received and decoded at a remote receiver.

Accordingly, an object of the present invention is the provision of a data acquisition and transfer system wherein transmitters may send data of any word length.

Another object of the invention is the provision of a data acquisition and transfer system wherein only one transmission line is required for each remote transmitter.

Another object of the invention is the provision of a data acquisition and transfer system wherein the receiver can accept any word length although different from any of a plurality of transmitters.

Still another object of the invention is to provide a data acquisition and transfer system wherein the system is completely automatic requiring no manual operation.

Other objects and many of the attendant advantages of this invention will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings

FIG. 1 is a schematic diagram of the transmitter for the data communication system;

FIG. 2 is a schematic diagram of the receiver for the data communication system;

FIG. 3 is a schematic diagram of the distribution system for the data communication system; and

FIG. 4 shows the transmit and receive timing signals.

Referring now to FIG. 1 wherein is shown in schematic diagram form a transmitter for the data communication system. Data is received in parallel form in parallel to serial register 10. The data is clocked out of parallel to serial shift registers 10 in serial form to data encoder 14 by means of clocking circuit 12 and shift load control 16. At the end of a data word, shift load control 16 disables the data outputs and prevents data transmission until a new data word is loaded into parallel to serial register 10. The encoded data is loaded into line driver 18 for transmission to the receiver.

Clock oscillator 20 provides a series of clock pulses that are fed to flip-flops 22 and 24 which are connected to provide the four timing pulses (shown in FIG. 4). Flip-flops 22 and 24 provide output sequence for control timing as follows:

At time t.sub.0, control flip-flop 26 is set, generating a high level which is required at the start of each bit time. The serial output of parallel to serial shift registers 28, 30, 32 and 34, is shifted to the right and the first bit of register 34 is gated into flip-flop 25 by time pulse t.sub.0. Data encoder gate 27 will set the input condition so that flip-flop 26 will be reset at t.sub.1 if the data is a "0" or reset at t.sub.3 if the data is a "1". Control flip-flop 26 is therefore reset in either case at time t.sub.3 and generates a low level which is required at the stop of each bit time period. The time t.sub.0 signal is used to shift the data through parallel to serial shift register 10 so that the next bit is ready for control gate 27 function.

In the illustrated embodiment shown, a counter (flip-flops 36, 38, 40, and 42) counts data bits until the count equals the number of bits in the data word. At this time a high appears at the output of gate 44 which enables flip-flop 46 to toggle providing a disabling gate to data output gate 48. Data output gate 48 will remain disabled until the next time t.sub.0, thus allowing a low level output for one bit period (t.sub.0 -t.sub.3) as an end of word indication. During this period of "dead time" the parallel to serial register 10 is placed in the parallel load mode and the rise of the time t.sub.0 signal loads a new data word.

Transmission of data is continuous as the shifting process repeats, producing a stream of self-clocked data words with a one data period of space between each word.

As shown in FIG. 4 each bit of the data stream is divided into four time periods labeled t.sub.0 through t.sub.3. The upper two waveforms labeled "0 data bits" and "1 data bits", respectively. As shown the signal is high at time t.sub.0 and low at time t.sub.3 for both "0" and "1" bits. These time periods are used for bit synchronization, but not for transmission of data. Time periods t.sub.1 to t.sub.2 carry data bit information. The level that exists on the transmission line at the start of the time period t.sub.2 carry data bit information. The level that exists on the transmission line at the start of time period t.sub.2, the mid-point of the data bit time, is strobed into the receiving shift register (FIG. 3). The data bit stream shown by the bottom waveform indicates that in its series of "0" and "1" data bits can be transmitted with each bit start indicated by a high transition and stop indicated by low transition with the data itself midway between.

The signal out of line driver 18 (FIG. 1) at terminal Z is fed to one input of the multiplexer 50 of the receiver shown in FIG. 2. One receiver is required for each central location. The number of remote transmitters will determine the number of inputs required to multiplexer 50. In the embodiment shown there are four inputs labeled 7, L, M, and N. The serial data received from the transmitters terminate at the inputs to multiplexer 50. The output signal from multiplexer 50 depends upon the address of the data coming in. The output from multiplexer gate 52 is fed straight through to output terminal J, to flip-flop 54 of information detector 56 and to gate 58 of start pulse detector 60. The data fed to output terminal J is fed directly to the serial shift registers 62 through 68 (FIG. 3) where it is converted from serial to parallel information. Information detector 56 is for determining the center of the bit pulse for providing the clocking signal to the serial registers (62-68) of FIG. 3. Detector circuit 56 is enabled when the time pulse t.sub.0 of the incoming bit pulse is received at flip-flop 54. Gate 35 is enabled and allows a stream of clock pulses from free-running clock 37 to counter 39. The count of one-half of the bit pulse is decoded in gate 41 and fed to the clock input terminals of shift registers 62 through 68 (FIG. 3). This enters the data that is at the input of register 62 and also shifts the stored memory (shift registers 62-68) by one place. This clock pulse also resets flip-flop 54 and detector 56 then waits for another t.sub.0.

The purpose of start pulse detector 60 is to determine when a valid word is located in the shift register that is being addressed (FIG. 3). The incoming data from multiplexer 50 is differentiated by means of flip-flop 43 and an exclusive OR gate 58 to produce a pulse that occurs when the data changes state which is set at t.sub.0 and t.sub.1 or t.sub.3 or during normal data transmission, the time between these pulses always resets counter 45 before it reaches a preset count. This count determines when a start pulse has occurred. When the time between two pulses is long compared to the time required to count to the preset number, a start pulse has occurred and the next bit after this start pulse is the first bit of the word. Therefore the next start pulse detected will indicate a valid word is present in the shift register and is ready to be loaded into the latches (70 through 76) FIG. 3. When an output occurs at counter 45, this is the indication of a start pulse. This indication is fed to the circuitry that will give an output pulse when the second start pulse is received for each word. The logic function is performed by flip-flop 47, gate 49, inverter 51, flip-flop 53, gate 55, and inverter 57 with the output at inverter 57. The output pulse from inverter 57 is fed to the multiplexer 59 to the correct set of latches shown in FIG. 3 for storage. Multiplexer 50 and demultiplexer 59 are addressed by the input-output control counter 61 and is incremented by 1 for every output of the start pulse detector. In this example there are four addresses.

In the embodiment shown the system provides for four transmitters, one receiver, and four shift registers and latches. There can be more or less transmitters by expanding or detecting the circuitry of the input-output central in the receiver, multiplexer and demultiplexer.

The transmitter samples data (1s or 0s) at their own rate. There is no synchronization between any transmitter. The self-clocking code is sent by coaxial cable, twister pair or fiber optics to the receiver.

The receiver samples each transmitter word separately until a full word is received and sent to the proper latches for storage. All shift registers receive the same information, only the latches associated with the transmitter selected by the input-output control are strobed for storage. Therefore the latches store the information in the same format that was received at the input to the transmitter.

Obviously many modifications and variations of the present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described.