US 4,013,896 AGrant

High-Speed Logic Gate With Two Complementary Transistors and Saturable Resistors

Issue Date:1977-03-22

•6 Claims

•6 Drawing Sheets

Abstract

A novel high-speed logic gate of compact design, having low energy consumption comprises a plurality of components each constituted by two complementary transistors and saturable resistors integrated upon one in the same substrate. The base of the first transistor has for its base a portion of the collector of a second transistor, and for its collector the base of the second transistor. The second transistor has its base diffused into its emitter into its base.

Metadata

Assignee

Thomson-CSF

Inventors

Jean-Edgar Picquendar
Pham Ngu Tung

Application Information

Application Number:US 6226116

Filing Date:1975-10-15

Priority Date:1974-10-18

Art Unit:254

Classifications

IPC:

H03K 1908H03K 1940H03K 1934

Field of Search:

307255;284;288;304;215;214;213;205

Patent Drawings (6 sheets)

Description

The gates used in logic circuits have characteristics which are matched to said logic circuits. It is often difficult to match them to other logic circuits.

Moreover, the majority of the known gates are bulky, dissipate too much power and often have too low a switching speed.

The object of the present invention is a novel family of gates utilising the component which formed the object of a copending Patent Application under Ser. No. 572,918.

The gate in accordance with the invention comprises at least one component of the aforementioned type, in which one of the electrodes in the terminal zones thereof is at a fixed potential, whilst the other is connected either to a fixed voltage source or earthed across a saturable resistor.

The invention will be better understood from a consideration of the ensuing description given with reference to the attached drawings in which:

FIG. 1 illustrates the diagram of a first embodiment of the invention;

FIG. 2 is an explanatory graph;

FIG. 3 is a plan view of the integrated circuit whose equivalent circuit diagram is shown in FIG. 1;

FIG. 4 illustrates the diagram of a second embodiment;

FIGS. 5 and 6 are sets of explanatory graphs;

FIG. 7 is the integration diagram of the device shown in FIG. 4;

FIG. 8 is a variant embodiment of the device shown in FIG. 4;

FIG. 9 is a diagram of a third embodiment;

FIG. 10 is the integration diagram of the device shown in FIG. 9.

FIG. 1 illustrates a component of the kind described in the aforementioned Patent Application, which comprises two complementary pnp and npn transistors and which will be designated hereinafter by the initials TT. This component has three input electrodes, the grounded input M (emitter of the pnp transistor), the input E (collector of the npn transistor) and the input S (base of the npn transistor). The input E is connected across a field-effect transistor REC, whose source and drain are connected together, to the address input to which a two level V.sub.AD voltage is applied.

The successive layers of the component TT have the indicated polarities and the voltage V.sub.AD can acquire two negative levels, one of small absolute value, substantially equal to 0, the other of the order of -1.5 v.

If V.sub.AD is sufficiently high in terms of absolute value, the pnp and npn transistors go conductive.

The potential difference V.sub.S - V.sub.E for the components TT of the kind disclosed in the indicated Patent Application, is of the order of 0.5 v. V.sub.S is of the order of V.sub.M i.e. -0.1 v; or of the order of -0.1 v.

FIG. 2 plots I.sub.E as a function of V.sub.AD. The graph I represents the current in the component REC which behaves as a saturable resistor. The graph II illustrates the current I.sub.E at the point E, coming from the component TT. The equilibrium current is given by the intersection between the two graphs. The addressing voltages are therefore such that V.sub.AD < V.sub.S - 0.5. If V.sub.S is between -0.1 and 1 v., then V.sub.AD must be smaller than 1.6 v.

In FIG. 3, the gate has a size of 5 .times. 5 microns square. The function of REC is to limit the input current I.sub.E which must nevertheless be sufficient to cause the unit to change from the blocked to the conductive state.

The values of the currents in one or the other of the two states of the gate can be summarised as follows:

FIG. 4 illustrates a power inverter gate. It comprises two components TT.sub.1, TT.sub.2. The input terminal E.sub.1 of the component TT.sub.1 is supplied across a saturable resistor REC.sub.1 with an address voltage having two levels -0.1 v or -1.6 v. The terminal S.sub.1 is connected across three series-connected diodes D.sub.1, D.sub.2, D.sub.3, to the terminal S.sub.2 of the component TT.sub.2. This terminal S.sub.2 is connected by a saturable resistor to a voltage source producing -2.5 v. The component TT.sub.2 has a terminal M.sub.2 which is the output terminal of the system and a terminal S at the potential -1.7 v. The terminal M.sub.2 is earthed across a saturable resistor REC.sub.4. The terminal S.sub.1 is earthed across a saturable resistor REC.sub.3. The terminal M.sub.1 is earthed.

The operation of the system is as follows:

The potential difference V.sub.S1 - V.sub.S2 is constant and depends upon the potential drop across the terminals of the set of three diodes, which is of the order of 1.5 v when these are conducting. In other words, V.sub.S1 and V.sub.S2 are substantially constant whatever the state of the system. Thus (FIGS. 5 and 6) the resistor REC.sub.2 will have the same characteristic.

When the component TT.sub.1 is blocked (zero address voltage) the potential at S.sub.2 is given by the point of intersection between the characteristics of REC.sub.3 and REC.sub.2 (FIG. 5). The potential at S.sub.1 is equal to -2.4 + 1.5 v = 0.9 v.

When the component TT.sub.1 is conductive, the potential at S.sub.1 is close to earth potential, namely -0.1 v. The potential at S.sub.2 is equal to -0.1 v -1.5 v = -1.6 v.

In the first case, the component TT.sub.1 is conductive. In the second case, it is blocked.

The various voltages are summarised in the following table:

The high state can be used for the addressing of storage cells.

When these cells are addressed, and if they number n, then if E is the current drawn by each cell the following condition must obtain:

however

However .beta..sub.2 .congruent.10

and .beta. = IS.sub.1 /I.sub.E1

It is simply necessary to make 10 I.sub.S1 /E > n

FIG. 7 illustrates a plan view of the integration diagram of the gate. Its dimensions are 12 .times. 24 microns square. The maximum current drawn at the input is 15 microamps at -1.6 v. The maximum internal consumption is 15 microamps.

From this gate, it is possible to derive a NOR-gate having as many inputs as required. FIG. 8 illustrates a NOR-gate with five inputs. In this figure, the component TT.sub.1 is replaced by five components TT.sub.11 to TT.sub.15 arranged in parallel across the terminal M.sub.1 and connected to address inputs respectively across saturable resistors REC.sub.11 to REC.sub.15.

FIG. 9 illustrates a write-in inverter gate. This gate has three components TT.sub.1, TT.sub.2, TT.sub.3.

The terminal E.sub.1 of the component TT.sub.1 is connected across a saturable resistor REC.sub.1 to a generator producing the signal (not shown). This signal is a voltage having two negative levels which can acquire one value close to 0 v., the 0 state, and another, lower value, of the order of -1 v., the 1 state. The terminal of transistor TT.sub.1 is earthed. The terminal S.sub.1 is connected to a source producing a negative voltage of the order of -1.7 v., through the medium of two diodes D.sub.1 and D.sub.2 connected in series in the forward direction from earth to the negative voltages, and of a saturable resistor REC.sub.2.

The component TT.sub.3 has its terminal M.sub.3 earthed, its input E.sub.3 being connected to the input E.sub.2 ; a resistor REC.sub.4 is connected between M.sub.3 and the collector of the first transistor of TT, its terminal S.sub.3, which latter is the output terminal of the system. The component TT.sub.2 has its terminal M taken to S.sub.3, its terminal S.sub.2 placed at -1.1 v and its terminal E.sub.2 taken to the input of the load resistor REC.sub.2.

The operation of the system is as follows:

a. With the input E.sub.1 in the 0 state, the component TT.sub.1 is blocked. E.sub.1 and E.sub.3 being at the same potential and the transistor TT.sub.3 likewise, the component TT.sub.2 is conductive and S.sub.3 is at a potential of around 1 v.

b. The input E.sub.1 is in the 1 state and the transistor TT.sub.1 is conductive as also is the component TT.sub.3. The output S.sub.3, or the output of the system, is virtually at earth potential. The transistor TT.sub.2 is blocked.

The integration diagram of the system shown in FIG. 9 has been illustrated in FIG. 10.

Claims

What we claim is:

1. A logic gate comprising: first and second solid state components, each component comprising first and second complementary transistors integrated upon one and the same substrate and having respective emitters, bases and collectors, the first transistor having for its base a portion of the collector of said second transistor, and for its collector, the base of said second transistor, said second transistor having its base diffused into its collector, and its emitter into its base, said components having each a first, a second and a third terminal, connected respectively to the emitter of said first transistor, to the base of said second transistor and to the emitter of said second transistor, said first terminals having first connections to ground, said second terminal of said first component having a second connection to ground, and a fixed voltage dropper for connection to the second terminal of said second component, means for connecting a two level voltage to said third terminal of said first component, and second and third connections for connecting to fixed d.c. voltages said second and said third terminal of said second component.

2. A gate as claimed in claim 1, wherein said first terminal of said first component is directly connected to ground, a first saturable resistor connecting said second component to first terminal to ground.

3. A gate as claimed in claim 2, wherein a second saturable resistor connects said second terminal of said first component to said two level voltage source, a third saturable resistor connects the third terminal of said first component to ground, and a fourth saturable resistor connects said third terminal of said second component to said first d.c. source.

4. A gate as claimed in claim 3, wherein said saturable resistors are field effect transistors having interconnected drains and sources respectively.

5. A gate as claimed in claim 4, comprising a plurality of first components having their first and third terminals connected respectively in parallel, and their second terminals connected respectively to two level voltage sources.

6. A gate as claimed in claim 4, further comprising a third component identical to the first and said second component, having its first terminal grounded, its second terminal bridge connected between the first terminal of said second component and ground, the connection to the ground comprising a saturable resistor, and its third terminal connected to the first terminal of said first component.

Patent Citations (6)

Patent	Date	Inventor
US3302041	1967-01-01	Poston
US3376431	1968-04-01	Merrell
US3456131	1969-07-01	Adem
US3508081	1970-04-01	Matsuda
US3660687	1972-05-01	Sahm et al.
US3891866	1975-06-01	Okuhara et al.

Abstract

Description

The gates used in logic circuits have characteristics which are matched to said logic circuits. It is often difficult to match them to other logic circuits.

Moreover, the majority of the known gates are bulky, dissipate too much power and often have too low a switching speed.

The object of the present invention is a novel family of gates utilising the component which formed the object of a copending Patent Application under Ser. No. 572,918.

The invention will be better understood from a consideration of the ensuing description given with reference to the attached drawings in which:

FIG. 1 illustrates the diagram of a first embodiment of the invention;

FIG. 2 is an explanatory graph;

FIG. 3 is a plan view of the integrated circuit whose equivalent circuit diagram is shown in FIG. 1;

FIG. 4 illustrates the diagram of a second embodiment;

FIGS. 5 and 6 are sets of explanatory graphs;

FIG. 7 is the integration diagram of the device shown in FIG. 4;

FIG. 8 is a variant embodiment of the device shown in FIG. 4;

FIG. 9 is a diagram of a third embodiment;

FIG. 10 is the integration diagram of the device shown in FIG. 9.

If V.sub.AD is sufficiently high in terms of absolute value, the pnp and npn transistors go conductive.

The values of the currents in one or the other of the two states of the gate can be summarised as follows:

The operation of the system is as follows:

When the component TT.sub.1 is conductive, the potential at S.sub.1 is close to earth potential, namely -0.1 v. The potential at S.sub.2 is equal to -0.1 v -1.5 v = -1.6 v.

In the first case, the component TT.sub.1 is conductive. In the second case, it is blocked.

The various voltages are summarised in the following table:

The high state can be used for the addressing of storage cells.

When these cells are addressed, and if they number n, then if E is the current drawn by each cell the following condition must obtain:

however

However .beta..sub.2 .congruent.10

and .beta. = IS.sub.1 /I.sub.E1

It is simply necessary to make 10 I.sub.S1 /E > n

FIG. 9 illustrates a write-in inverter gate. This gate has three components TT.sub.1, TT.sub.2, TT.sub.3.

The operation of the system is as follows:

The integration diagram of the system shown in FIG. 9 has been illustrated in FIG. 10.

Claims

What we claim is:

4. A gate as claimed in claim 3, wherein said saturable resistors are field effect transistors having interconnected drains and sources respectively.

Patent

Date

Inventor

Cited By

US3302041

1967-01-01

Poston

US3376431

1968-04-01

Merrell

US3456131

1969-07-01

Adem

US3508081

1970-04-01

Matsuda

US3660687

1972-05-01

Sahm et al.

US3891866

1975-06-01

Okuhara et al.