Manual Override Using a Variable Clock Frequency in a Control System Employing a D/a Converter to Translate Digital Control Signals From a Digital Computer to Analog Signals for Operating Process Control Devices

1. Field of the Invention

The present invention relates to digital-to-analog converters. More specifically, the present invention is directed to a digital-to-analog converter having a variable speed incrementation of a converter output signal.

2. Description of the Prior Art

Digital-to-analog converters are well-known in the art and are widely used in contemporary process control systems to translate digital control signals from a digital computer to analog signals for operating process control devices, e.g., valves. However, it is often desired to manually override a computer control directive by an operator located at the field mounted analog control device. Such a situation may arise from a failure of the remote digital computer to correctly control the analog device due to an equipment failure. Further, it often necessary for an operator to make rapid gross adjustments of the analog device upon the discovery of the need to override the computer control. Such gross adjustments are ultimately not needed as the final desired analog control value is approached. Accordingly, a reduction in the speed of incrementation must be provided following the gross adjustment period. Such a variable speed analog signal incrementation will allow an operator to rapidly achieve a desired analog signal value with gross changes while preventing overshoot as the desired value is ultimately attained with a fine analog signal changes. A prior art system for achieving a variable speed of an analog output signal is shown in U.S. Pat. No. 3,826,991 of James A. Hogan. However, this prior art system has a continuously varying output signal which is difficult to control by an operator where small changes are desired and it is not directly applicable to a digital control system inasmuch as the varying output signal is generated as an analog signal to be summed with another fixed analog control signal.

An object of the present invention is to provide an improved digital-to-analog signal converter circuit having a variable speed incrementation control for the converter analog output signal.

In accomplishing this and other objects, there has been provided, in accordance with the present invention, a variable speed analog signal incrementation circuit having a variable frequency pulse generator for selectively incrementing a stored digital word wherein the stored digital word is arranged to be applied as an input signal to a digital-to-analog converter. The variable frequency generator includes a first means for subdividing a fixed clock frequency signal into a plurality of differing predetermined frequency output signals and a second means for selectively connecting in succession each of the subdivided frequency output signals to the stored digital word to increment the digital word at a corresponding speed. A reset operation of the second means is selectively controlled to produce a restoration of a selection of a predetermined one of the subdivided frequency output signals.

A better understanding of the present invention may be had when the following detailed description is read in connection with the accompanying drawing, in which the single FIGURE is a block diagram of a variable frequency analog control circuit embodying the present invention.

Referring to the single FIGURE drawing in more detail, there is shown a variable speed analog signal incrementation control circuit having a variable frequency clock generator 2 for supplying a selectively variable frequency signal to a first counter circuit 4. The first counter 4 is, also, connected to a communication link, or data highway, to receive signals from a remote digital controller, or processor, 6 which is used to provide a digital output signal controlling an analog process variable, e.g., valve position. The count stored in the first counter 4 is applied to a digital-to-analog converter 8, hereinafter referred to as D/A converter 8, to be converted into an analog signal for controlling an analog process control device 10. The variable frequency clock generator 2 includes a fixed frequency clock circuit 12. An output signal from the clock circuit 12 is applied to a second counter 14 to be counted thereby. The counter 14 is effective to provide separate output signals on four respective output lines 16, 18, 20 and 22. The output signals on the output lines 16 to 22 represent a plurality of subdivided frequencies derived from the fixed frequency supplied by the clock circuit 12. Each of the output lines 16 to 22 is connected as one input to a respective one of a plurality of two-input AND gates 24, 26, 28 and 30 to apply a first input signal thereto. The outputs of the AND gates 24 to 30 are connected to a four-input OR gate 32. The output of the OR gate 32 is connected to the first counter 4 to supply a signal to be counted thereby.

A second input signal for each of the AND gates 24 to 30 is derived from a third counter 34 arranged to count a fifth subdivided frequency output signal from the first counter 14 which fifth output signal is selectively applied to the third counter 34 as hereinafter described. The third counter 34 is a two-stage counter having two output lines 36 and 38. The output lines 36 and 38 are connected to a plurality of gate circuits 40, 42, 44, 46 and 43 to form a decoder for the count stored in the third counter 34 wherein the four possible count states of the two-stage counter 34 are decoded into four output signals. These four output signals are applied to respective ones of the first-mentioned AND gates 24 to 30 as second input signals thereto. Additionally, a fifth output from the third counter 34, also representing one of the four count states, is applied as a first input to an AND gate 50 interposed between the first counter 14 and the second counter 34. A second input for the AND gate 50 is the aforesaid fifth subdivided frequency output signal from the second counter 14 on a fifth output line 51.

A pair of manual switches 52 and 54 are provided for controlling the "reset" operation of the third counter 34 and for applying a control signal to the first counter 4 to initiate a counting operation from the variable frequency clock generator. An input signal for both of these switches 52 and 54 is obtained from a positive source +V. The output signal from the first switch 52 is applied as a first input signal to an AND gate 56 and as a control signal to the first counter 4. The output signal from the second switch 54 is applied as a second input signal to the AND gate 56. The output signal from the AND gate 56 is applied at a "reset" signal to the third counter 34.

In operation, the variable speed analog signal incrementation control circuit of the present invention is effective to provide a means for increasing the rate of the change in the analog output signal from the D/A converter 8 in sequential steps and to initiate selectively a lower rate of increase of the analog output signal when desired by an operator.

Specifically, the variable speed analog signal incrementation circuit of the present invention is used by an operator to manually vary the output current signal of the D/A converter 8 for controlling the analog process control element 10. The variable speed incrementation circuit provides a means for varying this output current from an initial slow rate of change to an increasing incrementation rate by a sequential progression to facilitate the ease and speed of adjustment by the operator of the analog output current from the D/A converter 8. The variable frequency generator circuit 2 generates variable frequency pulses which are applied to the serial-to-parallel counter 4 to increment, i.e., to change, the digital word stored therein from the digital controller 6. If the desired output current value from the D/A converter 8 is grossly dissimilar from the initial output current setting then a rapid, or high speed, incrementation of this initial current value is desired in order to expedite the arrival of the output current signal at the desired value. The illustrated variable speed incrementation circuit has an increasing frequency verses time relationship which accelerates the change in the output current from the D/A converter 8. When the desired output current signal from the D/A converter 8 is approached, the variable incrementation circuit of the present invention is manually restored to a slow speed, or low frequency, operation and, finally, is manually inactivated when the desired output current signal from the D/A converter 8 is reached. In the embodiment shown in the single FIGURE drawing, the variable frequency generating circuit 2 has a capability of operating at four successive and different speeds, or frequencies, which could be expanded to more than four speeds or decreased to less than four speeds. Further, the variable frequency generating circuit 2 could be rearranged by simply using control signals from different portions of the frequency dividing counter 14 to provide either a decreasing speed of operation or a periodically increasing and decreasing speed of operation. Thus, when both of the switches 52 and 54 are closed by an operator, the output signal from the variable frequency clock generator 2 circuit is progressively increased in sequential steps to a higher frequency. Specifically, when the switches 52 and 54 are closed, both of the input signals to the AND gate 56 are high level signals from the source +V. The AND gate 56 is arranged to produce a high level output signal in response to the high level input signals applied thereto. The high level output signal from the AND gate 56 is applied to the third counter 34 to allow a counting operation by the third counter 34. Concurrently, the first counter 4 is controlled by a high level signal from the first switch 52 to accept the variable frequency signals from the variable frequency clock generator circuit 2.

The second counter 14 is continuously driven by a fixed frequency output signal from the clock 12 to produce a plurality of different subdivided frequency output signals on its output lines 16 to 22. However, these output signals are blocked by the AND gates 24 to 30 until a decoded gate energizing signal is received from the third counter 34 and the AND gates 40 to 46. In a preferred embodiment, the first output line 16 from the counter 14 is arranged to supply the highest subdivided frequency output signal while the other output lines 18, 20 and 22 supply lower frequency subdivided frequency output signals in progressive steps. The fifth output line 51 is arranged to supply a still lower subdivided frequency output signal to the AND gate 50 for application to the third counter 34. The AND gates 40 to 46 are arranged to decode the binary states of the two-stage third counter 34, i.e., the binary state 00, 01, 10 and 11. This decoding operation is effective to produce four separate and sequential output signals which are applied to the AND gates 24 to 30 to sequentially energize these AND gates to allow the subdivided frequency output signals from the counter 14 to be sequentially applied to the OR gate 32. In order to provide for an incrementation of the digital word stored in the first counter 4 from a slow speed to a high speed, the gating of the subdivided frequency signals is arranged to proceed from a low frequency signal to a high frequency signal, i.e., increasing speed of incrementation.

The fifth AND gate 43 connected to the third counter 34 is also arranged to respond to one of the binary states of the third counter 34 to enable the AND gate 50 for controlling the fifth output signal from the second counter 14. Thus, when the third counter 34 is reset by a low level signal from the AND gate 56, the AND gate 50 is de-energized to block further subdivided frequency signals from the counter 14 from being applied to the counter 34 to change its count state from the "reset" condition. While this reset condition is effective to supply one of the binary states from the third counter 34 to the AND gates 24 to 30 for energizing the lowest AND gate connected to the frequency output line from the second counter 14, the first counter 4 is prevented from accepting this low frequency signal by a low level state from the first switch 52 which switch is concurrently opened with the second switch 54. Thus, when the switches 52 and 54 are opened by an operator, the circuit is returned to an initial state by resetting the third counter 34 wherein the next closure of the switches 52 and 54 is effective to start the lowest frequency of the subdivided frequency output signals from the counter 14 to be applied to the first counter 4 with a step-wise progression as described above to the highest frequency of the subdivided frequency output signals from the counter 14. Accordingly, when the analog process control variable 10 is initially varied by the operator, the incrementation is increased from a low frequency state to a high frequency state until a gross change has been made at which point the operator opens the switches 52 and 54 to restore the initial state of the counter 34. Subsequently, the fine adjustment of the analog process control variable 10 is made by the operator by reclosing the switches 52 and 54 for a short period of time which allows only the low frequency subdivided frequency output signals from the counter 14 to be applied to the first counter 4 to further increment the digital word stored therein. Inasmuch as a desired final state of the analog process control variable 10 would be achieved by a limited number of the low frequency incrementations thus produced, the operator would subsequently reopen the switches 52 and 54 before a higher frequency incrementation of the digital word in the counter 4 had been achieved by a subsequent sequential operation of the AND gates 24 to 30.

Accordingly, it may be seen that there has been provided, in accordance with the present invention, a variable speed incrementation control for an analog output signal from a digital-to-analog signal converter circuit.