Echo Cancelling Device

The present invention relates to a device for cancelling echoes in a voice frequency signal transmission circuit, in a two-way telephone network.

It is known that in telephonic lines having circuits with two and four wires, connected together in a differential transformer, echo signals appear in the emission line. The echo canceller connected up in the four-wire circuit on the differential transformer side aims at reducing the echo signal appearing on the emission line without deteriorating the quality of the transmission.

The operation of the echo canceller is based on the fact that the path of the echo signal can be considered as a filter and that this echo signal y (t) is obtained by the convolution of the pulse reply h (t) of the path and of the signal x (t) emitted by a distant subscriber.

According to the known technique, such an echo canceller of the digital type is constituted essentially by a transversel filter having controlled weighting coefficients.

The transversal filter makes it possible to form a synthetic echo y (t) from a finite number, for example N, of filtration coefficients C, representing the samples of the pulse reply of the echo path h (t) and a same number of samples X (t) of the received signal x (t), sampled successively and suitably delayed. That echo signal y (t) obtained synthetically is subtracted from the true echo signal y (t) existing in the emission line.

An adaptive control loop makes it possible to adjust the filtration weighting coefficients C so as to obtain a residual echo .epsilon.(t) = y (t) - y (t) which is as small as possible.

In that adaptive loop, it is the result of the correlation between .epsilon.(t) and X (t) which adjusts the values of the coefficients C so that these latter represent as exactly as possible the samples of the echo path pulse reply, h (t).

A known embodiment of the echo canceller of the digital type is shown in FIG. 1. The echo canceller is installed near differential transformer 10 connecting a two-way two-wire circuit 11 to a four-wire circuit formed by two one-way channels (receiving and emitting) 12 and 13. The four-wire circuit connects the two-wire circuit 11 to another two-wire circuit, not shown, through another differential transformer, not shown, to constitute a telephone circuit between two subscriber sets connected up on the two-wire circuits.

A first shift register 20 records the samples X (t) sampled successively on the line 12 at intervals T and put in digital form in an analog-to-digital convertor 21. The capacity of register 20 is N. At each new sampling interval T, the oldest sample X (t) is replaced by the arrival of a new sample on the input. That register 20 has N outputs 22 from which the samples which exist there, referenced X (t), X (t-T), . . . X (t-NT) for the sampling period T, are taken.

A second shift register 24 memorizes N filtration weighting coefficients referenced C.sub.1 . . . C.sub.N. During each sampling period T, the contents of the two registers 20 and 24 are multiplied two by two in a multiplier 25 and the sum of these products is calculated in a summing circuit 26.

The summing circuit 26 provides the synthetic echo signal y (t) which is at the instant t considered: ##EQU1##

It is this synthetic echo signal y (t) which is deducted from the true echo y (t) so as to transmit only a residue of echo: y (t) - y (t).

In order to improve the quality of the transmission as much as possible by reducing that residual echo, the device for cancelling echoes controls the values of the weighting coefficients C.sub.i existing in the register 24, as a function of the residual echo signal.

That residual echo signal is formed in a digital subtractor 27 receiving the signal formed y (t) and the echo signal sampled at the instant t and put in digital form in an analog-to-digital convertor 23. The residual echo signal, in digital form, .epsilon.(t), at the output of the subtractor 27 is applied to a multiplier 28 also receiving the samples X (t) existing in the register 20. During the period T, the error sample .epsilon.(t) is multiplied successively, in the circuit 28, by the N samples X (t-iT) of the register 20. It is the result of the correlation between .epsilon.(t) and X (t) which adjusts the values of the weighting coefficients Ci so as to make error signal .epsilon.(t) as weak as possible in as short a time as possible.

The result of each of the multiplications effected in the multiplier 28 provides a correction term .DELTA. C.sub.i which is supplied to the summing device 29 at the same time as the coefficient Ci of same order coming from the register 24. That summing device 29 corrects the coefficients C.sub.i in the memory in the register 24 and applies the coefficients C.sub.i, corrected by the .DELTA. C.sub.i of same order, to the aforementioned multiplier 25.

At the output of the subtractor 27, a digital-to-analog converter 30 transmits the residual echo signal .epsilon. (t) which substitutes itself for the echo y (t) on the line 13 accompanied, if need be, by a signal z (t) emitted by a near subscriber.

In the above device, it is the result of the correlation between .epsilon. (t) and the samples X (t) of the received signal x (t) which adjusts the weighting coefficients C.sub.i to make the error signal .epsilon. (t) as weak as possible, in as short as possible a time called the convergence period. According to the value of .epsilon. (t) in relation to a given threshold, the correction term applied to the coefficients C.sub.i can assume a definite value among a few possible definite values.

The present invention has as its object an echo canceller of digital type, based on the above principle, produced in a simple way and implementing a particular method of processing the signals .epsilon. (t) and X (t) making it possible to increase the performances of the device.

The present invention has as its object an echo canceller comprising a transversal filter, to form a synthetic echo signal y (t), effecting a convolution of N samples X (t) each coded on n bits of a received signal x (t), recorded in a first memory and of N filtration weighting samples C obtained by correlation of the residual echo signal .epsilon.(t) and of the samples X (t) and recorded in a second memory, a digital subtractor forming the residual echo signal coded on n bits based on the true echo signal y (t) and on the synthetic echo signal, y (t) and an adaptive control loop for adjusting the filtration weighting coefficients C from the value of the said residual echo signal and from the correlation of the signs of N samples X (t) of the received signal and of the residual echo signal determining the sign of each of the variations of the filtration weighting coefficients C, characterized in that the said filtration weighting coefficients C, lower than 2.sup.n, are recorded in the said second memory (24) each on n + m bits and that the said adaptive control loop is constituted by a first adder (38) having (n + m) first inputs receiving the successive filtration weighting coefficients and having (n + m) second inputs receiving the residual echo signal .epsilon.(t) multiplied by a coefficient .alpha. close to zero and accompanied by the sign of the correlation of the signs effected, m being the minimum number of bits necessary for representing the reverse of the coefficient .alpha., and sending out the filtration weighting coefficients to the said second memory on which it is looped.

Such an echo canceller in which the coefficients C, coded on n + m bits, the m bits representing a decimal part, are corrected by increments or decrements obtained by multiplication of .vertline..epsilon.(t).vertline. by .alpha. close to zero gives more particularly:

a precise calculation of each new coefficient C;

A precise knowledge of the slight error on each new coefficient C thus calculated.

Other characteristics and the advantages of the present invention will become apparent from the description given with reference to the accompanying drawing, in which:

FIG. 1 is a diagram of an echo canceller according to the prior art,

FIG. 2 is a diagram of an echo canceller according to the invention,

FIG. 3 shows an embodiment of the diagram according to FIG. 2,

FIG. 4 is a logic circuit forming a part of the embodiment of the echo canceller according to the invention.

The diagram of the echo canceller according to FIG. 1 has been described hereinabove.

FIG. 2 shows a diagrammatic form of an embodiment of the echo canceller according to the invention. In FIG. 2, the elements which are identical to those in FIG. 1 are designated by the same references.

In FIG. 2, a single analog-to-digital convertor, namely the convertor designated by 21, ensures the coding in n bits, of the samples of the receiving signal x (t) and of the echo signal y (t) after sampling at 31 and 32 of those signals. A first commutating circuit 33 directs these sampled signals on the coder 21, whereas a second commutating circuit 34 directs the coded signals X (t) and Y (t) respectively towards the memory 20 constituted by a shift register having a capacity of N coded samples X (t) and towards a memory 35 receiving the coded samples Y (t).

The forming of the synthetic echo signal, designated by y (t) for the sampling period T of the receiving signal x (t), is obtained by successive multiplications at 25, of the N samples X (t) and of the coefficients C.sub.i of corresponding order and summing, at 26, of the N products C.sub.i X (t). The residual echo signal .epsilon.(t) is formed in the digital subtractor 27 in comparison with the synthetic echo signal y (t) and of the true echo signal y (t).

The adaptive correction loop for the filtration weighting coefficients C.sub.1 to C.sub.N, recorded in the shift register 24, operates by correlation between .epsilon.(t) and the N samples of the receiving signal X (t) in the memory at 20. That adaptive loop comprises a multiplier 36 for the signs S of the samples X (t) taken successively and for the residual echo signal .epsilon. (t) supplying N signals S (.epsilon.X) to give the sign of each correction to be made to each of the weighting coefficients C.sub.i. The multiplying circuit 36 is then constituted by a simple logic exclusive OR gate.

The adaptive loop comprises, moreover, an adder 38 looped back on the memory 24 containing the coefficients C.sub.i. The adder 38 receives on the one hand the successive coefficients C.sub.i and on the other hand the residual echo signal .vertline..epsilon.(t).vertline. across a multiplier 37, accompanied by the successive sign bits of the correlation S (.epsilon. X). The multiplier 37 effects the multiplication of .vertline..epsilon.(t).vertline. by a coefficient .alpha. close to but greater than zero, chosen, to great advantage, hereinafter, as equal to 1/256. The adder circuit 38 sends out a correction term .vertline..DELTA.C.sub.i .vertline., equal to .alpha..vertline..epsilon.(t).vertline. of the coefficients C.sub.i ; it forms, with the memory 24, a digital integrator having a very low gain in the control loop, having the configuration of a low-pass filter of the first order having a very low cut-out frequency. In the adaptive loop, the correction of the weighting coefficients C.sub.i is in connection with the .epsilon.(t) dynamic characteristic, the direction of the correction is given by correlation of the signs of the samples X (t) and of the residual echo .epsilon.(t). The proper operation of that adaptive loop is connected to the fact that, with a view to enabling a correction, which is the most exact possible, of the N weighting coefficients C.sub.i by the correction term .DELTA.C.sub.i, the coefficients C.sub.i are recorded in the memory 24 in the form of words each having n + m bits. The n bits define positive whole numbers; the m bits define positive values lower than 1, the number m corresponds to the number of bits necessary for the binary representing of .alpha.. Where .alpha. = 1/256, that is, 2.sup.-.sup.8, the number m is equal to 8. The adder 38 will then have n + m inputs for receiving the n + m bits of the coefficients Ci and m inputs for receiving the increase .vertline..DELTA.C.sub.i = .alpha...vertline. .epsilon. (t).vertline..

That arrangement makes it possible to bring in a slight error on each new coefficient C.sub.i ; moreover that error is known with precision.

FIG. 2 shows, moreover, a threshold detector circuit 39 incorporated in the device. That detector 39 receives the signal existing on the emission line 13 sent out at the output of the coder 21 and of the commutating circuit 34. The detector 39 is conditioned by the receiving signal X (t) coming from the far end and sent out by the commutating circuit 34. It effects comparison of the signal in the line 13 with a reference level calculated taking into account the signal X (t), or chosen equal to a maximum possible level of the echo signal on the line 13. That threshold detector circuit 39 sends out a first signal .beta. = 1 for a level of the signal on the line 13 which is lower than that reference. It sends out a second signal M = 1 at the time of exceeding of the reference level. When the signal x (t) is absent, these two signals .beta. and M are: .beta. = 0 and M = 0. The signal .beta. = 1, where M is necessarily 0, is significant of the presence on the line 13 only of an echo signal y (t) generated from x (t). The signal M = 1, where .beta. is necessarily 0 is significant of the presence on the line 13 of an echo signal y (t) on which a transmission signal z (t) coming from the near end 11 is superimposed: this is the case of the operation of the transmission circuit in the double speech conversation mode.

The advantage of this detector 39 will be seen hereinbelow more particularly with reference to FIG. 4.

FIG. 3 illustrates a particular embodiment of the device according to FIG. 2 in the case where the samples X (t) and Y (t) are coded with n = 8 bits accompanied by a bit S and in the case where the coefficient .alpha. of multiplication of .epsilon.(t) is chosen as equal to 1/256, where m = 8.

In FIG. 3, the elements in FIG. 2 are designated by the same reference numerals.

In the embodiment according to FIG. 3, the multiplier 25, multiplying the coefficients C.sub.i which reach it coded in 8 bits by the samples X (t) also coded in 8 bits, operates on 16 outputs bits referenced 2.sup.7 to 2.sup.0 and 2.sup.-.sup.1 to 2.sup.-.sup.8 respectively for the 8 output bits having a high weight and the 8 output bits having slight weight. The integrator 26 also has 16 inputs and 16 outputs to carry out the sum ##EQU2## on 16 bits. At the end of each sampling period, the synthesised echo signal y (t) is applied to the digital subtractor 27 in the form of a signal having 8 bits, truncating that signal y (t) on the 8 bits having the slighter weight referenced 2.sup.-.sup.1 to 2.sup.-.sup.8. The residual echo signal .epsilon.(t) is then sent out in 8 bits accompanied by a sign bit S; these bits are referenced 2.sup.0 to 2.sup.7.

Of course, it will be understood that the signal y (t) can be sent out in the form of a signal having n + m bits, that is 16 bits at the subtractor, the residual echo signal .epsilon.(t) will then be truncated on the m bits (8 bits) having the the slightest weight; .epsilon.(t) is still accompanied by the formed sign bit.

The adder 38 installed in the adaptive correction loop for the filtration weighting coefficients C.sub.i comprises 16 first inputs among which only the 8 inputs having the slightest binary weight referenced 2.sup.-.sup.1 to 2.sup.-.sup.8 receive the residual echo signal .epsilon.(t). It also has 16 second inputs referenced 2.sup.7 to 2.sup.0 and 2.sup.-.sup.1 to 2.sup.-.sup.8 receiving the coefficients C.sub.i represented by 16 bits referenced from 2.sup.7 to 2.sup.0 and 2.sup.-.sup.1 to 2.sup.-.sup.8 which are recorded in the shift register 24. The high weights of the coefficients C.sub.i corrected in the adder 38 are used only to effect the calculating of C.sub.i X (t-iT) in the multiplier 25.

The residual echo signal .epsilon.(t) applied to the first inputs having a slight weight of the adder 38 represents the increase .vertline..DELTA.C.sub.i .vertline. given to the coefficients C.sub.i, the sign of the increase being given by the product of the signs .epsilon.(t) X (t). This shift by eight orders or positions (m = 8) of the binary weights of .epsilon.(t) corresponds to the multiplying of that signal by the number n = 1/256.

A logic circuit 40 is, to great advantage, installed between the subtractor 27 sending out the residual echo signal .epsilon.(t) and the adder receiving that signal, to combine the binary weights of .epsilon.(t) on certain of the slight binary weights of the adder. That logic circuit is conditioned by the signals M and .beta. coming from the detector 39 in FIG. 2.

FIG. 4 shows a preferred embodiment of the logic circuit 40.

The residual echo signal .vertline..epsilon.(t).vertline. is applied at the input to that logic circuit. It comprises two first logic OR gates 41 and 42 combining the binary weights referenced 2.sup.7, 2.sup.6 and 2.sup.5, on the one hand and the weights referenced 2.sup.4, 2.sup.3 and 2.sup.2 on the other hand. Four logic AND gates 43, 44, 45 and 46 combine respectively the outputs of the OR gates 41 and 42 and the binary weights referenced 2.sup.1 and 2.sup.0 of .epsilon.(t) with the signal .beta. signifying the operation of the simple conversation transmission circuit x (t) (coming from the detector 39 in FIG. 2). The logic circuit comprises, moreover, a third logic OR gate 47 combining together the outputs of the OR gates 41 and 42 and the binary weights 2.sup.1 and 2.sup.0 of the signal .vertline..epsilon.(t).vertline.. A fifth logic AND gate 48 receives the signal coming from the OR gate 47 and the signal signifying the operation of the double conversation transmission circuit x (t) and z (t) (coming from the detector 39 in FIG. 2). A last logic OR gate 49 combines the signal sent out by the AND gate 48 and the signal sent out by the AND gate 48 to apply it to slightest binary weight referenced 2.sup.-.sup.8 of the summing device 38 (FIG. 3). The outputs of the AND gates 43, 44 and 45 are applied to the inputs having a slight binary weight 38 referenced respectively 2.sup.-.sup.1, 2.sup.-.sup.3 and 2.sup.-.sup.6.

This logic circuit makes it possible to give the coefficients C.sub.i increases representing the pulse reply of the echo path, whether the transmission circuit operates in the single conversation x (t) or double conversation x (t) and z (t) mode. The signals .beta. and M are directly connected with the presence of the signals x (t) and z (t). This logic circuit gives the two following states of operation:

- when operating without an emission signal z (t) coming from the near end, the signal M = 0 is obtained. If there is on receiving signal X (t) coming from the far end the signal .beta. assumes the value .beta. = 1; the residual signal .vertline..beta.(t).vertline. is applied to the adder 38 across the conductive AND gates 43 to 46, the AND gate 48 remaining blocked. Consequently, the coefficient .alpha. is at its chosen value and the convergence of the echo canceller is fast. If there is also no signal x (t), the results obtained will be .beta.=0 and M = 0. All the AND gates 43 to 46 and 48 are blocked, the signal .vertline..epsilon.(t).vertline. cannot be applied to the adder 38 and no correlation between X (t) and .epsilon.(t) is effected.

- When the transmission circuit operates with the signal z (t) and the signal x (t) applied, the result obtained, due to the exceeding of the echo threshold reference level, .beta.=0 and M = 1. Only the AND gate 48 is conductive and all the binary weights of .vertline..epsilon.(t).vertline. are applied to the input 2.sup.-.sup.8 of the adder 38: this corresponds to the detecting of the signal .vertline..epsilon.(t).vertline. of 16 orders towards the right and leads therefore to a slow convergence of the echo suppressor which neverthe continues to operate in the adaptive mode. If on the other hand there is no signal x (t), there still being the signal z (t), the result at the output of the detector is compulsorily .beta.=0 and M = 0. The AND gates of the logic circuit 40 are all blocked: no correlation can be effected.

In the echo canceller described hereinabove, the filtration weighting coefficient number N has been chosen as N = 64. The sampling period T of the receiving signals x (t) and echo signals y (t) is T = 125 .mu.s. During each period T, the bringing up to date of the values of the 64 coefficients C.sub.i is effected; simultaneously, the products C.sub.i X (t-iT) are calculated and, at the end of each period, a sample of the synthesised echo signal y (t) is formed to be compared with be sample of the true echo signal sampled, in order to provide new data for the correcting of the coefficients C.sub.i.

The sample of the synthesized echo signal y (t) is formed with exactitude since its value is truncated only at the end of the sampling period and not during the summing.

It will be observed, moreover, that the exactness of the echo canceller is due, moreover, to the fact that the coefficients C.sub.i are memorized in the register 24 in the form of a 16 bit word, this making it possible to effect an exact accumulation of the correction data .DELTA. C.sub.i, on the coefficients, whatever the value of .DELTA.C.sub.i may be. In the embodiment described, the data .DELTA.C.sub.i is given by the residual echo signal .epsilon.(t) to which a multiplication factor .alpha. = 1/256 (or a shift by 8 orders of the binary weights of .epsilon.(t) towards the right) is applied. The choice of that value .alpha. = 1/256 is an advantage and is a compromise between a value .alpha. which is as small as possible but greater than zero, to limit the loop gain produced by the digital integrator (24, 38) and thus avoid a divergence of the system and correspondingly enable the simplifying of the digital integrator circuit constituted by the adder 38 looped on the memory register 24. Of course, the value of .alpha. can be different; in a digital embodiment 1/.alpha. will be equal to a power of 2 and the number of orders of shift towards the right of .vertline..epsilon.(t).vertline. will be given by the coefficient in power.

In the example of embodiment given, with a convergence time close to 100 ms, the residual echo level generated by x (t) remains less than -40dB. At the time of operation of the echo canceller, when there is the signal z (t) coming from the near end, an automatic increase in the convergence time is given; that increase maintains the auto-adaptive operation of the echo canceller and causes no great deterioration of its performances.

The present invention has been described with reference to be embodiment illustrated, given by way of an example. It is evident that, without going beyond the scope of the invention, details can be modified and/or certain means can be replaced by other technically equivalent means therein.