Equalizer Comprising First and Second Equalizing Means and Trainable in Two Steps

This invention relates to a trainable equalizer.

On training an equalizer, it is conventional to transmit test signals from a transmitter prior to transmission of data signals to a receiver where the equalizer is located. For data signals and consequently test signals transmitted at a high speed compared with the frequency band, complicated procedures have been required for the training. For test signals subjected to a serious distortion during transmission, it has been difficult to duly train the equalizer. In order to train the equalizer with seriously distorted test signals, the transmitter may successively produce as the test signals a tone signal of the carrier frequency, a burst signal, and a pseudo-noise series or train of a predetermined pulse pattern a predetermined time after the burst signal. It is indispensable in the receiver to detect the burst signal, to find the end thereof, and to generate the predetermined time thereafter a pseudo-noise train of the predetermined pulse pattern. Furthermore, it has generally been necessary to set up correct timing between the pseudo-noise train generated in the receiver and that transmitted from the transmitter. This has inevitably resulted in a long period of time required to accomplish the training.

It is therefore an object of the present invention to provide an equalizer trainable with simple procedures in a short time.

It is another object of this invention to provide an equalizer trainable with misjudgment of the results of training substantially avoided and accordingly even with test signals supplied thereto with a serious distortion.

It is still another object of this invention to provide an equalizer trainable without the necessity of setting up correct timing between signals produced at the receiving end for training purposes and signals supplied thereto.

In accordance with this invention, there is provided an equalizer for producing an equalized signal in response to signals produced in a transmitter at a predetermined clock interval and supplied thereto. The supplied signals include a first and a second pseudo-noise train successively produced in the transmitter. The first pseudo-noise train consists of a series of blocks or partial trains, each having a first period and a predetermined pattern of pulses. The second pseudo-noise train has a second period longer than the first period. The equalizer comprises a delay line having a plurality of taps for delaying the supplied signals by a total delay equal to or longer than the first period to produce delayed signals from the respective taps. A series of adjustable gain circuits are connected to the respective taps and retain adjustable gains for giving the adjustable gains to the respective delayed signals to produce amplitude-varied signals. A noise generator produces a generated pseudo-noise train consisting of the predetermined patterns of pulses. Supplied with the generated pseudo-noise train and the amplitude-varied signals produced in response to the first pseudo-noise train by those central ones of the adjustable gain circuits which are connected to consecutive ones of the taps at which the first pseudo-noise train is delayed by a delay equal in total to the first period, first equalizing means adjusts the adjustable gains retained by the central adjustable gain circuits to make a thereby produced first output signal of the first equalizing means simulate the generated pseudo-noise train. Cyclic permutation means subjects the adjusted gains to cyclic permutation in the central adjustable gain circuits to make those of the central adjustable gain circuits which are disposed at a center portion of the series of the central adjustable gain circuits retain larger ones, in absolute values, of the adjusted gains. Supplied with the amplitude-varied signals produced in response to the second pseudo-noise train by all of the adjustable gain circuits, second equalizing means self-adaptively adjusts the adjustable gains retained by all the adjustable gain circuits to make a thereby produced second output signal of the second equalizing means become the equalized signal.

FIG. 1 is a block diagram of an equalizer according to a preferred embodiment of the instant invention and a portion of a receiver including the equalizer;

FIG. 2 shows a first pseudo-noise train and a generated pseudo-noise train;

FIG. 3 shows a series of a first and a second pseudo-noise train and another series of steps for training an equalizer according to this invention;

FIG. 4 is a block diagram of cyclic permutation means used in a simplified equalizer according to this invention; and

FIG. 5 shows several solutions obtainable by a first step illustrated in FIG. 3 with the simplified equalizer of which the cyclic permutation means is depicted in FIG. 4.

Referring to FIGS. 1 through 3, a trainable equalizer comprises an input terminal 11 supplied with signals to be equalized and an output terminal 12 to which the equalizer supplies an equalized signal after completion of the training. The supplied signals are produced in a transmitter at a predetermined clock interval T depicted in FIG. 2 and include a first and a second pseudo-noise series or train successively produced in the transmitter as best shown in FIG. 3 at 16 and 17. The first pseudo-noise train 16 consists of a series of blocks or partial trains, each having a first period P and a predetermined pattern of pulses exemplified in FIG. 2. The second pseudo-noise train 17 has a second period longer than the first period P. In the example being illustrated, the first pseudo-noise train 16 lasts twelve first periods P. The first period P is fifteen clock intervals T long. The second period is eight or more first periods P long. The first pseudo-noise train 16 may be produced by means (not shown) comprising switches, equal in number to the number of pulses in the first period P, set in compliance with the predetermined pulse pattern. The second pseudo-noise train 17 may be produced by a scrambler (not shown). When use is made of a seven-stage scrambler, it will be understood that the second period is 128 clock intervals T long.

The equalizer comprises a delay line D having a plurality of taps, n in number, including the input terminal 11. The delay line D comprises delay units D.sub.k (k = 1, 2 . . . a - 1, a . . . b - 1, b . . . and n - 1) between the respective taps. In accordance with a preferred embodiment of the present invention, each of the delay units D.sub.k delays the signals supplied thereto by a delay equal to a half of the clock interval T. Delayed signals x.sub.k (here, k = 1, 2 . . . , n - 1, and n) are produced from the respective taps. It is to be noted that the signals x.sub.1 produced at the first tap, namely, at the input terminal 11, are also called "delayed" signals for convenience of description. That portion of the delay line D which comprises the delay units D.sub. a through D.sub.b.sub.-1 provides a total delay of the first period P. In the shown example of the preferred equalizer, the whole delay line D provides a total delay of (n - 1)T/2 that is longer than the first period P.

The equalizer further comprises a series of adjustable gain circuits comprising, in turn, memory circuits G.sub.k for retaining adjustable gain signals representative of tap or adjustable gains G.sub.k (the same reference letters being used for simplicity of description), first multipliers M.sub.1.k connected to the taps and to the memory circuits G.sub.k for giving the adjustable gains G.sub.k to the delayed signals x.sub.k to produce amplitude-varied signals, second multipliers M.sub.2.k connected to the taps and responsive to a factor signal later described for multiplying the delayed signals x.sub.k by a factor given by the factor signal to produce product signals, and means for supplying the product signals to the memory circuits G.sub.k to adjust the adjustable gains G.sub.k in the manner described hereunder. Those of the adjustable gain circuits which are connected to the above-mentioned delay line portion, both ends inclusive, are herein named central adjustable gain circuits. The memory circuits G.sub.a through G.sub.b, first multipliers M.sub.1.a through M.sub.1.b, and second multipliers M.sub.2.a through M.sub.2.b of the central adjustable gain circuits are likewise called.

A first adder 21 is connected to the central first multipliers M.sub.1.a through M.sub.1.b to sum up the amplitude-varied signals produced thereby. It will be understood that the above-mentioned delay line portion, central adjustable gain circuits, and first adder 21 form a first transversal filter for producing a first transversal filter output signal. A second adder 22 is connected to the first adder 21 and to the remaining at least one first multiplier, such as M.sub.1.1, M.sub.1.2. . . and M.sub.1.a.sub.-1 (not shown) and M.sub.1.b.sub.+1 (not shown) . . . and M.sub.1.n to sum up the amplitude-varied signals produced by all of the first multipliers M.sub.1.k. The whole delay line D, all the adjustable gain circuits, and the second adder 22 form a second transversal filter for producing a second transversal filter output signal.

A receiver including the equalizer comprises a receiver input terminal 26 and an AGC circuit 27. In the manner known in the receiver art, the AGC circuit 27 carries out the so-called CD (carrier detection) to produce a pulse, or a start signal 28 depicted in FIG. 3, confirming reception by the receiver of signals sent from a transmitter and also carries out AGC to the received signals to supply the AGC-ed signals to other parts of the receiver through a terminal 29. The start signal 28 is indicative of substantial beginning of the received signals. By "substantial" beginning, it should be understood that a delay up to about two first periods P shown at 30 in FIG. 3 is allowed. In accordance with this invention, training of the equalizer is accomplished in a series of a first, a second, a third, and a fourth step 31, 32, 33, and 34 illustrated in FIG. 3. In order to define the duration of the first step 31 and the beginning of the fourth step 34, the equalizer comprises a timer 35 for producing control signals in response to the start signal 28. The control signals consist of a first control signal continuing a first predetermined interval from the start signal 28 and a second control signal appearing a second predetermined interval after the start signal 28. The first step 31 should be carried through during presence of the first pseudo-noise train 16. Consequently, the second step 32 begins before the first pseudo-noise train 16 comes to an end. The third step 33 is for insuring the fourth step 34 to begin after the second pseudo-noise train 17 is transmitted from the transmitter. In the example being illustrated, the first predetermined interval is about seven first periods P long. The second predetermined interval is about eleven first periods P long. The first control signal may comprise a first and a second pulse 36 and 37 at the leading and trailing edges thereof. In FIG. 3, the first pulse 36 is depicted in coincidence with the start signal 28 for simplicity of illustration. The second control signal may comprise a third pulse 38 at the leading edge thereof. Incidentally, it will readily be understood by those skilled in the art that the received signals are supplied from the receiver input terminal 26 to the equalizer input terminal 11 normally through a synchronous detector (not shown).

The receiver further comprises a clock generator 39 for producing clock pulses CL at the clock interval T. The equalizer comprises a pseudo-noise signal generator 40 responsive to the clock pulses CL for producing a generated pseudo-noise train X (FIG. 1) or 41 (FIG. 2) consisting of the predetermined patterns of pulses. The pseudo-noise signal generator 40 may be of the same construction as the means in the transmitter for producing the first pseudo-noise train 16. It is quite astonishingly unnecessary with an equalizer according to the preferred embodiment of this invention to establish block synchronism between the first pseudo-noise train 16 and the generated pseudo-noise train 41 and to maintain bit synchronism between the clock pulses CL and the clock intervals T of the received signals although the generated pseudo-noise train 41 is depicted in FIG. 2 in bit synchronism with the first pseudo-noise train 16 for convenience of illustration. Therefore, the clock generator 39 may not necessarily be controlled by the received signals. It is, however, desirable in order merely to stabilize the frequency of the produced clock pulses CL to effect the control through a terminal 42 in the manner known in the receiver art. The theory why the block and bit synchronisms are unnecessary is described in a paper published by the present inventor in a Japanese technical periodical, "Tusin-hosiki Kenkyukai Siryo (Papers for Communication System Study Group)" of Densi Tusin Gakkai (The Institute of Electronics and Communication Engineers of Japan), as Paper No. CS 74-23 on May 23, 1974. According to the paper, each of the delay units D.sub.k may provide a delay shorter than the clock interval T. Although a delay of T/2 is most preferred, a delay of 3T/4 is also preferred.

Inasmuch as the signals supplied to the equalizer input terminal 11 are sampled by the delay line D at a half of the clock interval T in accordance with the preferred embodiment of this invention, it is necessary to sample the first or second transversal filter output signal by a sampler 44 at the clock interval T to provide transversal filter output samples. The equalizer comprises first equalizing means for adjusting during the first step 31 the adjustable gains G.sub.a through G.sub.b of the first transversal filter in response to the first pseudo-noise train 16 and with reference to the generated pseudo-noise train 41 so that the first transversal filter output samples may simulate the generated pseudo-noise train 41. The equalizer further comprises second equalizing means for self-adaptively adjusting after the beginning of the fourth step 34 the adjustable gains G.sub.k of the second transversal filter in response to the second pseudo-noise train 17 so that the second transversal filter output samples may become the equalized signal. The equalizer still further comprises a threshold circuit or binary or multilevel signal discrimination circuit 45 known in the art for comparing the transversal filter output samples with at least one threshold level held thereby to produce resulting samples given by results of the comparison.

In order to selectively supply the first and second transversal filter output signals to the sampler 44, the equalizer comprises a first switch 46 between the adders 21 and 22 and the sampler 44. The equalizer further comprises a second and a third switch 47 and 48. The second switch 47 selectively supplies the first transversal filter output samples to a first subtractor 51 and the second transversal filter output samples to a second subtractor 52. The first subtractor 51 produces a first difference signal representative of a first difference between one each of the first transversal filter output samples and the pulses of the generated pseudo-noise train 41. The second subtractor 52 produces a second difference signal representative of a second difference between one each of the second transversal filter output samples and the resulting samples. The third switch 48 selectively supplies the first difference signal to the second multipliers M.sub.2.a through M.sub.2.b of the first transversal filter and the second difference signal to the second multipliers M.sub.2.k of the second transversal filter as the factor signal mentioned hereinabove. The factor mentioned above is given by the first difference during the first step 31 and by the second difference after the beginning of the fourth step 34. The connections formed by the switches 46 through 48 may be called first and second switch means. Responsive to the first pulse 36, the first switch means puts the first equalizing means into operation. Responsive to the second pulse 37, the first switch means terminates the adjustment by the first equalizing means of the adjustable gains G.sub.a through G.sub.b of the first transversal filter. Responsive to the third pulse 38, the second switch means puts the second equalizing means into operation.

During the first step 31, the adjustable gains G.sub.a through G.sub.b of the first transversal filter may be adjusted in compliance with the conventional means square equalization at the successive instants of the clock pulses CL. The algorithm therefor may be defined by: ##EQU1## where m represents the number of times of the gain adjustment, t represents the clock pulse instants, .alpha. represents a predetermined small positive constant of the order of 1/(2P), and d represents the pulse of the generated pseudo-noise train 41. It will now be appreciated that the means mentioned hereinabove for supplying the product signals during the first step 31 to the memory circuits G.sub.a through G.sub.b to adjust the adjustable gains G.sub.a through G.sub.b comprises means for multiplying the product signals by the constant .alpha. and means for subtracting the resulting products from the adjustable gains G.sub.a.sup.m through G.sub.b.sup.m to substitute new adjustable gains G.sub.a.sup.m.sup.+1 through G.sub.b.sup.m.sup.+1 for the previous adjustable gains G.sub.a.sup.m through G.sub.b.sup.m. Alternatively, the above-mentioned factor may be given by the first difference multiplied by the constant .alpha.. At the end of the first step 31, the adjustable gains G.sub.a through G.sub.b converge to adjusted gains that provide considerable equalization to the supplied signals.

Referring now to FIGS. 4 and 5, only six memory circuits C.sub.1 through C.sub.6 of the adjustable gain circuits for retaining adjustable gains C.sub.1 through C.sub.6 (the same reference letters being again used) are shown as the central memory circuits for simplicity of description. Due to the block asynchronism between the first and generated pseudo-noise trains 16 and 41, the memory circuits C.sub.1 through C.sub.6 retain the adjusted gains C.sub.1 through C.sub.6 in one of the manners exemplified in FIG. 5 as Solutions 1 through 6. On the other hand, it is known from the theory of equalizers for aperiodic data signals that larger ones, in absolute values, of the adjusted gains C.sub.1 through C.sub.6 should be retained, as in Solution 1 or 6, by those of the memory circuits C.sub.1 through C.sub.6 which are located at a center portion of the series of the adjustable gain circuits. In accordance with this invention, the adjusted gains C.sub.1 through C.sub.6 are therefore subjected to cyclic permutation in the memory circuits C.sub.1 through C.sub.6 during the second step 32. In other words, an equalizer according to this invention comprises cyclic permutation means for carrying out the cyclic permutation.

Referring to FIG. 4 in detail, the cyclic permutation means comprises a shift register 56 and a "step 2" operator 57 (both being depicted also in FIG. 1). The shift register 56 comprises as its stages the memory circuits C.sub.1 through C.sub.6 (in FIG. 1, G.sub.a through G.sub.b) of the central adjustable gain circuits. The operator 57 comprises a shift pulse generator 60 responsive to the second pulse 37 for supplying a predetermined number of shift pulses Y (FIG. 1) during a first half of the second step 32 to the shift register 56 so as to simultaneously shift at each instant of shift, namely, at the time of each shift pulse, the adjusted gains or, more correctly, the adjusted gain signals, to cyclically successive shift register stages. The shift pulses may have any repetition frequency. The predetermined number is equal to the number of the shift register stages. Means S.sub.1 through S.sub.6 are provided for deriving positive gains related to the respective adjusted gains, such as squares of the adjusted gains G.sub.a.sup.2 through G.sub.b.sup.2 or absolute values of the adjusted gains .vertline.G.sub.a .vertline. through .vertline.G.sub.b .vertline., in response to the respective adjusted gain signals to produce positive gain signals representative of the positive gains. Weights, such as five and three, are predetermined for the shift register stages so as to grow larger as the shift register stages depart from the center portion towards both ends of the shift register stages. Means for retaining the weights, except the weights of unity, are illustrated by arrows having the weights as the legends. Product circuits 61, 62, 63, and 64 are connected to the positive gain deriving means S.sub.1, S.sub.2, S.sub.5, and S.sub.6 for the shift register stages except those situated at the center portion C.sub.3 and C.sub.4 and to the weight retaining means to derive products of the weights and the positive gains derived for each instant of shift and to produce weighed signals representative of the products. A summing circuit 66 is connected to the gain deriving means S.sub.3 and S.sub.4 for the center portion shift register stages C.sub.3 and C.sub.4 and to the product circuits 61 through 64 to sum up the weighed signals and to produce at each instant of shift a weighed sum signal representative of a weighed sum of the positive gains. A memory 67 is provided for memorizing the weighed sum signals produced for the predetermined number of the shift pulses and also memorizing ordinal number signals representative of ordinal numbers of the shift pulses, namely, the instants of shift, for which the respective weighed sums are successively calculated by the summing circuit 66.

In a second half of the second step 32, a minimum finder 68 compares the weighed sum signals memorized in the memory 67 to find a minimum of the weighed sums. Responsive also to the ordinal number signals, the minimum finder 68 detects a specific instant of shift for which the particular weighed sum signal representative of the minimum weighed sum is produced to produce a result or specific instant signal indicative of the specific instant. Responsive to the result signal, the shift pulse generator 60 further produces additional shift pulses of a number dependent on the ordinal number of the shift pulse for the specific instant to make the center portion shift register stages C.sub.3 and C.sub.4 retain the adjusted gain signals representative of the larger adjusted gains. At this instant, the second step 32 autonomously comes to an end into the third step 33. Incidentally, the memory circuits C.sub.1 through C.sub.6 supply the adjustable or adjusted gain signals to the central first multipliers M.sub.1.a through M.sub.1.b (FIG. 1) as symbolized at Z and receive the product signals from the central second multipliers M.sub.2.a through M.sub.2.b through the above-mentioned means U.

As described in the preamble of the instant specification, the delay provided by the delay line D may be equal to the first period P. In this event, it is possible to simplify the circuitry of an equalizer according to the preferred embodiment by substituting a single adder 21 or 22 for the two adders 21 and 22 and by omitting the first switch 46. The transversal filter output samples serve as a first output signal of the first equalizing means during the first and second steps 31 and 32 and serve as a second output signal of the second equalizing means after the beginning of the fourth step 34.

While this invention has thus far been described in conjunction with specific embodiments thereof, it will be understood that an equalizer according to this invention is trainable primarily in two steps or procedures, namely, in the first step 31 by the first equalizing means and in the fourth step 34 by the second equalizing means. The first period P may be from fifteen to twenty clock intervals T long. Inasmuch as it is desirable to complete the training in a shortest possible period of time, it is preferred to produce in the transmitter the first pseudo-noise train 16 immediately followed by the second pseudo-noise train 17 although a short interval may be left therebetween. It is also preferred that the duration of the first pseudo-noise train 16 be about 250 milliseconds and that that of the first step 31 be about 150 milliseconds. It is possible to accomplish the second step 32 in about one first period P. Under the circumstances, the second predetermined interval for the third pulse 38 may be about 230 milliseconds long. The data signals may be either binary or multilevel signals of a predetermined clock or bit interval T, which provides time slots in multiplexed communication. When the data signals are of multilevel pulses, it is preferable to use a pulse train of the same number of levels as the second pseudo-noise train 17 while the first pseudo-noise train 16 may be whichever of a binary pulse train and a pulse train of the same or a different number of levels.