Semiconductor Circuit Device

This invention relates to a semiconductor circuit device, and in particular a semiconductor device using a depletion type insulated gate field effect transistor (hereinafter referred to as IG-FET) as a transistor gate for the charging and discharging of a capacitance element, in which it is possible to obtain a great time difference between the delay of rise of a pulse signal on a node in the circuit device and the delay of fall of the pulse signal on the node in the circuit device.

As a method for varying a rise-fall time ratio of a pulse signal on a node in a semiconductor circuit device using the IG-FET, it has conventionally been practised to change a ratio of a conductance of a drive transistor to a load conductance of a gate circuit for driving the node in the above-mentioned semiconductor circuit. Since, however, the transfer characteristics and noise margin are dependent upon the ratio of the load conductance of the gate circuit to the conductance of the drive transistor, the margin of the transfer characteristic of the gate circuit is decreased with the resultant disadvantage.

It is accordingly the object of this invention to provide a semiconductor circuit device capable of obtaining a sufficiently great time difference between the charge and discharge of a capacitance on a node in the semiconductor circuit device.

According to this invention there is obtained a semiconductor circuit device comprising a transfer gate circuit including at least one depletion type IG-FET of one conduction type channel having first and second electrodes and a gate electrode connected to one of the first and second electrodes, and a capacitance charging and discharging circuit connected to the input side of the transfer gate circuit so as to charge and discharge a capacitance present between ground and a node at the output side of the transfer gate circuit.

FIG. 1 is a circuit diagram showing a semiconductor circuit device according to one embodiment of this invention;

FIG. 2 is a waveform diagram for explaining the operation of the embodiment of FIG. 1;

FIG. 3 is a characteristic curve showing the operation characteristic of the embodiment of FIG. 1;

FIG. 4 is a circuit diagram showing a modification of the embodiment of FIG. 1;

FIG. 5 is a circuit diagram showing another modification of the circuit of FIG. 1;

FIG. 6 is a circuit diagram showing another modification of the embodiment of FIG. 1;

FIG. 7 is a block diagram showing a memory circuit to which this invention is applied;

FIG. 8 is a block diagram showing, by way of example, a driver circuit shown in FIG. 7;

FIG. 9 is a circuit diagram of the memory cell shown in FIG. 7;

FIG. 10 is a waveform diagram for explaining the operation of the circuit of FIG. 9;

FIG. 11 is a circuit diagram showing, by way of example, a waveform shaping circuit to which this invention is applied;

FIG. 12 is a waveform diagram for explaining the operation of the circuit of FIG. 11;

FIGS. 13 and 15 are circuit diagrams for showing further embodiments of the waveform shaping circuit;

FIGS. 14 and 16 are waveform diagrams for explaining the operations of the embodiments of FIGS. 13 and 15;

FIG. 17 is a circuit diagram showing an embodiment of this invention as applied to a timing signal generating circuit; and

FIG. 18 is a waveform diagram for explaining the operation of the circuit of FIG. 17.

In this specification, a channel of a depletion type IG-FET of which gate electrode is supplied with a zero-volt bias is referred to as a remaining channel, and only when the gate electrode of the IG-FET is forward biased with a predetermined voltage, the IG-FET is referred as ON state.

In FIG. 1, a depletion type n-channel IG-FET 2 has a drain electrode connected to the terminal 1 of a positive voltage power source of, for example, +5 volts. The gate electrode of the IG-FET 2 is connected through a node 3 to the source electrode of the IG-FET 2. To the node 3 is coupled the drain electrode of an enhancement type n-channel IG-FET 4. The IG-FET 4 has its gate electrode coupled to an input terminal 5 and its source electrode grounded. To the node 3 is coupled a common junction between the gate and source electrodes of a depletion type n-channel IG-FET 6 which constitutes a node 7. The drain electrode of the IG-FET 6 is connected through a node 8 to the gate electrode of an enhancement type n-channel IG-FET 9. The IG-FET 9 has its source electrode grounded and its drain electrode coupled to an output terminal 11 through a junction between the gate and source electrodes of a depletion type n-channel IG-FET 10. The drain electrode of the IG-FET 10 is connected to a terminal 12 of a positive power source of, for example, +5 volts.

The operation of the semiconductor circuit device of FIG. 1 will now be explained by reference to FIG. 2.

Since, at t = 0, a signal voltage applied to the input terminal 5 is +5 volts, the IG-FET 4 is in the ON state. The node 3 and thus the node 7 are substantially zero volt as shown in FIG. 2(b). Consequently, the node 8 coupled through the depletion type IG-FET 6 is zero volt as shown in FIG. 2(c) and the IG-FET 9 is in the OFF state. Since, at this state, the IG-FET 10 is turned ON, an output voltage on the output terminal 11 is about 5 volts, at t = 0, as shown in FIG. 2(d).

When, at t = t1, the signal voltage on the input terminal 5 is abruptly dropped down to zero volt as shown in FIG. 2(a), the IG-FET 4 is abruptly turned OFF and the potential on the node 3 is rapidly raised to +5 volts. As a result, the potential on the node 7 is also rapidly increased as shown in FIG. 2(b) to cause the IG-FET 6 to be rapidly rendered conductive. The potential on the node 8 is rapidly increased somwhat later than at t = t1, as shown in FIG. 2(c). This delay is ascribed to a time constant between a resistance between the source and drain electrodes of the IG-FET 6 and a stray capacitance such as the gate capacitance, capacitance between the connection wires and the substrate, junction capacitance etc. of the IG-FET 9 connected between the node 8 and ground. When the potential on the node 8 is rapidly raised as shown in FIG. 2(c), the IG-FET 9 is rapidly turned ON to cause the voltage on the output terminal 11 to be rapidly dropped down to zero volt as shown in FIG. 2(d).

When, at t = t1, the input voltage is increased stepwise to +5 volts as shown in FIG. 2(a), the IG-FET 4 is rapidly turned On and the potential on the node 7 is rapidly lowered to zero volt as shown in FIG. 2(b). As a result, the gate bias of the IG-FET 6 becomes zero volt, but the remaining channel is left between the source and drain electrodes of the depletion type IG-FET 6. The above-mentioned stray capacitance built up between the node 8 and ground is discharged little by little through the remaining channel left at the IG-FET 6 and through the IG-FET 4, and the potential on the node 8 is gradually decreased, at t = t2, as shown in FIG. 2(c) to cause the IG-FET 9 to be gradually turned OFF. Consequently, an output voltage at the output terminal 11 is gradually increased as shown in FIG. 2(d).

In this way, the charge and discharge of the stray capacitance developed between the node 8 and ground is effected through IG-FET's 2 and 4 as a charge-discharge circuit and the depletion type of IG-FET 6 which serves as a transfer gate. At the charge time, the stray capacitance is rapidly charged to +5 volts through the IG-FET 2 and turned-ON IG-FET 6. At the discharge time, on the other hand, the stray capacitance is slowly discharged through the turned-ON IG-FET 4 and through the remaining channel of the IG-FET 6 whose gate voltage is zero volt. The time variation of the voltage on the output terminal 11 at the charge and discharge of the stray capacitance is as shown in FIG. 3. The origin of the time axis in FIG. 3 is at the time when the level of the input voltage is switched, for example, as shown at t = t1 and t = t2 in FIG. 2(a). A time required for the voltage on the node 8 to become 1 volt is about 78 nano-second at the discharge of the stray capacitance and about 138 nano-second at the charge of the stray capacitance, leaving a voltage difference of about 60 nano-second between them. In the case of 2 volts, a much more time difference results. If such a time difference is utilized, it is possible to prevent, for example, a mutual interference between the memory contents of memory cells at the write-in and read-out time and an erroneous operation at the time of reading out any data from the memory cell, as will be later described.

There will now be explained the other embodiments and modifications of this invention. The similar reference numerals are employed to designate parts or elements corresponding to those shown in FIG. 1 and any further explanation is therefore omitted.

In a modification shown in FIG. 4, an enhancement type n-channel IG-FET 2a having its gate and drain electrodes commonly connected to the positive power source 1 is used in place of the IG-FET 2 of FIG. 1 and a resistor 10a is used in place of the IG-FET 10 in FIG. 1. This circuit is operated in the same way as in FIG. 1.

The FIG. 5 is similar in arrangement to the modification of FIG. 4, except that use is made, in place of the enhancement type IG-FET 2a in FIG. 4, of an enhancement type p-channel IG-FET 2b whose gate electrode is coupled, together with the gate electrode of the enhancement type n-channel IF-FET 4, to the input terminal 5, and that the node 3 is connected to a junction between the source electrode of the IG-FET 2b and the drain electrode of the IG-FET 4. If a signal voltage on the input terminal 5 is, for example, +5 volts, the IG-FET 2b is turned OFF, while the IG-FET 4 is turned ON, and a voltage on the node 3, as well as on the node 7, is substantially zero volt. Since, in this case, the IG-FET 9 is turned OFF, a potential on the ouptut terminal 11 is +5 volts through the resistor 10a.

When the input voltage is dropped down to zero volt, the IG-FET 2b is turned ON and the IG-FET 4 is turned OFF. Since, in this case, the voltage variation is rapidly effected, a voltage on the node 7 is rapidly increased and, in consequence, a stray capacitance on the node 8 is also rapidly charged, causing a rapid drop of a voltage on the output terminal 11 to zero volt. When, on the other hand, the input voltage is increased from zero volt to +5 volts, the IG-FET 2b is turned OFF and the IG-FET 4 is turned ON. As a result, a potential on the node 7 becomes substantially zero volt and the stray capacitance on the node 8 is slowly discharged through the remaining channel of the depletion type IG-FET 6. Therefore, the IG-FET 9 is slowly turned OFF, causing the potential on the output terminal 11 to be slowly raised.

Although with the above-mentioned embodiments the stray capacitance is used as a capacitance which is charged and discharged through the transfer gate FET 6, a capacitor element 9a as shown in FIG. 6 may, of course, be used as such. In this case, the capacitor element 9a is rapidly charged through the IG-FET's 2 and 6 and slowly discharged through the IG-FET's 6 and 4. Many modifications may be used as the charge path between the node 3 and the terminal 1, and 9 a discharge ground. A p-channel type IG-FET may of course be employed in place of the n-channel type IG-FET.

FIG. 7 shows a block diagram showing the major part of a memory device using a difference in time between the charge and discharge of a capacitance.

In FIG. 7, reference numeral 21 shows a circuit for a row address selection; 22, a circuit for a column address selection; 23, a memory matrix; and 24, an input/output circuit. These circuits are usually integrated on a single chip. The row and column of the memory matrix may of course be oriented interchangeably.

The outputs of a plurality of row address selecting drivers 111a, 111b and 111c each composed of inverter are suitably connected to decoders 112a and 112b each constituting an NOR gate. For the sake of clarity, only the three row address selecting drivers are shown by way of example. With a full decode system in view, 2.sup.3 decoders (i.e. 8 decoders) are necessary. In FIG. 7, only the two decoders are shown by way of example. The output of the decoder 112a is connected to the row selecting line of the memory matrix 23 through a decoder output driver having an even number of stages, for example, a two-stage decoder output driver (i.e. 13 and 14), each stage of which consists of an inverter. The decoder output drivers 13 and 14 are not particularly necessary, if the output signal of the decoder 112a is of a magnitude sufficient to drive the memory matrix 23. Between the decoder output drivers 13 and 14 is connected a depletion type IG-FET 6 of n-channel variety. The control gate of the IG-FET 6 is coupled to the source electrode of the IG-FET 6.

The row address selecting drivers 111a, 111b and 111c generate, upon receipt of an input signal, an output signal which is coupled to a predetermined decoder, for example, the decoder 112a. The output of the decoder 112a is delivered through the first decoder output driver 13 to the source electrode of the depletion type IG-FET 6. In the normal state, the output of the decoder 112a takes either one of the states "High" and "Low". In this embodiment, the High state is +5 volts and the Low state is zero volt.

There will now be explained the charging and discharging of a stray capacitance on a node 7 at the input side, i.e. the source electrode side, of the depletion type IG-FET 6 and on a node 8 of the output side i.e. the drain electrode side thereof.

When the node 7 on the source electrode side of the IG-FET 6 is, upon being charged, changed from the Low state to the High state, the gate electrode of the IG-FET 6 which is connected to the source electrode of the IG-FET 6 also assumes the High state. As a result, the source-drain conductance of the IG-FET 6 is increased, causing the stray capacitance on the node 8 to be rapidly charged.

The node 7 on the source electrode of the IG-FET 6 is discharged through the first decoder output driver 13, resulting in a change from the High state to the Low state. At this time, the node 7 is rapidly discharged, thus lowering a potential on the gate electrode of the IG-FET 6. For this reason, the drain-source conductance of the IG-FET 6 becomes small and the node 8 on the drain side of the IG-FET 6 is slowly discharged. It is therefore possible to obtain a great time difference between the delay of rise and the delay of fall of the pulse signal on the node 8 at the drain side of the IG-FET 6. Such charging and discharging characteristics can be properly varied by changing, for example, the threshold voltage, and width-length ratio of the gate electrode, of the depletion type IG-FET 6.

To the node 8 on the drain electrode side of the IG-FET 6 is connected a node 18 on the output side of the second decoder output driver 14. Since the node 8 on the input side of the decoder output driver 14 is rapidly charged and slowly discharged, the node 18 on the output side of the decoder output driver 14 is slowly charged and rapidly discharged.

FIG. 3 shows the time variation of a potential on the node 18, as measured at the charging and discharging times, which is caused upon applying a pulse signal to the decoder 112a of the row address selecting circuit 21. In the graph of FIG. 3 the origin denotes the point in time when the input pulse on the address selecting driver is switched, and a dotted line drawn at the level of 1 volt denotes a threshold voltage necessary to operate the designated row selecting lines of the memory matrix 23. When the voltage on the node 18 falls from 5 volts to below the threshold voltage of 1 volt as shown in FIG. 3, the designated row selecting line of the memory matrix 23 is turned OFF. When, on the other hand, the voltage rises from zero to above 1 volt, the designated row selecting line of the memory matrix 23 is turned ON. The threshold voltage may be suitably selected.

The column address selecting circuit 22 is essentially similar to the row address selecting circuit 21. The outputs of, for example, two column address selecting drivers 30a and 30b are properly coupled to decoders 31 and 52. The outputs of the decoders 31 and 52 are coupled respectively through first decoder output drivers 32 and 53 to a node on the source side of respective depletion type IG-FET's 33 and 54. The node on the source side of the IG-FET 33 is coupled to the control gate electrode 35 of the IG-FET 33. To the node 36 on the drain electrode side of the depletion type IG-FET 33 is coupled an inverter 37 constituting a second decoder output driver. The output of the second decoder output driver 37 is delivered to the gate electrode 39 of the column selector 38. The charging at the node 36 is fast and discharging is slow in the same way as in the column address selecting circuit. Therefore, the output of the inverter 37 supplied from the node 36, i.e. a common gate electrode 39 of first and second IG-FET's 40 and 41, both constituting the selector 38, has such a charging and discharging characteristic that it is slowly charged and rapidly discharged. The drain electrode 42 of the first IG-FET 40 is coupled to a predetermined digit line 44, while the drain electrode 43 of the second IG-FET 41 is coupled to a predetermined digit line 45. The digit lines 44 and 45 in a pair are connected to transistors 46 and 47, respectively. With one of the paired digit lines having a value of D, the other digit line assumes a value of D. The transistors 46 and 47 normally supply voltages to the respective digit lines. A node 48 on the source electrode of the first IG-FET is connected to the input and output circuit 24, while a node 49 on the source electrode of the second IG-FET is connected to the input and output circuit 24. Reference numerals 50 and 51 show load resistors for the respective digit lines. To the nodes 48 and 49 is connected the source electrode of three remaining IG-FET's not shown, each constituting a selector.

The arrangement of the memory matrix 23 will be explained by citing a well known static type memory cell.

FIG. 9 shows a memory cell constituting part of the memory matrix 23. For the sake of clarity only two memories M1 and M2 are shown by way of example. A flip-flop circuit is used in the memory cells M1 and M2. The memory cell M1 consists of a memory cell body m1 and gate transistors Tr1 and Tr2, while the memory cell M2 consists of a memory cell body m2 and gate transistors Tr3 and Tr4. Row selecting lines a' and b' are connected respectively through the gate transistors Tr1 and Tr2, and Tr3 and Tr4, to the memory cells M1 and M2. The row digit line 44 is connected through a point A3 to the memory cell M1 and through a point B3 to the memory cell M2, while the digit line 45 is connected through a point A4 to the memory cell M1 and through a point B4 to the memory cell M2.

Suppose that the row selecting lines a' and b' are connected to the nodes 18 and 19, respectively, in the row address selecting circuit 21. When the row selecting line a' assumes the High state, the transistors Tr1 and Tr2 are held in the "ON" state. Where, for example, a pair of data 1, 0 are read out of the memory cell body m1, they are coupled respectively through the transistors Tr1 and Tr2 one to the digit line 44 and the other to the digit line 45. With the digit line 44 in the High state, the digit line 45 assumes the Low state. The digit lines 44 and 45 are in a reversed relation to each other. With the common gate 39 in the High state and the IG-FET 40 in the ON state, the data coupled to the digit lines 44 and 45 are delivered respectively through the source electrodes 48 and 49 to the input and output circuit 24. Where, with the row selecting line b' in the High state, the memory cell M2 is selected by the row selector, the corresponding data are supplied, likewise, to the input and output circuit 24.

The operation of one embodiment of this invention will be explained on the assumption that the column lines of the memory matrix are held fixed and that an input signal for row address selection is switched.

For ease in explanation, suppose that a first signal is supplied through the decoder 112a to the row selecting line. Next suppose that the row address selecting input signal is switched and that a second signal is supplied through the decoder 112b to the row selecting line b'.

FIG. 10 shows the case where a signal is applied to the row address selecting driver with a cycle time of 500 nano-second and t = 0 and the signal is switched at t = 500 nano-second, a potential on the row selecting line a' being shifted to the Low level and a potential on the row selecting line b' being gradually shifted to the High level. As will be understood from the graph of FIG. 3 a relatively slow charge is effected on the row selecting line a' and after a predetermined cycle time (in this case, 500 nano-second) a rapid discharge is effected by the switching of the signal. At t = 500 nano-second + 78 nano-second, for example, the potential on the row selecting line a' is decreased to 1 volt, causing the transistors Tr1 and Tr2 to be turned OFF. As a result, the memory M1 is completely closed. At t = 500 nano-second, the potential on the row selecting line b' is slowly charged and at t = 500 nano-second + 138 nano-second, for example, increased to 1 volt, causing the transistors Tr3 and Tr4 to be turned ON. In consequence, the memory M2 is opened, permitting an exchange of data between the digit lines 44 and 45. Since according to this invention a different charging time can be provided between the row selecting lines, it is possible to prevent simultaneous opening of the memory cells M1 and M2. If, for example, the transistor Tr3 is turned ON before the transistor Tr1 is turned OFF, the memory bodies m1 and m2 are operatively connected through the transistors Tr1 and Tr3 to cause an erroneous operation such as the mistransfer, mixing etc. of data stored in the memory bodies m1 and m2. According to this invention, however, the other transistor is turned ON after one transistor is completely turned OFF, thus assuring a stabilized operation without involving any erroneous operation. This advantageous feature can be most suitably applied to a full decode type memory. Since the depletion type IG-FET is used as a transfer gate, not as a usual load resistor, it is possible to provide a different charging-discharging time between the row selecting lines without varying the transfer characteristic of the system. Furthermore, the charging-discharging time difference can be adjustably varied in favor of design consideration by suitably changing the gate configuration of the depletion type IG-FET, threshold value etc.

Although the explanation is restricted to the row selecting lines only, the same thing can equally be applied to the column selecting lines. That is, the row decoder 52, first driver 53, depletion type IG-FET 54 having the source and gate electrodes connected in common, second driver 55, gate 57 of the selector 56 are connected as shown in FIG. 7. The IG-FET's 58 and 59 are connected with the common gate 57 left therebetween. The source electrodes of the IG-FET's 58 and 59 are connected to the lines 48 and 49, respectively and the drain electrodes of the IG-FET's 58 and 59 are connected to digit lines 60 and 61, respectively.

Consider now that, with such an arrangement, an input signal to the row address selecting driver is switched. When the selector 38 is shifted, upon receipt of a signal from the decoder 31, from the ON state to the OFF state, a potential on the gate electrode of the selector 38 is rapidly decreased to cause the IG-FET's 40 and 41 to be shifted to the OFF state to permit the selector 38 to assume the closed state. On the other hand, the gate 57 of the selector 56 is slowly charged to cause the IG-FET's 58 and 59 to be slowly shifted to the ON state. In this way, data through the digit lines 44 and 45 are first transmitted to the input and output circuit 24 and, after some length of time, data through the digit lines 60 and 61 are transmitted to the input and ouput circuit 24, thus preventing mixing of data. It is therefore possible to prevent any erroneous operation which would otherwise occur when data is read out of the memory.

A memory matrix read-out/write-in selecting signal and chip selecting signal are coupled to terminals R/W and CS, respectively, of the input and output circuit 24. A terminal I/O of the input and ouput terminal receives an input or generates an output. A plurality of chips (only one is shown in FIG. 7) are provided on the input and output circuit 24. Any one of the chips is selected by applying the signal to the terminal CS. The input and ouput circuit 24 is a usual circuit.

For example, the chip shown in FIG. 7 is selected by applying a signal 0 to the terminal CS of the input and output circuit 24 and then data is read out of the memory. In this case, the flow of the signal is as follows:

Suppose that a potential on the line 48 is 0, and a potential on the line 49 is 1, when data is read out of the memory 23. Since, in this case, an n-channel type IG-FET 70 is turned OFF upon receipt of a signal 0 on the line 48 and an n-channel type IG-FET 71 is turned ON upon receipt of a signal 1 on the line 49, one input of an NOR gate 72 is 0. The signal 0 on the terminal CS is supplied through an inverter 85 to the NAND gate 84 and the signal 1 on the terminal R/W is supplied through an inverter 86 to the NAND gate 84. Since the output of the NAND gate 84 is 0, both the inputs of an NOR gate 72 are 0. As a result, the NOR gate 72 generates an output 1 which, in turn, is coupled to one input of an NOR gate 73 of the succeeding stage. Since the ouput 0 of the NAND gate 84 is coupled to the other input of the NOR gate 73, the ouput of the NOR gate 73 is 0. The output 0 of the NOR gate 73 is coupled to the gate electrode of n-channel type IG-FET 74. The IG-FET 74 is therefore held in the OFF state. The output 1 of the NOR gate 72 is coupled to the gate electrode of an n-channel type IG-FET 75 to cause the latter to be held in the ON state. Consequently, the potential on the terminal I/O is zero volt, i.e. the output of the terminal I/O is 0. Therefore, a section enclosed by a dotted line block R(99) serves to effect readout operation.

Writing data into the memory matrix 23 is effected by applying a signal 0 to the terminals CS and R/W to select a predetermined address through a circuit W(100) and, at the same time, supplying a data signal to the terminal I/O. It should be noted that the logical level on each part of the input and ouput circuit 24 in FIG. 7 is that level assumed at the readout time. At the write-in time the input of the terminal R/W is 0. In this case, the ouput of the NAND gate is 0 and that of the gate 84 is 1. If the level on the terminal I/O is 0, the output of the inverter 82 is 1 and both the inputs of the NOR gate 81 are 1 and 0, respectively. Consequently, the NOR gate 80 generates an ouput 1. The output 1 of the NOR gate 80 is delivered to the gates of the n-channel type IG-FET's 77 and 78 to cause the latter to be turn ON. Since, on the other hand, the n-channel IG-FET's 76 and 79 are held in the OFF state by the output 0 of the NOR gate 81, a signal 0 is passed through the line 48 and a signal 1 is passed through the line 49. An inverter circuit for generating two ouputs, opposite in polarity to each other, with respect to one input from the drivers 111a to 111c, 30a, 30b etc. as shown in FIG. 7 is comprised of, for example, three usual inverters I1, I2 and I3 as shown in FIG. 18. A signal A to an input terminal is derived, as two signals A and A opposite in polarity to each other, from an output terminal as shown in FIG. 8.

There will be explained by reference to FIGS. 11 to 16 embodiments of this invention as applied to a waveform shaping circuit.

A waveform shaping circuit of FIG. 11 is entirely similar in arrangement to the circuit of FIG. 1 and any further explanation is, therefore, omitted by applying the same reference numeral to parts or elements corresponding to those shown in FIG. 1.

When a pulse signal with a waveform as shown in FIG. 12(a) is applied to an input terminal 5 in FIG. 11, an IG-FET 4 is turned ON at time A1. The pulse signal is delayed by a time required for an IG-FET 9 to be turned OFF and a potential on an ouput terminal 11 becomes a high level as shown in FIG. 12(b). When at time t2 the input becomes zero, the IG-FET's 6 and 9 are almost simultaneously turned ON and an output level becomes zero. In consequence, a pulse input corresponding to a time width (t2 - t1) is generated as a pulse of a narrow width corresponding to a delay due to the discharge of a stray capacitance.

FIG. 13 shows an embodiment in which the gate and drain electrodes of a depletion type IG-FET 6 are connected in common. At the drain electrode side of the IG-FET 6 a slow charge and rapid discharge result. In consequence, a rapid rise of output is effected with respect to a rise of input and the fall of the ouput is delayed with respect to the fall of the input. A pulse output of a width as shown in FIG. 14(b) is therefore obtained with respect to an input as shown in FIG. 14(a).

FIG. 15 shows an embodiment in which use is made as a transfer gate of series-connected depletion-type IG-FET's 6a and 6b. The gate and drain electrodes of the IG-FET 6a are connected to each other, while the gate and source electrodes of the IG-FET 6b are connected to each other. As shown in FIG. 16, therefore, it is possible to obtain an output pulse of a width substantially the same as that of an input pulse, i.e. an ouput pulse whose phase is shifted with respect to the input pulse, as shown in FIGS. 16(a) and (b).

FIG. 17 shows an embodiment of this invention as applied to a timing signal generating circuit. In FIG. 17, an input signal a as shown in FIG. 18(a) is supplied through an inverter 120 to a junction between the gate and source electrodes of an IG-FET 6a. In consequence, an output signal b on the drain electrode of the IG-FET 6a has a narrow pulse width as shown in FIG. 18(b) which is similar to the narrow pulse width as shown in FIGS. 11 and 12. The output signal b is coupled to an inverter 121 where an inversed signal c as shown in FIG. 18(c) is obtained. The signal c is derived as one output signal of the timing signal generating circuit from one output terminal and, at the same time, is coupled to a junction between the gate and source electrodes of an IG-FET 6b. As explained in connection with FIGS. 13 and 14, the ouput of the IG-FET 6b has a wide pulse width with respect to that of the input signal c. The output of the IG-FET 6b is coupled to a two stage inverter (i.e. inverters 122 and 123) where an ouput of a wide pulse width as shown in FIG. 18(d) is obtained. The output of the inverter 120 is also coupled to the source of another depletion type IG-FET 6c. The gate and drain electrodes of the IG-FET 6c are connected to each other. Consequently, a signal e with a wide pulse width as shown in FIG. 18(e) is obtained at the drain electrode side of the IG-FET 6c with respect to the inversed ouput of the inverter 120. The output signal e of the IG-FET 6c is derived, through inverters 124 and 125, as one output h of the timing signal generating circuit. The output of the inverter 124 is also coupled to the source electrode of a depletion type IG-FET 6d. Since the gate and drain electrodes of the IG-FET 6d are connected to each other, an output signal f at the source electrode side of the IG-FET 6d has a narrower pulse width as shown in FIG. 18(f) than the width of the signal e. The output f is coupled to an inverter 126 where an inverted signal g as shown in FIG. 18(g) is obtained.

Though the above-mentioned embodiments use the n-channel type IG-FET, the same result can also be obtained by employing a p-channel type IG-FET.