Key Switch Signal Multiplexer Circuit

The present invention relates to a key input circuit for use in electronic equipment or appliances, such as electronic desk calculators.

The key input circuit is used as the input circuit of an electronic desk calculator, an electronic typewriter or the like electronic equipment, and is usually composed of a plurality of push-button switches. Desired key information is inputted to the electronic equipment by sequentially manipulating the push-button switches.

FIG. 1 shows an example of a prior art key input circuit which was proposed by the present inventors. In the figure, PG designates a timing pulse generator which transmits a plurality of series of timing pulses DT1-DT10 successively shifted on phase on its respective output lines. Shown at KB.sub.1 and KB.sub.2 are key blocks by which groups of, for example, numeral key signals and function key signals are formed. A plurality of keys, not shown in this figure, within the key blocks KB.sub.1 and KB.sub.2 are respectively connected to outputs of the timing pulse generator PG. Read control circuits RC.sub.1 and RC.sub.2 receive outputs of the keyboards KB.sub.1 and KB.sub.2 as their inputs, respectively, and receive the outputs of the timing pulse generator PG as synchronization control signals. An encoder EC converts the outputs of the read control circuits RC.sub.1 and RC.sub.2 into, for example, combinations of signals representing binary numbers. A memory circuit M stores the outputs of the encoder EC.

IC indicates an integrated semiconductor device, part of which is constituted of the timing pulse generator PG, the read control circuits RC.sub.1 and RC.sub.2, the encoder EC and the memory circuit M. P.sub.01 - P.sub.0n represent output terminals of the integrated semiconductor circuit, and P.sub.i1 and P.sub.i2 represent input terminals thereof. The operation of the key input circuit thus constructed will be briefly explained below.

Information as to, for example, which keys in the key block KB.sub.1 have been depressed is represented by timing pulses, which timing pulses are multiplexed on one line and are fed to the read control circuit RC.sub.1. On the basis of the timing pulses, the read control circuit RC.sub.1 distinguishes which depressed keys the multiplexed key signals correspond to. The key information restored by the read control circuits RC.sub.1 and RC.sub.2 in this way are coded into binary numbers by the encoder EC. The coded key information is stored in the memory circuit M.

According to the key input circuit thus described, the number of the input terminals P.sub.i1 and P.sub.i2 from the keys to the integrated semiconductor circuit IC can be made remarkably smaller as compared with the number of keys.

Here, if the number of timing pulse series is increased a larger number of key information signals can be multiplexed. That is, since a timing pulse must be applied to each key in the system of the type disclosed in FIG. 1, in order to increase the number of keys it was previously required to increase the number of timing pulses in each series. The timing pulses, however, are not exclusively used for the key input circuit, but are mainly used as indication digit switching signals in the case of performing dynamic indication in an associated display device, for example, as seen in U.S. Pat. No. 3,715,746. When the number of timing pulse series is increased only for use in the key input circuit, the number of timing pulses employed becomes larger than the number of indication digits. Thus, if the number of timing signals exceeds the number of indicator lamps in the display device, it might be necessary to control the number of indicator lamps by more than one timing signal or to control the respective lamps by nonconsecutive timing singals, either of which conditions would result in a flickering of the display lamp. As a result, the indication is intermittently effected, and it becomes extremely unstable and produces a flickering appearance to the eyes. Accordingly, it is also undesirable from the aspect of arithmetic control if the number of timing pulse series is increased only for the purpose of multiplexing a larger number of key information signals. Further, when the number of timing pulse series is increased, the number of the external output terminals P.sub.0l - P.sub.0n of the integrated circuit must be increased on account of the necessity for supplying a different series of timing pulses to each of the keys. However, it is extremely difficult to increase the number of terminals in an integrated circuit.

In this respect, with the circuit shown in FIG. 1, a plurality of keys are classified into relatively few key blocks, and the read control circuits are connected to the respective blocks, whereby a large number of key information signals are represented with a small number of timing pulse series.

The present invention intends to further improve the key input circuit as stated above.

An object of the present invention is to provide a key input circuit which can easily increase the number of keys without increasing the size and complexity of the read control circuit which is already composed of a large number of gate circuits.

Another object of the present invention is to provide a key input circuit which can generate a number of key information signals without adding to the number of timing pulses and having a small number of timing pulses.

Another object of the present invention is to provide a key input circuit which reduces the number of input terminals from key blocks to an integrated circuit by substituting a plurality of timing pulses for the information of a key.

FIG. 1 is a circuit diagram showing an example of a key input circuit of the prior art;

FIG. 2 is a circuit diagram showing an embodiment of a key input circuit according to the present invention;

FIG. 3 is a circuit diagram of key switches to be connected on the input side of the circuit shown in FIG. 2;

FIG. 4 is a waveform diagram of pulse signals derived from a pulse generator for use in the key input circuit shown in FIG. 2;

FIG. 5 is a table listing the relations between key information and output signals; and

FIG. 6 is a schematic block diagram of an alternate embodiment of he key input circuit of the present invention.

An embodiment of the key input circuit according to the present invention will be described in detail hereunder with reference to the accompanying drawings.

FIG. 2 is a circuit diagram showing the embodiment of the key input circuit according to the present invention. In the figure, P.sub.i1 and P.sub.i2 designate external input terminals of an integrated semiconductor circuit, part of which is constituted of a key input multiplexor circuit KM, a start pulse generator circuit SP, a read control circuit RC, an encoder EC and a memory circuit M as will be hereinafter described. Each of AND gates AG.sub.1 and AG.sub.2 has a multiplexed key signal supplied through the terminal P.sub.i1 or P.sub.i2 to one of its input terminals. To the other input terminals of the AND gates AG.sub.1 and AG.sub.2 are applied respective timing pulses TL and TH shown in FIG. 4 from timing pulse generator PG. An OR gate OG.sub.1 receives outputs of the AND gates AG.sub.1 and AG.sub.2 as its inputs. These gate circuits constitute the key signal multiplexing portion KM. The external input terminals P.sub.i1 and P.sub.i2 are respectively connected to an output terminal OT1 of a numeral key block KB.sub.1 and an output terminal OT.sub.2 of a function key block KB.sub.2 shown in detail in FIG. 3, both the key blocks receiving as their inputs series of digit pulses DT.sub.1 - DT.sub.10 which form a first group of timing pulses (refer to FIG. 4), which are supplied from the timing pulse generator P.G. As stated above, the terminals T.sub.2 and T.sub.4 are supplied with a second group of timing pulses in the form of respective series of sector pulses TL and TH which, as shown in FIG. 4, are provided on the basis of the digit signal DT.sub.1 and are opposite in phase to each other. In FIG. 4, the upper level of each signal represents the logic 1, and the lower level the logic 0.

In FIG. 2 a flip-flop circuit FF.sub.1 is set by an output of the key signal multiplexing portion KM. The flip-flop circuit FF.sub.1 is reset by a timing pulse TH.sup.. DT.sub.10.sup.. BT.sub.4, which is supplied to a terminal T.sub.5 and which is made on the basis of the sector pulse TH, the digit pulse DT.sub.10 and a bit pulse BT.sub.4 provided by the pulse generator circuit PG. An OR gate OG.sub.8 receives as its inputs an output of the flip-flop circuit FF.sub.1 and an auto-clear signal supplied to a terminal T.sub.6. Flip-flop circuits FF.sub.2 and FF.sub.3 are connected in cascade to the output terminal of the OR gate OG.sub.8. An inverter IN is connected to the output end of the flip-flop circuit FF.sub.3, and an AND gate AG.sub.5 receives as its inputs an output signal of the flip-flop circuit FF.sub.2, an output signal of the inverter IN and signals fed to terminals T.sub.7 and T.sub.8. These components FF.sub.1, OG.sub.8, FF.sub.2, FF.sub.3, IN and AG.sub.5 form the start pulse generator circuit SP. The signals supplied to the input terminals T.sub.7 and T.sub.8 of the AND gate AG.sub.5 serve as key input blocking signals during overflow and operation, respectively. Although not shown, the signals applied to terminals T.sub.6, T.sub.7 and T.sub.8 are conventional calculator control signals derived from other portions of the calculator.

AG.sub.6 - AG.sub.16 indicate AND gates each of which receives as its inputs the output of the key signal multiplexing portion KM, an output of the start pulse generator circuit SP and the a corresponding one of the plural series of digit pulses DT.sub.1 - DT.sub.10. The gates AG.sub.6 - AG.sub.16 constitute the key signal reading circuit RC.

The encoder EC receives outputs of the AND gates AG.sub.6 - AG.sub.16 of the key signal reading circuit as its inputs, and converts them into a parallel binary-coded signal of 5 bits. It is composed of five OR gates OG.sub.2 - OG.sub.6. The AND gate AG.sub.16 is additionally supplied with the timing pulse series TH as a control input signal. An AND gate AG.sub.17 receives as its inputs an output of the OR gate OG.sub.6 and the sector pulse series TH. Flip-flop circuits FF.sub.4 - FF.sub.8 are set by outputs of the OR gates OG.sub.2 - OG.sub.5 and an output of the AND gate AG.sub.17, respectively. The flip-flop circuits FF.sub.4 - FF.sub.8 form the memory M. Outputs OT.sub.3 - OT.sub.7 of the respective flip-flops FF.sub.4 - FF.sub.8 are connected to an arithmetic circuit (not shown). As reset inputs R of the flip-flop circuits FF.sub.4 - FF.sub.8, there are provided the output signal of the start pulse generator circuit SP and a clear signal.

The operation of the key input circuits thus constructed will now be explained.

1. Key Blocks KB.sub.1 and KB.sub.2

The respective series of sequential timing pulses DT.sub.1 - DT.sub.10 are fed to the left terminals of the respective keys of the key block KB.sub.1, as seen in FIG. 3. Then, when any key is closed, the timing pulses fed to the closed key appear at the output terminal OT.sub.1 of the key block KB.sub.1. For example, when the numeral key K.sub.5 is closed, the timing pulses of the series DT.sub.5 appear at the output terminal OT.sub.1.

Similarly, when any key of the key block KB.sub.2 is closed, the sequential timing pulses of the series supplied to the closed key appear at the output terminal OT.sub.2.

Accordingly, information as to which keys have been closed represented by the respective series of timing pulses DT.sub.1 - DT.sub.10 appearing at the terminals OT.sub.1 or OT.sub.2. The information is united into the one output in each key block (multiplexed). The key signal thus multiplexed becomes an input signal of the key signal multiplexor circuit KM as explained below.

While the key blocks KB.sub.1 and KB.sub.2 are shown in FIG. 3 to comprise groups of ten switches and eight switches, respectively, the key blocks are not restricted to any particular number of switches. Thus, the group of switches in each key block may comprise an equal number of switches or a different number of switches may be provided in each group as illustrated.

2. Key Signal Multiplexor Circuit KM

The AND circuits AG.sub.1 and AG.sub.2 receive as control signals one of the series of timing pulses TL and TH, respectively. When the timing pulses of the respective series TL and TH become 1, the gates of the respective AND circuits are opened. The OR circuit OG.sub.1 functions to combine the signals which are controlled by the timing pulses TL and TH in this manner.

Accordingly, the key signal generated in the key block KB.sub.1 can pass through the key signal multiplexing circuit KM only when a timing pulse of the series TL is at level 1. The key signal produced in the keyblock KB.sub.2 can pass through the circuit KM only when a timing pulse of the series TH is at level 1.

In summary, the key signal multiplexing circuit KM functions so that the key signals multiplexed by the key blocks KB.sub.1 and KB.sub.2 may be distinguished therebetween in time and so that they may be further multiplexed. Thus far, the information of the respective keys are converted into timing pulses of logical expressions, as illustrated in FIG. 5.

3. Start Pulse Generator Circuit SP

A detailed explanation of the operation will be omitted, and only essential points will be described. The start pulse generator circuit SP separates a start pulse signal for determining the period in which the key signal is read out.

For Example, in the case where the numeral key K.sub.3 is kept depressed, timing pulses of DT.sub.3. TL appear on the output side of the key input signal multiplexing circuit KM during such period. If a pulse signal corresponding thereto is indefinitely fed into, for example, a register of the calculator, the contents of all the digits of the register will become 3. The start pulse signal prescribes the read period for the key signal so as to avoid such inconvenience, and is generated for every depression of a key.

The start pulse signal is employed as a control signal of the read control circuit RC and the memory circuit M hereinbelow described.

4. Read Control Circuit RC

Each time the start pulse is generated, the AND circuits AG.sub.6 - AG.sub.15 of the read control circuit RC detect what key signals are contained in the multiplexed key signal fed from the key signal multiplexing circuit KM. For example, when the output of the AND circuit AG.sub.7 becomes 1, it is made known that the numeral key K.sub.2 or function key K.sub.x has been closed.

The AND circuit AG.sub.16 is especially provided in the embodiment. It detects whether or not the timing pulse DT.sub.1 .sup.. TH is included in the multiplexed key signal, namely, whether or not a decimal point key K. has been depressed. This is intentionally provided to dispose, for convenience' sake, the decimal point key K. along with the numeral keys K.sub.1 - K.sub.0 by considering it as being separate from the function keys.

5. Encoder EC

The encoder EC codes into binary numbers the key signals which have been detected and converted into the timing pulses DT.sub.1 - DT.sub.10 by the read control circuit RC. For example, the key signal converted into the timing pulse DT.sub.2 is coded to the fourth bit of numbers into 0010 by the OR circuits (in the output sequence from the OR circuit OG.sub.5 to the OR circuit OG.sub.2).

Here, the output stage of the encoder EC at the fifth bit of the numbers, namely, the AND circuit AG.sub.17 discriminates between the key signals of the numeral key block KB.sub.1 and the function key block KB.sub.2. More specifically, the AND circuit AG.sub.17 opens its gate only when the timing pulse TH is 1, and does not open its gate when the timing pulse TL is 1. Therefore, the output 1 of the AND circuit AG.sub.17 makes known that a key included in the numeral key block KB.sub.1 has been depressed, while the output 0 makes known that a key located in the function key block KB.sub.2 has been depressed. Accordingly, by way of example, when the numeral key K.sub.2 is depressed, the output of the encoder becomes 00010. When the function key K.sub.x is depressed, it becomes 10010.

The above relations are listed in FIG. 5.

6. Memory circuit M

The key signals thus derived from the encoder EC differ in phase in dependence on the depressed keys, so that the phases need to be made uniform. The memory circuit M is employed for such purpose, namely to store the outputs of the encoder EC.

When it is necessary to clear the contents of the whole calculator, when a key has been erroneously depressed, and when a key is to be depressed anew, the memory circuit M must eliminate key signals already stored therein. To this end, a clear signal from other portions of the calculator and the start pulse signal from the start pulse generator circuit SP are used as the reset input of the memory circuit M.

The relations between the key information and the output signals in the circuit thus constructed, are tabulated as illustrated in FIG. 5.

Although, in the foregoing embodiment, description has been made of the case where the output of the encoder EC is stored in the memory M, the present invention is not restricted to the exemplified case. Even when the memory is arranged between the read control portion RC and the encoder EC, as seen in FIG. 6, a similar effect is achieved.

Although, in the embodiment, description has been made of the case where the two key blocks consisting of the numeral setting key block and the function key block are employed, the invention is not restricted thereto, and three or more key blocks can be used.

As described above, the key input circuit according to the present invention is so constructed that key signals are multiplexed by timing pulses (digit pulses), while outputs of a key block unit divided into blocks of numeral setting keys, function keys, etc., are multiplexed by timing pulses longer in period than the first-mentioned timing pulses. Therefore, the number of input pins to the integrated circuit can be made remarkably small relative to the number of keys. In addition, the number of timing pulses in each series can be made small relative to the number of keys.

In the keys input circuit in FIG. 1, the read control portion composed of a number of gate circuits is required for each key block. Since, in contrast, the key input circuit according to the present invention requires only the single read control portion, it can be brought into an extremely simple construction.