US 3,979,899 AGrant
Digital Display Type Electronic Time Keeper
Issue Date:1976-09-14
•8 Claims
•9 Drawing Sheets
Abstract
A digital display type electronic time keeper is disclosed which has a time standard signal generating source having a crystal oscillating circuit. Means are provided for frequency-dividing the time standard signal, for counting the signal fed from the means for frequency-dividing the time standard signal which is driven by at least one power source, and for decoding the counted data. A display device having a positive dielectric anisotropy twisted effect type nematic liquid crystal is driven by the decoded signal. A booster using two phase signals taken from a part of the frequency dividing means provides a power source for driving the counting means, the decoding means and the display device. A level adjuster matches the output of the frequency-dividing means and the input of the counting means and is disposed therebetween. Additional means are provided for correcting the display data of the display device.
Metadata
Assignees
- Mitsubishi Denki Kabushiki Kaisha
- Citizen Watch Co., Ltd.
Inventors
- Masateru Yoshida
- Yoshio Nakao
Application Information
Application Number:US 564092&
Filing Date:1975-04-01
Priority Date:1974-04-01
Art Unit:211
Classifications
IPC:
G04B 1924
Field of Search:
583403504 A;23 R;23 C;23 BA;50 R336160 LC
Patent Drawings (9 sheets)
Description
Background of the Invention
1. Field of the Invention:
The present invention relates to a digital display type all-electronic time keeper which can be used instead of a conventional mechanical time keeper and a mechanical electronic time keeper.
2. Description of the Prior Art:
Recently, electronic time keepers including watches have been commercialized. A digital display type all-electronic watch using a liquid crystal as a display element has also been commercialized. However, a relatively high voltage has been required for a digital display type all-electronic time keeper with a liquid crystal.
Summary of the Invention
It is an object of the present invention to provide a digital display type all-electronic time keeper which includes a twisted effect type nematic liquid crystal having positive dielectric anistropy (hereinafter referred to as a twist mode liquid crystal) rather than the conventional digital display type liquid crystal time keeper such as the indicator display type crystal watch or the crystal oscillation type DS mode digital liquid crystal time keeper.
The foregoing and other objects are attained in accordance with one aspect of the present invention through the provision of a digital display type electronic time keeper comprising: a time standard signal generating source comprising a crystal oscillating circuit; means for frequency-dividing the time standard signal; means for counting the signal fed from the means for frequency-dividing the time standard signal which is driven by at least one power source; means for decoding the counted data; a display device having a positive dielectric anisotropy twisted effect type nematic liquid crystal which is driven by the decoded signal; a booster using two phase signals taken from a part of the frequency dividing means which provide a power source for driving the counting means, the decoding means and the display device; a level adjuster for matching the output of the frequency-dividing means and the input of the counting means and being disposed therebetween; and means for correcting the display data of the display device.
Brief Description of the Drawings
Various objects, features and attendant advantages of the present invention will be more fully appreciated as the same becomes better understood from the following detailed description of the present invention when considered in connection with the accompanying drawings, in which:
FIG. 1 is a block diagram of a digital display type all-electronic watch in accordance with the present invention;
FIG. 2 is a frequency division circuit of FIG. 1 which provides an output of 64 Hz in nine steps;
FIG. 3 is a circuit diagram of one embodiment of the main electronic circuit of the digital display type all-electronic watch using a twist mode liquid crystal;
FIG. 4 is a block diagram of one embodiment of the time driving integrated circuit of FIG. 3; and
FIGS. 5A, B, C, D, E and F comprise a circuit diagram of one embodiment of the time driving integrated circuit of FIG. 4.
Brief Description of the Preferred Embodiments
Reference will now be made to the drawings wherein like reference numerals designate identical or corresponding parts throughout the several views.
The numeral reference 1 designates a crystal oscillating circuit; 2 designates a frequency division circuit; 3 designates a potential level matching device for connecting the frequency division circuit 2 and a time driving integrated circuit 6; 4 designates a booster for driving a display device 7; 8 designates an outer operative switch; and 9 designates a power source.
The frequency divider used for the electronic watch of the invention is shown in FIG. 2 and has nine steps for frequency dividing to provide a signal having 64 Hz.
The crystal oscillating circuit has a tuning fork type super miniature crystal oscillator Q.sub.15 having a frequency of 32768 Hz. The crystal oscillating circuit 1 shown in FIG. 3 is finely adjusted by a frequency adjusting capacitor C.sub.T so as to correspond to the positive frequency.
An oscillation inverter In.sub.1 is molded in one tip as an oscillation frequency division integrated circuit 2 together with output inverters In.sub.2, In.sub.3 and In.sub.4 from frequency divider F.sub.D1, a waveform shaping device S.sub.H1, a transistor level-adjuster Tr.sub.a ; and a booster 4. The tip is assembled in the watch.
The frequency divider F.sub.D1 is a flip-flop circuit as shown in FIG. 2 wherein nine steps for 1/2 frequency division are connected in series to output a signal having 64 Hz. The output signal having 64 Hz is input into the waveform shaping device S.sub.H1 to form fine pulses whereby the transistor level adjuster Tr.sub.1 is driven. The transistor Tr.sub.1 receives the voltage boosted to about 5 volts by the booster integrated circuit 4.
The frequency divider F.sub.D1 side is matched to the time driving integrated circuit 6 by the transistor Tr.sub.1 together with the resistor R.sub.64 and the MOS-R R'.sub.64. The frequency of 1024 Hz in the 5th step of the frequency divider FD.sub.1 is input through the inverters In.sub.3, In.sub.4 to the booster circuit 4. The booster circuit 4 is a Schenkel type booster circuit which is driven by two phase input signals .phi. 1024 and .phi. 1024 to charge about 5 volts of DC voltage in the capacitor Css by four times voltage to provide the power source for driving the time driving integrated circuit 6 and the twist mode liquid crystal having positive dielectric anisotropy. The booster integrated circuit 4 is formed by molded hybrid integrated circuits and is assembled in the watch with the other integrated circuit tip.
The frequency divider F.sub.D1 side is matched to the time driving integrated circuit 6 side by the transistor Tr.sub.1, the resistor R.sub.64 and the MOS-R R'.sub.64.
The pulse having 64 Hz is input through the inverters In.sub.5, In.sub. 6 to the time driving integrated circuit 6 to display the time on the display device 7.
In the switch operating part 8 for the outer operating device, a switch at terminal R.sub.6 .degree. operates date displays V, VI in the display device 7; a switch at terminal R.sup.5 .degree. provides quick correction of date displays V, VI; a switch at terminal R.sub.3 .degree. provides quick correction of the time display I, II; a switch at terminal R.sub.2 .degree. provides quick correction of minutes display III, IV; a switch at terminal R.sub.1 .degree. provides zero setting of second display V, VI; a switch at terminal R.sub.0 .degree. operates to set the time starting point and switches at terminal T.sub.1 and T.sub.2 operate to erase all displays.
The lead lines of the time driving integrated circuit 6 are connected to the corresponding parts of the symbols of I, II, III, IV, V, VI and VII; the seven segments of the display device and the symbols of the week day display device.
FIG. 4 is a block diagram of the inner circuit of the time driving integrated circuit 6. The operation of the circuit 6 will now be described. As stated above, the signal of the frequency divider of FIG. 3 is applied through the level adjuster 3 and the inverters In.sub.5, In.sub.6 to the time driving integrated circuit 6 as fine clock pulses having 64 Hz. In the time driving integrated circuit 6, the signal is converted to 1 Hz by a frequency division circuit 11; is fed through a second counter circuit 12; is input to a minute counter circuit 13 as a minute signal; is input to an hour counter circuit 14 as an hour signal output; and is further input to the date counter circuit 15 and the week day counter circuit 16 as a date signal output.
The outputs of the counter circuits for second, minute, hour, date, etc. are applied to a second-date decoder circuit 17; an hour decoder circuit 18; and the minute decoder circuit 19 and further to a minute driving circuit 20; an hour driving circuit 21; a second-date driving circuit 22 and a week day driving circuit 23 which respectively correspond to the decoder circuits.
The driving circuits drive the display device by a signal having 32 Hz which is frequency-divided by flip-flop 24. The signal applied from input control part 25 as a result of the switch signal applied from the outer operating part 8 is fed to the correction circuit of each of the counter circuits corresponding to the switch signals to change the counting data and to correct the display of the display device.
FIGS. 5 A, B, C, D, E and F comprise a circuit diagram of one embodiment of the time driving integrated circuit 6 of FIG. 4. The embodiment will be described in detail with reference to the drawings.
The pulse signal of 64 Hz fed from the inverters In.sub.5, In.sub.6 is frequency-divided to provide 1 Hz by frequency divider 11 which comprises flip-flops FF.sub.1.sub.- - FF.sub.15. The 1 Hz signal is applied to the line L.sub.101. The signal having 1 Hz is counted by the second counter 12 which comprises flip-flops FF.sub.16 -FF.sub. 21 and the counted value is demodulated by the second-date decoder circuit 17 to the display signal to drive the second-date driving circuit 22.
The driving circuits D.sub.1 - D.sub.7 of the driving circuit 22 drive the ten figure of the second display segment of FIG. 3. The terminals ADs. DAs, Bs, Cs, Ds, Es, Fs, and Gs are connected to the corresponding references of the second display segments V of FIG. 3. In like manner, the driving circuits D.sub.8 - D.sub.13 drive the second one figure of the seven second display segments.
The terminals As', Ds', Bs', Cs', Es', Fs' and Gs' are connected to the corresponding references of the second display segments of FIG. 3. The terminal ADs and DAs are commonly connected. In the minute display circuit, the one minute signal fed from the flip-flop F.sub.22 of the second counter 12 is fed through the NOR gate N.sub.1 of FIG. 5A and the corrective circuit 301 to the minutes counter 13 which comprises the flip-flops FF.sub.22 - FF.sub.29. The signal is converted to the minute signal by the decoder 19 to display the minute figures III and IV of FIG. 3.
The output terminals of the minute driving circuits 20 of FIG. 5B correspond to the references of the seven minute display segments of FIG. 3.
The outputs of the counter 19 for the minute figure drive the driving circuits D.sub.21 - D.sub.26. The display signal of the minute ten figure is demodulated by the decoder 19" . The driving circuits D.sub.21 - D.sub.26 are respectively connected to the output terminals B.sub.M, C.sub.M, F.sub.M, E.sub.M, G.sub.M, AD.sub.M and DA.sub.M. The terminals AD.sub.M and DA.sub.M for driving the segments of the symbols of the minute ten figure III of FIG. 3 are commonly utilized.
The decoder 19' demodulates the minute one figure to drive the driving circuits D.sub.14 - D.sub.20 which are connected to the corresponding output terminals A.sub.M ', B.sub.M ', C.sub.M ', D.sub.M ', E.sub.M ', F.sub.M ' and G.sub.M ' which are connected to the corresponding references of the seven segments A.sub.M ', B.sub.M ', C.sub.M ', D.sub.M ', E.sub.M ', F.sub.M ' and G.sub.M ' of the minute one figure of FIG. 3.
The corrective circuit 301 is for one second quick correction for the minute display so that the terminal R.sub.2 .degree. of the input control part 25 is in high potential to keep the line L.sub.104 in low potential to turn off the gate G.sub.12. The one second signal fed from the line L.sub.102 is taken from the line L.sub.109 as the small duty signal having 1 Hz and the signal is applied to the counter 13 to provide the one second quick correction for the minute display.
The minute signal fed from the counter 13 is passed through the corrective circuit 302 to be counted in the counter 14. The signal is demodulated by the hour decoder 18 to drive the hour driving circuit 21. The output terminals A.sub.H, B.sub.H, C.sub.H, D.sub.H, E.sub.H, F.sub.H and G.sub.H connected to the hour driving circuits D.sub.27 - D.sub.34 are connected to correspond to the references A.sub.H, B.sub.H, C.sub.H, D.sub.H, E.sub.H, F.sub.H and G.sub.H of each segment of the seven segments II of FIG. 3. The output terminals K.sub.H of the driving circuit D.sub.27 are connected to correspond to the reference K.sub.H of the segment I.
The output of the hour counter 14 is fed through the corrective circuit 303 to the date counter 15. The signal of the one figure is demodulated in the decoder 17 and the signal is fed to the driving circuits D.sub.1 - D.sub.7. The driving circuit terminals As', Bs', Cs', Ds', Es', Fs' and Gs' are connected to the corresponding references of As', Bs', Cs', Ds', Es', Fs' and Gs' of the segments to display the one figure of the date.
The signal for displaying the ten figure of the data fed from the date counter 15 is demodulated in the decoder 17" to drive the driving circuits D.sub.8 - D.sub.13. The driving circuit terminals Bs, Cs, Es, Fs, Gs, ADs and DAs are connected to the corresponding references of the seven segments V of FIG. 3 to drive the ten figure. The terminals ADs, DAs are commonly connected.
The terminal P.sub.1 is normally connected to the power voltage V.sub.DD and the terminal PM is commonly connected to the segment for displaying the PM of FIG. 3. When the decoder 21 provides the display of 12 o'clock by the signal of the hour counter 14, the driving signal is simultaneously applied to the AM terminal so that the AM segment and the frame AM' of FIG. 3 are commonly turned on. Accordingly, the indication of before noon is the AM display with the frame.
The signal fed from the date counter 15 is passed through the corrective circuit 303 to the ring counting circuit 16 and is fed to the week day display signal driving circuit 23. The driving circuit terminals Sun., Mon., Tue., Wed., Thu., Fri., and Sat. are connected to the corresponding week day of the week day display of FIG. 3 to provide a cycle drive.
The colon dot display of FIG. 3 turns on and off for 1 second by feeding the one second signal of the frequency divider 15 from the terminal col. through the line L.sub.101 and the driving circuit D.sub.37. The circuit diagram of the time driving integrated circuit 6 for driving the display device of FIG. 3 and the operation thereof and the signal path have previously been described.
The terminals and circuits 25, 25' and 25" for operating and controlling the display device as the time keeper are shown in FIG. 4 and FIG. 5. These terminals are connected to the corresponding terminals 8 of FIG. 3.
During normal operation, the terminals R.sub.o .degree., R.sub.1 .degree., R.sub.2 .degree., R.sub.3 .degree., R.sub.4 .degree., R.sub.5 .degree. and R.sub.6 .degree. are in the OFF state and the terminals R.sub.0, R.sub.1, R.sub.2, R.sub.3, R.sub.4 and R.sub.5 are in the high potential state. When the terminal R.sub.0 .degree. is switched to high potential from the normal work state, the line L.sub.105 is switched to low potential whereby the voltage circuits 301, 302, 303 and 304 are connected to the line L.sub.105.
In the corrective circuit 301, when the line L.sub.105 is switched to low potential, the gate G.sub.11 applies the signal having 64 Hz fed from the line L.sub.111, as a quick correction signal, to the minute counter 13 to provide a quick correction of the correct time of the minute counter. The output of the minute decoder 19 is fed to the driving circuit 20 to correct the seven minute display segments III and IV to display the 00 minute.
The signal of the line L.sub.105 is fed through the corrective circuit 302 to enable the gate G.sub.22 to apply the signal having 64 Hz fed through the line L.sub.112 to the hour counter 14 to provide the quick correction of the hour counter 14. The signal of the hour counter is applied to the decoder 18 to correct the seven segments I and II connected to the driving circuits D.sub.27 - D.sub.34 to display 12 o'clock.
At the same time, the line L.sub.113 connected to the flip-flop FF.sub.t of the counter is switched to low potential to drive the AM display driving circuit D.sub.35 to drive the AM display segments of FIG. 3. The signal fed from the line L.sub.105 is applied to the corrective circuit 34 to enable the gate G.sub.14 to apply the quick correction signal having 64 Hz fed from the line L.sub.14 to the decoder 17 connected to the date counter 15 to correct the segments to display the 31 date. The signal fed from the line L.sub.105 enables the gate G.sub.17 of the corrective circuit 303 to apply the quick correction signal having 64 Hz fed from the line 107 to the ring counter 16 to display Sunday.
When the terminal R.sub.1 is switched to low potential by the input control switch terminal R.sub.1 .degree., the low potential signal of the line L.sub.102 is applied to the corrective circuits R.sub.S1 - R.sub.S10 for the flip-flops FF.sub.13 - FF.sub.21 to reset the flip-flops to zero. Thus, the flip-flops of shorter than 1/8 second are reset, the zero signal is applied to the decoder and the driving circuit 22 is driven to reset the second display to 00 second.
When the control switch terminal R.sub.2 .degree. is turned on, the line L.sub.108 is switched to low potential to enable the gate G.sub.12 of FIG. 5 to apply the one second signal fed from the line L.sub.109 to the minute counter 13 to obtain the quick correction of the minute display for 1 second.
When the control switch terminal R.sub.3 .degree. is turned on, the signal fed from the line L.sub.14 enables the gate G.sub.13 of FIG. 5 to apply the one second signal fed from the line L.sub.109 to the counter 14 to obtain the quick correction of the hour display for 1 second.
When the control switch terminal R.sub.4 .degree. is turned on, the signal fed from the line L.sub.15 enables the gate G.sub.15 of FIG. 5 to apply the one second signal fed from the line L.sub.109 to the counter 15 to obtain the quick correction of the date display for 1 second.
When the control switch R.sub.5 .degree. is turned on, the signal fed from the line L.sub.16 is applied to the gate G.sub.16 to enable the gate to apply the one second signal fed from the line L.sub.109 to the ring counter 16 to obtain the quick correction of the week day display for 1 second.
When the terminal R.sub.4 of the input control part 25" is turned on, the line L.sub.20 in the date-second decoder 17 is switched to low potential and the signal fed from the counter 15 is only demodulated to display the date display. When the terminal R.sub.4 .degree. is turned on in this condition, the quick correction of the date display is obtained. When the control terminal R.sub.6 is switched to low potential under the condition of low potential of the terminal R.sub.4 of the input control part 25", the line L.sub.21 is switched to low potential and the line L.sub.26 is switched to high potential whereby the decoder 17 demodulates the second display signal fed from the second counter 12 to display the second in the seven segment display V, VI of FIG. 3. That is, when the terminal R.sub.4 is at a high potential, the date display is obtained regardless of the condition of the terminals R.sub.1, R.sub.6 .degree. of FIG. 5.
When the terminal R.sub.4 is at a low potential, the quick correction of the date display for 1 second is obtained by the signal fed from the line L.sub.109. In this case, when the terminal R.sub.6 .degree. is at a low potential, the date display is switched to the second display. When the terminal R.sub.1 is at a low potential, the line L.sub.21 is switched to a low potential and the second display is reset to zero.
The terminals T.sub.1, T.sub.2 of the input control part 25' are respectively a terminal for testing and a terminal for display erasing. During the normal operation, both terminals T.sub.1, T.sub.2 are at a high potential and the signal having 32 Hz fed from the line L.sub.30 is applied to the driving circuits. The liquid crystal driving segments are driven by the AC signal having 32 Hz fed from the decoders.
When one of the terminals T.sub.1, T.sub.2 is at a low potential, one of the lines L.sub.31, L.sub.32 is at a high potential and the other is at a low potential whereby the driving circuit is driven by DC power to test it. When both of the terminals T.sub.1, T.sub.2 are at a low potential, both of the lines L.sub.32, L.sub.31 are at the same potential level so that the driving circuit is not actuated to thereby prevent current consumption. That is, the time keeping functional circuit is operated but the display circuit which causes high current consumption is in its OFF state. The functional operation of the time driving integrated circuit of FIG. 3 has previously been described.
The mechanism of the digital time keeper of the invention has an integrated circuit having multi-functional display functions for displaying hour, minute, second as well as AM or PM, date and week day at high efficiency so that the time keeper can be made rather compact. Further, the power source can be a solar battery and a chargeable secondary battery or a combination of a solar battery and a commercial battery.
Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described herein.
Claims
What is claimed as new and desired to be secured by Letters Patent of the United States:
1. A digital display type electronic time keeper comprising: a crystal oscillating circuit for generating a time standard signal, a frequency division circuit for frequency dividing the time standard signal, a time driving integrated circuit for counting the frequency divided time standard signal from the frequency division circuit and for decoding the counted frequency divided time standard signal, a potential level matching device for matching the output of the frequency division circuit and the input of the time driving integrated circuit, a display device driven by the decoded counted frequency divided time standard signal comprising a positive dielectric anistropy twisted effect type nematic liquid crystal, a booster for driving the time driving integrated circuit and the display device from two phase signals from the frequency division circuit, an outer operative switch for correcting the display device, a power source for driving the crystal oscillating circuit and the frequency division circuit, means connecting the input of the crystal oscillating circuit to a first output of the power source, means connecting a second input of the frequency division circuit to a second output of the power source, means connecting the output of the crystal oscillating circuit to a first input of the frequency division circuit, means connecting a first output of the frequency division circuit to the input of the booster, means connecting a first output of the booster to a second input of the time driving integrated circuit, means connecting a second output of the booster to a second input of the display device, means connecting a second output of the frequency division circuit to the input of the potential level matching device, means connecting the output of the potential level matching device to a first input of the time driving integrated circuit, means connecting the output of the outer operative switch to a third input of the time driving integrated circuit, means connecting the output of the time driving integrated circuit to a first input of the display device, the display device comprising seven separate segment type displays for hour and minute; a single display for selectively showing second or date by seven segment displays under the selective switching control of said outer operative switch; additional displays for week day, AM, PM; and a colon dot display which turns on and off for one second between the displays of hour and minute.
2. The digital display type electronic time keeper according to claim 1 wherein the crystal oscillating circuit, the frequency division circuit, the potential level matching device and the time driving integrated circuit comprise C-MOS integrated circuits and the booster comprises a Schenkel type hybrid integrated circuit.
3. The display type electronic time keeper according to claim 1 wherein the frequency division circuit comprises nine steps and generates a 64 Hz signal.
4. The display type electronic time keeper according to claim 1 wherein the crystal oscillating circuit comprises a tuning fork miniature crystal oscillator having a frequency of 32768 Hz.
5. The display type electronic time keeper according to claim 1 wherein the booster comprises molded hybrid integrated circuits.
6. The display type electronic time keeper according to claim 1 wherein the power source comprises a solar battery.
7. The display type electronic time keeper according to claim 1 wherein the power source comprises a solar battery and a chargeable secondary battery.
8. A digital display type electronic time keeper comprising: a crystal oscillating circuit for generating a time standard signal, a frequency division circuit for frequency dividing the time standard signal, a time driving integrated circuit for counting the frequency divided time standard signal from the frequency division circuit and for decoding the counted frequency divided time standard signal, a potential level matching device for matching the output of the frequency division circuit and the input of the time driving integrated circuit, a display device driven by the decoded counted frequency divided time standard signal comprising a positive dielectric anisotropy twisted effect type nematic liquid crystal, a booster for driving the time driving integrated circuit and the display device from two phase signals from the frequency division circuit, an outer operative switch for correcting the display device, a power source for driving the crystal oscillating circuit and the frequency division circuit, the outer operative switch comprising: a first control switch for displaying the initial conditions 00 seconds, 00 minutes, hour 12 AM, day 31 and Sunday, a second control switch for controlling seconds, a third control switch for controlling minutes, a fourth control switch for controlling hours, a fifth control switch for controlling dates, a sixth control switch for controlling week days, a seventh control switch for controlling date-second displays, an eighth control switch to erase all displays, the fifth control switch when activated causing display of a date regardless of the conditions of the second and seventh control switches, the fifth control switch when not activated causing display of seconds regardless of the condition of the seventh control switch when the second control switch is in its active state, the seventh control switch being capable of changing the date display or second display when the second and the fifth control switches are non-activated.
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