High Band Width Emitter Coupled Logic Gate

1. Field of Invention

This invention relates to a logic gate, and more particularly to improved high speed emitter coupled logic (ECL) gate.

2. Description of the Prior Art

Many prior art ECL gates are data bit rate limited to somewhere around 250 megabits per second. These rates are unacceptable in high speed communication applications, for example in certain pulse code modulating environments. One attempt to increase the speed of ECL gates is directed towards varying circuit impedances in order to reduce current swings in the emitter-follower output transistor during switching. Another situation increases power dissipation and moreover speed improvement is practically limited by design considerations. Another approach is to employ sophisticated processing and device techniques which essentially minimizes collect-to-substrate capacitance in order to improve rise and fall times of the generated signal. In addition to being costly and more difficult to control these approaches are also performance limited when it is desirous to improve the data bit rate by an order of magnitude over that now obtainable with known prior art ECL gates. For example, certain applications require a 600 megabit per second data rate.

It is therefore an object of the invention to provide an improved high speed, high band width ECL gate capable of operating in the 600 megabit per second data range.

Another object of the present invention is to provide an improved ECL gate wherein AC beta roll off is minimized, thus significantly improving rise and fall times, and cross talk also is reduced.

Another object of the present invention is to provide an improved ECL gate capable of operating at significantly higher data bit rates without corresponding output signal attenuation.

In accordance with the aforementioned objects, the present invention provides an ECL logic gate wherein switchable current sinks connected to the emitter terminal of the emitter-follower output transistor maintain a substantially constant current flow through the emitter-follower output transistor during switching of the logic gate.

FIG. 1 is a schematic drawing illustrating a basic ECL gate and the switchable current sink circuits for maintaining a substantially constant current flow through the emitter-follower output transistors at both the in-phase and out-of-phase sides of the ECL gate.

FIG. 2 shows a DC and power transfer characteristic curve illustrating the rise-fall time improvement obtainable with the present invention.

Now referring to FIG. 1, it illustrates a conventional emitter-follower coupled logic gate 10 connected to a switchable current sink means 12 for improving the rise-fall time of the logic signals generated at output terminals 14 and 16 constituting the in-phase (OR) output terminal for providing a logic signal A+B and the out-of-phase (NOR) output terminal for providing a logic signal A+B in response to input signals A and B applied to input terminals 18 and 20.

The ECL gate 10 includes a plurality of input switching transistors 22 and 24 connected between a first common emitter node 26 and a collector voltage switching node 28. The base terminals of the input switching transistors 22 and 24 are connected to the input terminals 18 and 20, respectively. A first current source comprising transistor 30 supply voltage V.sub.CS and resistor 32 is connected between node 26 and a negative supply voltage V.sub.EE connected to terminal 34, which in the preferred embodiment is -5.2 volts. A load impedance or resistor 40 is connected between node 28 and the positive voltage supply V.sub.CC connected to common line 42 by means of terminal 44. In the preferred embodiment the voltage V.sub.CC is ground potential.

An emitter-follower output transistor 46 is connected at its base terminal to node 28 and at its collector terminal to line 42 by means of line 48. The emitter-terminal of transistor 46 is connected to output terminal 16 which in turn is connected to a line impedance or resistor 51 and voltage supply V, 50 ohms and -2.0 volts in the preferred embodiment. A reference switching transistor 52 is connected at its emitter terminal to node 26 and at its collector terminal to a second voltage switching node 54. The base of transistor 52 is connected to a reference supply voltage V.sub.BB of approximately -1.30 volts in the preferred embodiment. An impedance or load resistor 56 is connected between node 54 and line 42. In a similar manner, the OR or in-phase output signal A+B logic output signal is provided at the emitter terminal of an output emitter-follower transistor 60 having its base connected to node 54, its collector terminal connected to line 42, and its emitter terminal connected to output terminal 14. Further, a line impedance or resistor 61 and supply voltage V also is connected to the output terminal 14.

The switchable current sink means 12 comprises a pair of circuits each respectively connected between a voltage switching node and the emitter terminal of an emitter-follower output transistor. Connected between node 28 and the emitter terminal of transistor 60 is a voltage translating circuit comprising transistor 70 and diode 72. The cathode terminal of diode 72 is connected to the reference voltage V.sub.EE by means of resistor 74 and line 76. A current sink comprising transistor 80 and resistor 82 is connected between the cathode of diode 72 and the emitter terminal of transistor 60 by means of lines 84 and 86, respectively. The bottom end of resistor 82 is connected to a supply voltage V.sub.EEO of approximately -3.2 volts in the preferred embodiment.

Similarly, connected between voltage switching node 54 and the emitter terminal of emitter-follower output transistor 46 is a voltage translating circuit comprising transistor 90 and diode 92. The cathode terminal of diode 92 is connected by means of resistor 94 to reference voltage V.sub.EE by means of line 96. Also, the diode 92 is connected by means of line 98 to a current sink comprising transistor 100 and resistor 102. The bottom of resistor 102 is connected to reference voltage V.sub.EEO. The collector terminal of transistor 100 is connected to the emitter terminal of emitter-follower output transistor 46 by means of line 106.

In a conventional ECL gate the collector current in the emitter-follower output transistor 60 switches between 22 milliamps in an up or binary one level to approximately 5 milliamps in the down or binary zero level. Due to this large current change, the AC beta roll off causes the rise and fall times associated with the output logic signal generated at terminal 14 to exhibit serious rounding of the edges during the transition from one level to another level as illustrated by curve 110 in FIG. 2. At the midpoint in the swing the effect is not as significant but the entire ramp rate still is deleteriously affected. This problem has limited the data bit rate to somewhere in the range of 250 megahertz.

With either logic input signals A or B at a binary up or one level either transistor 22 or 24 is conducting and transistor 52 is off or nonconducting thus placing the base of emitter-follower output transistor 60 at a relatively up or high state and, transistor 60 is conducting. With an impedance load of 50 ohms connected to a -2.0 volt supply, the current through transistor 60 is approximately 22 milliamps. Simultaneously, the base of transistor 70 is low or at a relatively down level and thus very little current flows through resistor 82. Assuming that the logic input signal is going to a logical zero or down level, then transistor 52 begins conducting thus pulling the base of transistor 60 to a low state. Accordingly, the emitter of transistor 60 begins going low thus demanding less current through its collector. However, the base of transistor 70 is going high so as to raise the base potential of transistor 80 to a high state. Thus the collector of transistor 80 requires more current. When the logical input signal completes its transition, transistor 52 is fully conductive and the base of transistor 60 is low. The line impedance or resistor 61 requires approximately 5 milliamps assuming a voltage -V to approximately -2.0 volts. However, with both the base terminals of transistors 70 and 80 at a high state and with the appropriate selection of the value of resistor 82, transistor 80 requires a collector current of approximately 17 milliamps which is supplied from transistor 60 via line 86. Accordingly, 5 milliamps is supplied for the load and 17 milliamps for the collector current of transistor 80. Thus, the collector current of transistor 60 remains at approximately 22 milliamps. Naturally, converse operation occurs when the input again goes to a logical one or up state and an identical operation applies to the emitter-follower transistor 46.

With relatively constant currents being supplied to the emitter-follower transistors, the circuit is always operating in a constant F.sub.t region and the output rise and fall times will have a much sharper transition as illustrated by curve 112 in FIG. 2. Moreover, the higher repetition or data rates are achievable without output signal attentuation. In cases where only one side is brought out of the logic gate an ancillary advantage occurs, the current in the V.sub.CC line essentially remains constant, this results in less signal being fed to other portions of the chip or die and thus reduces the cross talk to other outputs not being switched at the same time.