US 3,974,517 AGrant
Metallic Ground Grid for Integrated Circuits
Issue Date:1976-08-10
•4 Claims
•2 Drawing Sheets
Abstract
A metallic ground conductor grid applied over a planar isolation barrier in an integrated circuit provides a low resistance ground. An insulating layer, formed over the ground conductor, has apertures therein for interconnecting selected areas of the integrated circuit to the ground conductor grid.
Metadata
Assignee
- Harris Corporation
Inventors
- Thomas J. Sanders
- Jacob A. Davis
- William R. Morcom
Application Information
Application Number:US 5616778
Filing Date:1975-03-25
Priority Date:1973-11-02
Art Unit:254
Classifications
IPC:
H01L 2704
Field of Search:
35740;46;48;54;65;71
Patent Drawings (2 sheets)
Description
Background of the Invention
1. Field of the Invention
The present invention relates generally to integrated circuits and more specifically to a low resistant metallic ground grid for integrated circuits.
2. Description of the Prior Art:
The ever-increasing complexity of integrated circuits has lead to large chip sizes. One problem with these large circuit areas is the resistant drop in the ground metallization line between the ground pad and all other ground points in the circuit. Many times the ground line's resistance is significant enough to cause ground voltage drop problems in some junction isolated circuits.
In junction isolated circuits having substantial amounts of current flowing in the substrate, the ground line is only part of the consideration. The current flowing in the substrate has to also flow through a highly resistive isolation diffusion until it can get into the metallized ground line through conveniently placed ground tap, which is common to the metallized ground line and the isolated diffusion.
The prior art provides generally a ground path by diffusion into the semiconductive body of the integrated circuit or by a metal ground conductor formed on an insulating layer on the surface of the integrated circuit. In order to keep the resistance per square relatively small, the diffused ground paths are generally made wide, thus reducing the packing density of the integrated circuit. The metal ground conductors of the prior art are difficult to form on uneven surfaces of the integrated circuit without breaking or having pinholes and without shorting out other portions of the integrated circuit through imperfections in the insulating layer. Also, the metal ground conductor of the prior art requires the formation of a surface insulating layer at all points at which metal interconnects must crossover. This is not only responsible for the increase in expense of the integrated circuit, but also adds restraint to the circuit layout.
Summary of the Invention
The method of the present invention provides a metallic ground grid where the resistive drop is due to the isolation diffusion and can be nearly reduced to zero while at the same time various parallel paths are provided which can aid in carrying current to the ground path. According to the present invention, a pattern is etched in the oxide over the diffused isolation regions using a photoresist mask to expose the isolation regions of an integrated circuit. With the resist still on the oxide layer, the metal conductor is formed on the integrated circuit. The conductor is to be thinner than the combined oxide and photoresist layers. After stripping the photoresist along with metal that has been deposited thereon, the remaining conductor is partially anodized so that an insulating layer covers the conductor at least to the remaining height of the oxide layer. Apertures are then formed in the anozided layer and the oxide layer on the remainder of the integrated circuit so that conductors can be formed to connect selected areas of the integrated circuit to the ground grid with a minimum ground line resistance.
Objects of the Invention
An object of the present invention is to provide a low resistance ground grid for integrated circuits.
It is another object of the present invention to provide a method for forming a low resistance ground grid for integrated circuits.
It is a further object of the present invention to provide a metallic ground grid which may be connected to selected areas of an integrated circuit and require no additional steps of producing an insulated layer thereon for conductor crossovers to the integrated circuit.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.
Brief Description of the Drawings
FIGS. 1-5 are cross-sectional views of successive stages of development in the fabrication of the metallic ground grid of the present invention in an integrated circuit.
Description of the Preferred Embodiment
Referring to FIG. 1, a transistor having a base 10 and an emitter 12, a collector 14 is shown being formed in a spaced apart planar region 16 formed in a substrate 18. A plurality of the planar regions 16 having a conductivity type N are shown separated by isolation barriers or regions 20 of P+ conductivity type, also formed in the P type substrate 18. The planar surface of the integrated circuit is coated with a non-conductive material 22 such as silicon dioxde (but any relatively smooth, non-conductive material will work for this purpose). The silicon dioxide can be formed on the silicon substrate by oxidizing the silicon in a steam ambient at 1,100.degree.C. for about an hour. As depicted in FIG. 1, the integrated circuit is at a point where all the diffusion for semiconductive devices are complete and a circuit is ready for a normal contact aperture mask process. Though only a transistor is shown in the present drawings, it is to be understood that the remaining regions 16 each have a semiconductor device formed therein as needed for a designed integrated circuit.
Instead of the normal contact aperture formation steps, the pattern for the metallic ground grid is defined. Preferably this is achieved by the application of a photoresist emulsion and its delineation. A positive photoresist such as Shipley can be used and has provided excellent results with glass substrates. Photoresist may be applied by brushing, dipping, spraying, spinning or other coating techniques. Once applied, the photoresist is exposed using a mask and developed so as to define the pattern of the metallic ground grid. The photoresist layer 24 and the non-conductive layer 22 are etched to form apertures grid pattern 26 above the isolation barrier regions 20 as shown in FIG. 2.
With the photoresist still on the integrated circuit, a layer 28 of conductive material is deposited in apertures 26 to a thickness less than the thickness of the combination of non-conductive layers 22 and the photoresist layer 24. This insures the discontinuity in the conductive material layer 28 on top of the photoresist 24 and the conductor 28 in the apertures 26. Preferably, the conductive material is aluminum evaporated onto the substrate at room temperature. Other conductive metals may be used and deposited by other well known methods of the prior art.
The photoresist layer 24 and the conductive layer 28 thereon are removed chemically. Using the Shipley photoresist, acetone is generally used to chemically remove or strip the photoresist. A contact baked at 400.degree.C. for 1 hour is performed to insure proper adherence of the conductor to the doped silicon planar surface of the isolation barrier 20. The conductive grid has a thickness of approximately 5000 angstroms and a resistance of 0.1.OMEGA./square.
The aluminum pattern remaining in apertures 26 is then partially anodized so that a layer of aluminum oxide 30 covers the non-anodized aluminum conductor 28. The anodization is performed at 100 volts in a solution of oxalic acid. As shown in FIG. 3, the metal oxide layer 30 fills the remainder of aperture 26 and forms a generally planar surface with the insulative layer 22. The metal oxide layer 30 provides an added adequate insulator for allowing interconnecting metals to pass over the isolation regions without making contact with the ground grid deposited as described above. The integrated circuit is now ready to have the contact apertures opened.
The integrated circuit is processed through a conventional photoresist operation, during which contact apertures in selected regions of the integrated circuit as well as selected areas above the metallic grid 28 are formed in a layer of photosensitive material coated on the planar surface defined by insulators 22 and 30. The contact apertures delineated by the photoresist material are formed by exposing the photoresist coated slice to a hydrofluoric acid etch solution while will remove all the oxide from those areas of the wafer not coated by the photoresist. The photoresist is then removed in a series of baths in J-100 stripper. The exposed areas left by the above photoresist etch are those in which the interconnections are made between selected areas of semiconductive devices in the integrated circuit and the metallic ground grid 28. As shown in FIG. 4, the apertures 32 and 34 expose selected areas of metallic ground grid 28 and apertures 36, 38 and 40 expose selected areas to base 10, emitter 12 and the collector 14 of the illustrated transistor.
The final step includes depositing and delineation, by conventional means of the connector and interconnector metals of the integrated circuit. Generally, a layer of an aluminum of approximately 10,000 angstroms is applied; however, other conductive metals may be used. Preferably a direct photoresist technique is used to delineate the aluminum connectors and interconnectors. The aluminum is evaporated over the entire substrate, followed by a coat of photoresist. The photoresist is exposed through a mask and etched to achieve the desired pattern of the connectors and interconnectors as shown in FIG. 5 as layer 42. As specifically shown, the base of the transistor 10 is connected to the ground metallic grid 28 by the aluminum layer 42 filling apertures 32 and 36, respectively, and crossing the insulative layers 22 and 30.
The metal grid pattern 28 formed on the planar surface above isolation barriers 20 provides an extensive low resistive ground pattern which alleviates undesired resistive ground drops in integrated circuits. With the application of the grid 28 prior to the formation of contact apertures in the integrated circuit, the need for the formation of insulative crossover regions on the semiconductor at select locations is eliminated. The formation of the metal oxide layer 30 over the whole surface of the metallic ground grid 28 provides a more effective insulator and reduces the number of steps required to selectively insulate the metallic ground grid 28. Thus, the process as described above produces a low resistive metallic ground grid which is economical to produce.
Although the invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only and is not intended to be taken by way of limitation. The semiconductive transistor shown is but an example of the type of semiconductor devices which may be formed in junction isolated regions in a planar integrated circuit. The metallic ground grid was preferably formed with aluminum because of its excellent adherence characteristics to silicon, yet other conductive metals may be used. Similarly, the formation of silicon dioxide and aluminum oxide as the insulating layers are but expedient examples of insulators and other insulators well known in the art may be used. The spirit and scope of the invention is limited only by the terms of the appended claims.
Claims
What is claimed:
1. A semiconductor integrated circuit comprising: a body of semiconductor material of a first conductivity type having a first planar surface; a plurality of spaced apart planar regions adjacent said first surface, each of a second conductivity type, opposite said first conductivity type, said regions including semiconductive components; isolation barriers of semiconductor material of said first conductivity type adjacent said first surface of said first conductivity type separating said planar regions; a first continuous conductor deposited on a substantial portion of said isolation barriers and connected directly to a source of common potential; a first homogenous insulation layer of a first material covering said first planar surface and the lateral edges of said first conductor and having a thickness greater than the thickness of said first conductor so as to define a second planar surface with a channel therein above said first conductor; a second insulation layer of a second material in said channel covering said first conductor and having a thickness substantially equal to the thickness of said first insulation layer minus the thickness of said first conductor so as to complete said second planar surface; and second conductors overlying said second planar surface and interconnecting said first conductor and selected planar areas of said semiconductor components through apertures in said first and second insulation layers.
2. A circuit of claim 1 wherein the width of said first conductor and the width of said second insulation layer are each substantially coexistent with the planar width of said isolation barriers.
3. A circuit of claim 2 wherein said first conductor is metallic and said second insulation layer is an oxide of said first conductor.
4. A circuit of claim 3 wherein said first conductor is aluminum, said first insulation layer is a silicon oxide, and said second insulation layer is an aluminum oxide.
Patent Citations (7)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3423650 | 1969-01-01 | Cohen | |
| US3581165 | 1971-05-01 | Seelbach et al. | |
| US3634203 | 1972-01-01 | McMahon et al. | |
| US3754170 | 1973-08-01 | Tsuda et al. | |
| US3766445 | 1973-10-01 | Reuter et al. | |
| US3774079 | 1973-11-01 | Zechman | |
| US3862017 | 1975-01-01 | Tsunemitsu et al. |