Circuit Arrangement for an Electric Melting Furnace

The invention concerns a circuit arrangement for an electric melting furnace which is supplied via a controlled converter, the latter converter being equipped with thyristors and being controlled by a control unit and a series-connected regulator. More particularly, the invention concerns a circuit arrangement comprising a monitoring circuit (supervisory circuit) which develops signals indicative of the operational states of the converter thyristors.

In a circuit arrangement of the above-described type, it would be advantageous for the circuit arrangement to ensure that emergency operation of the electric melting furnace be maintained, even if one or more thyristors of the converter fail. Such a result can be realized, with the still operable thyristors, if the nominal value of the load current is reduced accordingly.

It is an object of the present invention to provide a circuit arrangement of the above-mentioned kind which is designed to additionally permit emergency operation of the electric melting furnace, in the case of failure of one or more converter thyristors.

In accordance with the principles of the present invention, the above and other objectives are realized in a circuit arrangement of the above-described type by employing the signals indicative of the operational state of the thyristors to control switching devices for shorting the ohmic resistors included in the feedback path of the circuit current regulator. In this way, if one or more of the thyristors fail, the gain of the linear regulator is reduced, thereby reducing the current being fed by the remaining operable thyristors to the electric furnace.

The above and other features of the present invention will become more apparent upon reading the following detailed description which makes reference to the accompanying drawing, in which:

FIG. 1 shows a circuit arrangement in accordance with the principles of the present invention.

In FIG. 1, an electric melting furnace O is supplied current via a controlled converter SR which is fed from an a-c network N. This current being supplied by converter SR may lie, for instance, in the range between zero and 10 Hz. Associated with the converter SR is a control apparatus comprising a control unit St and a series-connected current regulator IR. The current regulator IR has a linear gain characteristic and includes an operational amplifier, one of whose inputs is fed an actual current value from a current transformer W arranged in the load circuit. The other input of the regulator IR is fed by a current reference value which is supplied by a reference-value transmitter SG, shown as a potentiometer. In the feedback path of the current regulator IR are disposed two ohmic resistors R6 and R7 which serve as feedback resistors. As can be appreciated, the current regulator IR ensures that during undisturbed, normal operation, the actual current value in the furnace is adjusted to the predetermined current reference value.

The converter SR comprises a number of thyristors, of which, for clarity purposes, only four thyristors, Th.sub.a1, Th.sub.a2, Th.sub.b1, Th.sub.b2 are shown in the drawing. These four thyristors belong to the same branch of the converter SR, and are divided into a thyristor group a and a thyristor group b.

To monitor the thyristor groups a and b, monitoring circuits comprising fuses and an alarm contact are provided. In particular, fuses Si.sub.a1 and Si.sub.a2 are connected in series with the thyristors Th.sub.a1 and Th.sub.a2, while fuses Si.sub.b1 and Si.sub.b2 are connected in series with the thyristors Th.sub.b1 and Th.sub.b2. The four fuses Si.sub.a1, Si.sub.a2, Si.sub.b1 and Si.sub.b2, in turn, control alarm contacts a1, a2, b1 and b2. If anyone of the fuses blows, the associated alarm contact opens.

As shown, the alarm contacts a1, a2 of the thyristor group a and the alarm contacts b1, b2 of the thyristor group b, respectively, are each connected in series. The two series circuits a1, a2 and b1, b2, respectively, are, in turn, together connected on one side to the negative pole K of a d-c voltage source. On the other side, both series circuits are connected, via respective inverter elements P1 and P2, with an evaluation circuit A. The evaluation circuit A comprises a NOR gate B and a NAND gate D, both of which are connected on the input side with the outputs of the inverters P1 and P2, respectively. As will be discussed more fully below, the evaluation circuit A delivers a first output signal z1 when one of the two signals x1, x2 from the inverters P1 and P2 is present, while it delivers a second output signal z2 when the signals x1, x2 are simultaneously present. The signals x1 and x2 represent signals which indicate the operational states of the thyristors Th.sub.a1, Th.sub.a2, Th.sub.b1 and Th.sub.b2.

The output of the NOR gate B is connected with the control input of a first switching element, which is depicted in the drawing as a field-effect transistor FET 5. The output of NAND gate D, in turn, is connected with the control input of a second switching element which, in the present case, is also shown as a field-effect transistor FET 6. The switching path of the first field-effect transistor FET 5 is connected across the resistor R6, while the switching path of the second field-effect transistor FET 6 is connected parallel to the series circuit comprising the resistor R6 and the resistor R7. As above-indicated the latter two resistors R6 and R7 are connected into the feedback path of the current regulator IR.

The resistance of the two resistors R6 and R7 is selected to be very high as compared to the resistance of the field-effect transistors FET 5 and FET 6 when the latter are in a conducting state. In particular, each of the two resistors R6, R7 may, for instance, have a resistance of 10 kohm. As a result, when the first switching element (FET 5) is conducting, the resistor R6 will be shorted, and when the second switching element (FET 6) is conducting the series circuit comprising the two resistors R6, R7 will be shorted.

If under normal operating conditions no disturbances are present in the thyristor group a, then the two alarm contacts a1, a2, of the thyristor group a are closed. In such case, the signal x1 indicating the operational state of the thyristors Th.sub.a1 and Th.sub.a2 is assumed to be in its low state, and is designated an L-signal. With x1 in its low state, the output y1 of the inverter P1 is in a high state and is designated an H-signal. The latter signal is passed on to the first input of the NOR gate B and to the first input of the NAND gate D. Similarly, if no disturbances are present in the thyristor group b, the two alarm contacts b1 and b2 of the thyristor group b are closed and the signal x2 indicating the operational state of the thyristors Th.sub.b1 and Th.sub.b2 is also in a low state, i.e., is an L-signal. As a result, the output y2 of the inverter P2 is a high state signal, i.e., an H-signal. The latter signal is passed on to the second input of the NOR gate B and the second input of the NAND gate D. With no disturbances at the thyristor groups a and b their thus appears two H-signals at the inputs of the NOR gate B. These signals result in an L-signal as the output signal z1. The field-effect transistor FET 5 controlled by the signal z1 is, therefore, held in a cut-off state. The two H-signals at the inputs of the NAND gate D also result in an L-signal as the second output signal z2. The field-effect transistor FET 6, is, therefore, likewise held by the signal z2 in a cut-off state. The two resistors R6, R7 are, thus, fully effective in the feedback path of the current regulator IR. The latter regulator, therefore, has a set gain.

If, however, one of the alarm contacts a1 or a2 opens, due to the associated fuse Si.sub.a1 or Si.sub.a2 blowing as a result of a defect in the thyristors Th.sub.a1 or Th.sub.a2 or due to an overloading of these thyristors, the signal x1 indicating the operational state of the thyristors Th.sub.a1 and Th.sub.a2 becomes an H-signal. At the output of the inverter P1 there, thus, now appears an L-signal which is passed on to the second input of the NOR gate B and the second input of the NAND gate D. The H-signal at the first, and the L-signal at the second input of the NOR gate B result in an H-signal as the output signal z1. The field-effect transistor FET 5 is, thereby, made to conduct, and the first resistor R6 shorted. On the other hand, the H-signal at the first, and the L-signal at the second input of the NAND gate D still cause an L-signal to appear as the NAND gate output signal z2. The field-effect transistor FET 6, therefore, remains in the cut-off state. Only the second resistor R7 is now effective in the feedback path of the current regulator IR. As a result, the gain of the current regulator IR is reduced, thereby causing a corresponding reduction of the load current in the electric melting furnace O. This reduction in load current permits the load current to still be supplied by the remaining operational thyristors Th.sub.b1 and Th.sub.b2 without these thyristors becoming overloaded.

If there are no disturbances in the thyristor group a, but there are disturbances present in the thyristor group b, a similar operation as discussed above occurs, thereby resulting in a reduced load current which permits the thyristors Th.sub.a1 and Th.sub.a2 to continue to operate.

The evaluation circuit A is, thus, designed so that, when either the signal x1 or x2 indicates a fault (i.e., is an H-signal), the circuit provides a control signal to the control electrode of the field-effect transistor FET 5 which puts the former in a current-conducting state. The circuit is further designed, moreover, so that the field effect transistor FET 6 remains in the cut-off state, as long as either only the signal x1 or the signal x2 is indicating a defect in its respective thyristor group.

If, however, there are disturbances in the thyristor group a and at the same time in the thyristor group b, then both signals x1 and x2 become H-signals. There, thus, appear L-signals at both inputs of the NOR gate B and at both inputs of the NAND gate D. These signals, in turn, result in an H-signal for the signal z1, thereby placing the field effect transistor FET 5 into a conducting state. Likewise, the two L-signals cause the output signal z2 to be an H-signal which signal also places the field-effect transistor FET 6 in a current-conducting state. The series circuit comprising the resistors R6 and R7 in the feed-back path of the current regulator IR is thereby short-circuited. Short-circuiting both resistors results in a further reduction of the gain of the current regulator IR over the prior case, so that the load current in the electric melting furnace O is further reduced. This further reduction in load current permits the remaining nondisturbed thyristors in the converter SR to continue to operate without being overloaded or destroyed.

The evaluation circuit A is, thus, additionally designed so that, when the signals x1 and x2 simultaneously indicate a fault (i.e., are both H-signals), it delivers an output signal z2 which places the field-effect transistor FET 6 into the current-conducting state. Both resistors R6 and R7 are thereby short-circuited, which results in a further reduction of the gain of the current regulator IR. Emergency operation of the electric melting furnace O can thereby be maintained, while the disturbances are being corrected.