Voltage and Temperature Compensation Circuitry for Current Mode Logic

This invention relates to compensated CML logic circuits and more specifically to an improved integratable CML logic circuit which includes voltage and temperature compensation means.

A typical CML logic circuit arrangement may employ two transistors having their emitters connected to each other. The coupled emitters are then coupled through a constant current source transistor and an emitter resistor to a source of potential. The base of one of the two first-mentioned transistors and the base of the constant current source transistor and an emitter resistor to a source of potential. The base of one of the two first-mentioned transistors and the base of the constant current source transistor are normally coupled to one or more sources of reference potential, the base of the other of said two first-mentioned transistors serving as an input to the CML logic circuit.

The sources of reference potential may be derived from a voltage divider or taken directly from one or more voltage sources. The function of the constant current source transistor is to keep the overall emitter current of the two emitter-coupled transistors at a predetermined constant value. The value of the current is determined by the value of the emitter-resistor of the constant current source transistor, by the reference voltage applied to the base of the constant current source transistor, and by the emitter-base junction voltage of the constant current source transistor. Any variation in supply voltage or in the junction temperature will result in a variation of the voltage across the emitter-base junction of the constant current source transistor, since this voltage is strongly temperature dependent. If the voltage at the base of the constant current source transistor should be kept at a truly constant value with respect to ground by the reference potential, then variations in the voltage at the emitter of the constant current source transistor, as from fluctuations in junction temperature or from variations in power supply, would result in a varying current through the two commonly coupled transistors.

If the reference potential at the base of one of the two first-mentioned transistors is taken from the collector of a fourth transistor whose emitter is coupled through a resistor to a source of potential, and if the reference voltage at the base of the fourth transistor should be kept absolutely constant with respect to ground, the circuit will similarly fail to compensate for variations in supply voltage and junction temperature. Thus, variations in the input threshold levels and in variations in the levels of the output signals would result. Attempts have been made in the prior art to solve these temperature-related problems, as illustrated by U.S. Pat. Nos. 3,560,770 to J. Giles; 3,590,274 to R. Marley; and 3,622,799 to R. Marley et al.; but these prior attempts have not been totally successful. None of these attempts achieve the degree of total compensation possible with applicants' circuit. Only applicants' unique compensation compensates for fluctuations in junction temperature and for variations in power supply so as to insure that the output levels and input thresholds remain truly invarient.

It is an object of this invention to provide a compensated CML logic circuit whose input thresholds and output levels are invariant with changes in supply voltage and junction temperature.

It is a further object of this invention to provide a voltage and temperature compensated integratable CML logic circuit.

It is yet a further object of this invention to provide a compensation circuit which tracks variations in power supply voltage on a one-to-one basis, measured with respect to ground, except that the compensation circuit output is allowed to vary by one V.sub.be with variations in junction temperature.

It is still a further object of this invention to provide a fully-compensated constant current source whose output is invariant with variations in supply voltage or junction temperature.

These and other objects of this invention are herein illustrated in a CML logic circuit which includes the voltage and temperature compensating circuit of the present invention. The output of the compensating circuit is coupled to the base of the constant current source transistor which feeds the differential amplifier stage of the CML logic gate and to the base of a second constant current source transistor whose collector voltage is used to bias the non-input transistor of the differential amplifier stage of the current switch. The output of the compensation circuit, which is applied to the bases of these constant current source transistors, will track variations in power supply voltage on a one-to-one basis, measured with respect to ground, except that the voltage is allowed to vary by one V.sub.be with variations in junction temperature. The compensation circuitry includes a temperature compensating network having a temperature compensation factor of zero and a resistive means; both the temperature compensation network and the resistive means are coupled with the base of a compensation circuit output transistor. The resistive means provides for a one-to-one tracking of fluctuations in supply voltage, and the voltage drop across the base-to-emitter junction of the output transistor provides a temperature compensation factor for the overall compensation circuit of minus one. The temperature compensation network itself provides an overall compensation factor of zero by combining a temperature compensating subcircuit having a compensation factor of minus one with a temperature compensating subcircuit having a temperature compensation factor of plus one via a unique voltage divider arrangement whereby the tapped output of the voltage divider couples an overall compensation factor of zero to the base of the compensation circuit's output transistor; the base-to-emitter junction of the output transistor itself contributing the overall temperature compensation factor of minus one.

The above-cited objects of the invention together with other objects and advantages which may be obtained by its use, will be apparent from the following detailed description of the invention taken in conjunction with the drawing:

FIG. 1 is a schematic diagram of the overall compensation network of the present invention;

FIG. 2 is a schematic diagram of a temperature compensating subcircuit which has a temperature compensation factor of minus one and an overall temperature compensation factor of minus two;

FIG. 3 is a schematic diagram of a temperature compensation subcircuit having a temperature compensation factor of plus one and an overall compensation factor of zero;

FIG. 4 is a schematic diagram of the entire voltage and temperature compensation circuit of the present invention; and

FIG. 5 is a schematic diagram of an improved CML logic circuit which includes the overall voltage and temperature compensating circuit of FIG. 4.

Referring first to FIG. 1, the broad concept of the overall compensation network of the present invention will be described. A compensation network output transistor 11, also referred to as compensation network output transistor Q1, has its emitter coupled to a source of potential V.sub.EE and its collector coupled to ground through resistor 13. The output 15 of the compensation network is taken from the junction 17 of the collector of transistor 11 and the non-grounded end of resistor 13. A temperature compensating network is illustrated by block 19, one terminal of which is connected to junction 17 and the other terminal of which is connected to the base of transistor 11. The voltage V.sub.x which appears across the temperature compensating circuit 19 involves a temperature compensating factor of its own which is applied between the base of transistor 11 and output 15 via junction 17 so as to contribute to the overall compensation factor inherent in the compensated voltage V.sub.R which is measured with respect to the power supply voltage V.sub.EE and which is defined as the voltage measured between the source of potential V.sub.EE and junction 17 or the compensation network output 15.

The base of output transistor 11 is also connected to ground through a resistor 21 so as to enable the output transistor 11 to conduct so as to have the voltage at the junction 17, measured with respect to ground, track fluctuations in supply voltage on a one-to-one basis. Hence, the voltage V.sub.R, which is measured with respect to the supply voltage V.sub.EE, will remain absolutely invariant with variations in supply voltage but will be allowed to vary by one V.sub.be with variations in junction temperature.

The overall compensated voltage V.sub.R is determined by the temperature compensating voltage V.sub.x of the circuit of block 19 and by the base-to-emitter drop across the compensation output transistor 11 and is given by the formula V.sub.R = V.sub.x + V.sub.be. V.sub.R is, by definition, invariant with respect to supply voltage since resistor 21 provides for a one-to-one tracking of variations in supply voltage with respect to ground. The total regulated voltage is therefore given by V.sub.R = V.sub.x + V.sub.be which is invariant with respect to variations in supply voltage but which allows for voltage compensation for temperature-induced voltage variations of V.sub.x .+-. variations in the base-to-emitter junction voltage of transistor 11.

Since this voltage is to be used to control the voltage at the base of a constant current source transistor, which in itself will have a base-to-emitter junction voltage variation with temperature, it is desired that the overall temperature compensation factor present in the V.sub.R equation has an overall value of minus one. Since there is effectively a minus one compensation factor attributable to the base-to-emitter junction of transistor 11, it is necessary to construct the temperature compensation circuit 19 such that its overall contribution to the temperature compensation factor is zero, i.e. ##EQU1## if T is temperature.

Referring now to FIG. 2, a temperature compensation network having an overall temperature compensation factor of minus two will be described. The temperature compensation output 23 is taken from the collector of an output transistor 25 whose emitter is coupled to a source of potential V.sub.EE. A resistor 27 is connected between ground and the junction 29 of the collector of transistor 25 and the temperature compensation output 23. Junction 29 is coupled to the base of a second compensating transistor 31 whose collector is connected to ground and whose emitter is coupled through resistor 33 to a source of potential V.sub.EE. The junction 35 between the emitter of transistor 31 and resistor 33 is coupled to the base of output transistor 25. The voltage V.sub.TC which appears between the terminal 23 and the source of potential V.sub.EE has an overall temperature compensation factor of minus two, as readily seen from the circuit. One V.sub.be is derived from subcircuit 37, as represented by V.sub.x which is measured between the base of transistor 31 and junction 35, and the second portion of the overall factor of V.sub.TC is accounted for by the V.sub.be drop of output transistor 25.

Referring now to FIG. 3, a temperature compensation network having an overall temperature compensation factor of zero and a subcircuit temperature compensation factor of plus one for V.sub.x will be described. A temperature compensation network output 39 is taken from the collector of an output compensation transistor 41 via junction 43. The emitter of transistor 41 is connected to a source of potential V.sub.EE and junction 43 is connected to ground through a resistor 45. A temperature compensating subcircuit 47 includes a transistor 49 whose emitter is coupled to a source of potential V.sub.EE through resistor 51 and whose collector is coupled to the base of output transistor 41. The base of transistor 49 is coupled to the source of potential V.sub.EE via diode 53 whose anode is connected to the base of transistor 49 and whose cathode is connected to the source of potential V.sub.EE. As known in the art, this diode may be an integrated circuit transistor which has its collector connected directly to its base or the like. The junction of the anode of diode 53 with the base of transistor 49 is connected to junction 43 via resistor 55. A resistor 57 is then coupled between junction 43 and the base of transistor 41. The voltage V.sub.x which appears across resistor 57 exhibits a temperature compensation factor of plus one for the subcircuit 47. Since this plus one factor exists between the junction 43 and the base of transistor 41, the V.sub.be voltage drop of transistor 41 supplies a factor of minus one giving an overall temperature compensation factor of zero for the voltage V.sub.TC appearing between the terminal 39 and the source of potential V.sub.EE.

FIG. 4 shows the voltage and temperature compensation network of the present invention which exhibits an overall temperature compensation factor of minus one at the output and is comprised of the combination of the subcircuits of FIGS. 2 and 3 via a unique voltage divider configuration. An output 59 of the voltage and temperature compensation network is taken from the collector of an output transistor 61 whose emitter is coupled to a source of potential V.sub.EE. The junction 63 of output terminal 59 and the collector of transistor 61 is coupled to ground node 64 through resistor 65. A voltage compensation resistor 67 is coupled between ground and the base of output transistor 61 so as to allow for a one-to-one tracking (with respect to ground) of variations in power supply voltage, thereby insuring that the regulated voltage V.sub.R, which is measured with respect to the power supply voltage, remains invariant with fluctuations in supply voltage V.sub.EE.

A temperature compensating subcircuit 69 will now be described. A first temperature compensation transistor 71 has its base coupled to node 63 via resistor 73, its emitter coupled to a source of potential V.sub.EE through a resistor 75, and its collector coupled to the base of transistor 61 via node 77. The junction of resistor 73 and the base of transistor 71 is coupled to the source of potential V.sub.EE through a diode 79 whose anode is poled toward the base of transistor 71 and whose cathode is poled toward the source of potential V.sub.EE. A voltage divider comprising three resistors 81, 83 and 85 is coupled between junction 63 and the source of potential V.sub.EE. The first voltage divider resistor 81 has one end coupled to junction 63 and the opposite end connected to node 77. Node 77 is connected via resistor 83 to the emitter of a second compensating transistor 87 and the junction of the emitter of transistor 87 with resistor 83 is coupled to a source of potential V.sub.EE via resistor 85. Temperature compensation transistor 87 has its base coupled to junction 63 and its collector is coupled through a resistor 89 to ground. The junction 77 is also coupled to the base of output transistor 61 so as to control the compensated output voltage as seen at terminal 59 and provide an overall compensated voltage V.sub.R which will remain invariant with fluctuations in the power supply V.sub.EE and provide an overall temperature compensation factor of minus one.

Briefly, the operation of the circuit of FIG. 4 with respect to compensation for fluctuations in supply voltage will be described. Recall that the output voltage V.sub.R must remain invariant with fluctuations in supply voltage V.sub.EE. Since V.sub.R is measured with respect to V.sub.EE, the voltage at junction 63, when measured with respect to ground, must track the variations in V.sub.EE on a one-to-one basis so as to maintain the voltage V.sub.R invariant. If the supply voltage V.sub.EE were to become more negative or, what amounts to the same thing, if the ground node 64 were to become more positive, the potential V.sub.R would tend to vary. As V.sub.EE becomes more negative, the magnitude of V.sub.R would tend to become greater since the node 63 is tied to ground through resistor 65 and would remain relatively constant while V.sub.EE increased thereby necessitating an increase in V.sub.R. Similarly, as node 64 goes more positive, junction 63 would tend to follow node 64 since it is tied to node 64 through resistor 65, and since node 63 tends to go positive with respect to the supply voltage V.sub.EE, the voltage V.sub.R increases in magnitude just as in the case wherein V.sub.EE increased and the node voltage 63 remained constant.

But the circuit of the present invention is designed such that V.sub.R remains invariant with fluctuations in supply voltage or ground level. An attempted increase of V.sub.R is feed back through box 69 to the base of transistor 61, thereby increasing the collector current of transistor 61 and, subsequently, keeping V.sub.R relatively constant. This feed-back control, however, is not perfect, because an enlarged collector current requires a slightly increased V.sub.be and, hence, a slightly increased V.sub.R which is equal to the sum of V.sub.x and V.sub.be. This remaining error is compensated for by a supplementary base current I.sub.b which is provided through resistor 67 which connects the base of transistor 61 to ground. As V.sub.EE goes more negative, the relatively constant base-to-emitter voltage of transistor 61 requires that the voltage at the base of the transistor 61 goes more negative as well. Since the voltage at the base of transistor 61 goes more negative and since the other end of resistor 67 is tied to ground, the supplementary base current I.sub.b must increase to account for the drop in voltage across the resistor 67. The increase in the base circuit is amplified by the current gain .beta. (beta) such that the collector current through resistor 65 increases by a factor of .beta. times the increase in base current. The increase in collector current through the transistor 61 and hence through resistor 65 insures that a greater voltage drop occurs across the resistor 65 with the result that junction 63 goes more negative. The values of the resistor 65 and 67 when taken in conjunction with the current gain factor of transistor 61 allow a selection of parameters such that variation in supply voltage with respect to ground are compensated for by induced variations in the voltage level of junction 63 which track variations in supply voltage V.sub.EE on a one-to-one basis so as to maintain the voltage difference V.sub.R between the junction 63 and the supply voltage V.sub.EE absolutely invariant.

To avoid confusion, the same operation will be briefly described for values referenced to the supply voltage V.sub.EE instead of ground. As indicated above, V.sub.EE going more negative with respect to ground is the equivalent of node 64 going more positive with respect to the supply voltage. If node 64 goes more positive, it will tend to pull the junction 63 along with it, hence, tending to increase the value of V.sub.R. Since it is an object of the present invention to maintain V.sub.R invariant with fluctuations in supply voltage or ground level, junction 63 must be driven more negative by dropping a greater voltage across resistor 65. Again, the presence of resistor 67 between the node 64 and the base of transistor 61 provides the necessary compensation for the imperfection of the basic feed-back control loop constituted by transistor 61 and box 69. As the voltage at node 64 increases and the voltage at the base of transistor 61 remains relatively constant since it is tied through the base emitter junction to the supply or reference potential V.sub.EE, a greater voltage is dropped across resistor 67. This greater voltage drop across resistor 67 results in an increase in base current I.sub.b. An increased base current drives the transistor harder and results in an increased collector current which is related to the increase in base current by the current gain factor of transistor 61. The increased collector current causes a greater voltage drop across resistor 65 thereby forcing the potential of junction 63, lower as desired. Values of current gain and resistors can be chosen such that junction 63 would tend to be driven lower such that the voltage V.sub.R remains invariant. In either description, it is evident that the use of resistor 67 insures that V.sub.R remains invariant with fluctuations in supply voltage or ground plane level while the variations appear across the resistor 65 instead.

A similar operation would result should the supply voltage V.sub.EE go more positive with respect to ground or the node 64 tend to go more negative with respect to V.sub.EE. In either event, the operation of the circuit is substantially as described above but with decreased collector current and less voltage dropped across resistor 65.

Referring now to FIG. 5, a fully-compensated CML logic gate which includes the voltage and temperature compensated constant current source subcombination of the present invention which in turn utilizes the preferred embodiment of the voltage and temperature compensation circuit of FIG. 4, will be described.

A differential amplifier stage of the CML gate includes an input transistor 91 and a non-input transistor 93. The input to the logic gate would be fed via terminal 95 to the base of the input transistor 91. The outputs of the logic gate are taken from the collectors of transistors 91 and 93 respectively. The collector of transistor 91 is also connected to ground through a resistor 97 and the collector of transistor 93 is connected to ground through resistor 99. The emitters of transistors 91 and 93 are coupled together at junction 100 and connected to the collector of a constant current source transistor 101 whose emitter is connected via emitter resistor 103 to a source of potential V.sub.EE. The base of non-inverting transistor 93 is coupled to ground through resistor 105 and to the collector of a second constant current source transistor 107 whose emitter is coupled to the source of potential V.sub.EE via emitter resistor 109. The bases of the constant current transistors 101 and 107 are coupled together at node 111 which corresponds to the output 59 and correspondingly junction 63 of the temperature and voltage compensating network of the circuit of FIG. 4 which is indicated by the dotted block 112 in the circuit of FIG. 5. Junction 111 is coupled to ground through resistor 113 and to the collector of a temperature compensation output transistor 115 whose emitter is coupled to the source of potential V.sub.EE. The three-resistor voltage divider is coupled between junction 111 and the source of potential V.sub.EE such that one end of resistor 117 is coupled to the junction 111 and the other end of resistor 117 is coupled to node 119 and then through resistor 121 to the emitter of a temperature compensation transistor 123 and thence to the source of potential V.sub.EE via resistor 125. Node 111 is also connected to the base of the second temperature compensating transistor 127 through a resistor 129. The base of transistor 127 is further coupled through a diode 131 to the source of potential V.sub.EE such that the diode is poled with its anode toward the base of transistor 127 and its cathode is poled toward the source of potential V.sub.EE. Transistor 127 has its emitter coupled through resistor 133 to the source of potential V.sub.EE and its collector coupled to node 119. Transistor 123 has its base connected to the node 111 and its collector coupled to ground either directly or through resistor 135. The base of transistor 115 is coupled to ground via a voltage compensation resistor 137 in order that the output of transistor 115 can track fluctuations in supply voltage on a one-to-one basis with respect to ground thereby holding V.sub.R invariant. The collector of transistor 115 is then connected to node 111 for temperature compensation purposes such that the output voltage V.sub.R, as measured between junction 111 and the source of potential V.sub.EE, is fully compensated for fluctuations in the voltage supply and for variations in junction temperature.

This compensated control voltage V.sub.R is supplied to the base of constant current source transistors 101 and 107 respectively and since this voltage remains invariant with fluctuations in the power supply voltage and compensates for voltage variations of up to that of one V.sub.be which might result from junction temperature variations, the output of these constant current source transistors remains truly constant. A fully compensated truly constant current source is shown as the combination within the dotted lines defining block 140 of the circuit of FIG. 5. The constant current which is supplied to the coupled emitters of transistors 91 and 93 via the combination of constant current source transistor 101 and its emitter resistor 103 and the constant current which flows from the constant current source comprising transistor 107 and its emitter resistor 109 which is fed to the base of the non-input transistor 93 and through resistor 105 to ground insures that the input thresholds and the output voltage levels are truly constant and will not vary with fluctuations in power supply voltage nor with variations in junction temperature. The improved regulated CML logic gate and its compensation network for providing a regulated voltage compensated for fluctuations in power supply and for variations in junction temperature insures that the constant current source stages of the CML logic gate supply truly constant currents hence insuring input thresholds and output voltage levels which are invariant with changes in supply voltage or variations in junction temperatures.

The following list of resistor values for the circuit of FIG. 4 is provided with the understanding that the values given are considered to denote a specific preferred embodiment already built and tested, it being understood that those skilled in the art could certainly practice the present invention with other component values and still achieve the objects of this invention.

All values refer to the resistors of FIG. 4 and are given in ohms but the values apply to corresponding resistors in the other circuits as well.

R65 = 51

r67 = 3000

r73 = 307

r75 = 78

r81 = 330

r83 = 594

r85 = 179

r89 = very small or zero

With this detailed description of the structure and operation of the present invention it will be obvious to those skilled in the art that various modifications can be made without departing from the spirit and scope of the invention which is limited only by the appended claims.