Phase Comparator

This invention pertains generally to phase comparator circuitry and more particularly to phase comparator circuitry suitable for monolithic integrated circuit fabrication.

It is an object of this invention to provide an improved phase comparator circuit adapted for integrated circuit fabrication.

This and other objects of the invention are attained generally by providing, in combination: A first differential amplifier having a first input terminal adapted for coupling to an input signal source through a first input impedance, a second input terminal coupled to a predetermined voltage source, and a first output terminal; a second differential amplifier having first and second input terminals adapted for coupling to the input signal source through second and third input impedances, respectively, and a second output terminal coupled to the first output terminal; a high gain amplifier having an input coupled to the first and second output terminals and an output coupled in degenerative feedback to the first input terminal of the first differential amplifier through a first feedback impedance and also coupled in degenerative feedback to the first input terminal of the second differential amplifier through a second feedback impedance; and means responsive to a reference signal selectively to actuate the first differential amplifier to couple the input signal to the high gain amplifier through such first differential amplifier exclusively or to actuate the second differential amplifier to couple the input signal to the high gain amplifier through such second differential amplifier exclusively.

For a more complete understanding of the invention, reference is now made to the following description of the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a phase comparator according to the invention;

FIG. 2 is a schematic diagram of a switch used in the phase comparator network shown in FIG. 1;

FIG. 3 is a diagram of a circuit useful in understanding the operation of the phase comparator shown in FIG. 1;

FIG. 4 is also a diagram of a circuit useful in understanding the operation of the phase comparator circuit shown in FIG. 1;

FIG. 5 is a curve showing the waveform of a reference voltage signal applied to the phase comparator shown in FIG. 1;

FIGS. 6A, 7A, 8A, 9A show different exemplary input voltage waveforms applied to the phase comparator circuit shown in FIG. 1, such waveforms having 0.degree., +90.degree., +180.degree. and +270.degree. phase relationships, respectively, with the reference voltage signal waveform shown in FIG. 5;

FIGS. 6B, 7B, 8B and 9B show the voltage waveforms produced at the output of the phase comparator when such phase comparator has the voltage waveforms shown in FIGS. 6A, 7A, 8A and 9A applied thereto, respectively; and

FIG. 10 is a schematic diagram of a high gain amplifier used in the phase comparator circuit shown in FIG. 1.

Referring now to FIG. 1, a phase comparator 10 incorporating our concepts is shown to include a pair of "matched" differential amplifiers 12, 14. Each one of such amplifiers has, respectively, a pair of input terminals 16, 18 and 20, 22 and a common output (i.e. line 23) as shown. Each one of such pair of differential amplifiers 12, 14 is connected (in a manner to be described) between a +V.sub.CC supply and a -V.sub.CC supply so that one of the differential amplifiers is selected for operation in accordance with the signals on lines 28, 30. The signals on lines 28, 30 are supplied by a switch 32, the details of which will be described in connection with the explanation of FIG. 2. Suffice it to say here that, when a reference voltage having a periodic waveform as shown in FIG. 5 is supplied to the switch 32 during alternate half periods of such waveform, a pair of transistors Q.sub.11, Q.sub.12 is alternately actuated (by signals on lines 28, 30) thereby to complete the connection (through resistors R.sub.8, R.sub.9 and transistors Q.sub.11 , Q.sub.12) of the differential amplifiers 12, 14 to the +V.sub.CC, -V.sub.CC supplies via resistors R.sub.12, R.sub.13 and transistors Q.sub.17, Q.sub.18. It is noted that preferably transistors Q.sub.11 and Q.sub.12 are matched to provide matched current sources for the differential amplifiers 12, 14. It follows then that during one-half of the period of the reference voltage applied to switch 32, a voltage is produced on line 23 which is proportional to the difference in potential between the voltages applied to terminals 16, 18 of differential amplifier 12 and, during the other half of such period, a voltage is produced on line 23 which is proportional to the difference in potential of the voltages applied to terminals 20, 22 of differential amplifier 14. An input voltage, e.sub.i, (the phase of which is to be compared with the phase of the reference voltage) is applied as shown: To terminal 18 of differential amplifier 12 (via an input resistor R.sub.10); to terminal 20 of differential amplifier 14 (via an input resistor R.sub.11); and to terminal 22 of differential amplifier 14 (via an input resistor R.sub.14). The output of the actuated one of the pair of differential amplifiers 12, 14 is coupled, via line 23, to a high gain amplifier 34, the details of which will be described in connection with FIG. 10. The output of such high gain amplifier 34 provides the output voltage, e.sub.o, of the phase comparator 10 on line 36. The signal on line 36 is coupled to resistor R.sub.10 at terminal 38 via feedback resistor R.sub.15 and also to terminal 39 via feedback resistor R.sub.16. Terminal 38 is connected to terminal 18 of differential amplifier 12 and terminal 39 is connected to terminal 20 of differential amplifier 14, as shown. It is here noted that when differential amplifier 12 is actuated, the input voltage, e.sub.i, may be considered as being applied to an operational amplifier having a feedback resistor R.sub.15 and input resistor R.sub.10 as shown in FIG. 3. Further, the "feedback loop" (i.e. the path from terminal 38 (FIG. 1) to terminal 18, transistor Q.sub.14, transistor Q.sub.13, high gain amplifier 34, feedback resistor R.sub.15 back to terminal 38) has a 180.degree. phase shift associated therewith and hence such "feedback loop" is a "negative" or degenerative loop. Further, because input terminal 16 of differential amplifier 12 is coupled to ground via resistor R.sub.7, the ratio of the output voltage on line 36, e.sub.o, to the input voltage e.sub.i, may be represented as:

with, as here,

the half periods of the reference voltage when differential amplifier 12 is actuated.

During the alternate half periods of the reference voltage, that is when the differential amplifier 14 is actuated, the input voltage, e.sub.i, may be considered as being applied to one terminal of an operational amplifier via input resistor R.sub.11 and to another terminal of such operational amplifier via input resistor R.sub.14, such operational amplifier having degenerative feedback via feedback resistor R.sub.16 as represented by the diagram shown in FIG. 4. (Here the feedback path is from terminal 39 to transistors Q.sub.16, Q.sub.15, high gain amplifier 34, feedback resistor R.sub.16, back to terminal 39 (FIG. 1)). It follows then that the ratio of e.sub.o to e.sub.i may be represented as:

with, as here,

during the periods of the reference voltage when differential amplifier 14 is actuated.

In summary, then, during successive half periods of the reference voltage the voltage, e.sub.o, produced on line 36 (i.e. the output of the phase comparator 10) is substantially the input voltage, e.sub.i, and during the second half period such output, e.sub.o, is the negative of the input voltage, e.sub.i. Common mode rejection of the reference voltage is accomplished by matching transistors Q.sub.11 and Q.sub.12 and differential amplifiers 12, 14 as described above. Such transistors and differential amplifiers are matched because such are here formed on a common monocrystalline semiconductor body (not shown). The signal at the output of comparator 36 varies in accordance with the phase angle between the input voltage, e.sub.i, and the reference voltage when the periods of such voltages are substantially the same. This may be better understood by referring now to FIGS. 5, 6A - 6B, 7A - 7B, 8A - 8B and 9A - 9B. FIG. 5 shows a waveform of the reference voltage applied to switch 32 (FIG. 1), such waveform having a period, T. Let us here assume that durng the first half of such period the ratio of e.sub.o /e.sub.i is substantially +1 and during the second half of such period the ratio e.sub.o /e.sub.i is substantially -1. It follows then that with the input voltages, e.sub.i, such as those shown in FIGS. 6A, 7A, 8A and 9A, corresponding output voltages, e.sub.i, appear as shown in FIGS. 6B, 7B, 8B and 9B. That is, when the input voltage and the reference voltage are "in phase" the output voltage of the phase comparator 10, under such assumption, appears as that shown in FIG. 6B and may be considered as having an average value of +A volts. When the voltages are "180.degree. out-of-phase" the output of the phase comparator 10 appears as shown in FIG. 8B and may be considered as having an average value of -A volts. When the voltages are .+-. 90.degree. out-of-phase the output voltages of phase comparator 10 appears as shown in FIGS. 7B and 9B and may be considered as having an average value of 0 volts. A little thought will make it apparent that the average voltage produced at the output of the phase comparator 10 under such assumption is proportional to the cosine of the phase angle difference between the input voltage, e.sub.i, and the reference voltage where such input voltage has a sinusoidal waveform.

Referring now to FIG. 2, switch 32 is shown to include a resistor R.sub.1 adapted for coupling to the reference voltage source (not shown). Transistors Q.sub.1, Q.sub.2 are connected as diodes to limit the reference voltage (which may here be either a 9VRMS sinusoidal signal or a TTL periodic voltage signal) to .+-. 0.7 volts. When, during one-half of the period of the reference voltage, the voltage at the base electrode of transistor Q.sub.6 is +0.7 volts, transistor Q.sub.6 conducts, whereas transistor Q.sub.7 is nonconductivve during this half period (because the base electrode of transistor Q.sub.7 is at 0 volts), and current passes through line 30, diode connected transistor Q.sub.8 (such transistor serving as a current source driver for transistor Q.sub.12 (FIG. 1)), transistor Q.sub.4 and resistor R.sub.3, thereby to actuate differential amplifier 14 (FIG. 1) as described above. Conversely, when the voltage on the base electrode of transistor Q.sub.6 is - 0.7 volts, that is during the other half period of the reference voltage, the base electrode of transistor Q.sub.7 is more positive than the base electrode of transistor Q.sub.6 and hence current flows through transistor Q.sub.7 (whereas transistor Q.sub.6 is nonconductive during this half period) and current passes through line 28, diode connected transistor Q.sub.9 (such transistor serving as a current source driver for transistor Q.sub.11 (FIG. 1)), resistor R.sub.3 and transistor Q.sub.4, thereby to actuate differential amplifier 12 (FIG. 1) as described above. Field effect transistor (FET) 50, zener diode 52, transistor Q.sub.10 and resistor R.sub.6 provide here 0.75 mA of current, through the current source drivers Q.sub.5 and Q.sub.19. It is here noted that FET 50 is here acting as a high voltage, so-called, "pinchoff" resistor. Transistor Q.sub.3 and resistor R.sub.2 enables the switch 32 to accommodate conventional TTL input signals by providing a current sink to the source of such TTL input signal source. In summary, then, during one-half of the period of the reference voltage current passes through line 28 and during the other half-period current passes through line 30.

Referring now to FIG. 10, high gain amplifier 34 is shown. The output of the actuated one of the pair of differential amplifiers 12, 14 (FIG. 1) is coupled via line 23 to, inter alia, the base electrode of transistor Q.sub.23. Such transistor Q.sub.23 is connected as an emitter follower having a load resistor R.sub.17 to drive transistor Q.sub.24. The load for transistor Q.sub.24 includes transistor Q.sub.22 and a current source formed by transistor Q.sub.20. It is here noted that the base electrode of transistor Q.sub.20 is connected to the base electrode of transistor Q.sub.19 (FIG. 2)). This arrangement provides a relatively large single stage gain. Transistor Q.sub.24 drives transistor Q.sub.29 directly and drives transistor Q.sub.26 indirectly via level shift provided by Q.sub.20, Q.sub.21 and Q.sub.22. It is noted that if the output, line 36, of the comparator 10 (FIG. 1) is shorted to ground there will be a large voltage drop across the resistor R.sub.20 which thereby will forward bias transistor Q.sub.27 and tend to cut off output transistor Q.sub.26. Also, if there is a large negative current through transistor R.sub.21, transistor Q.sub.28 will become forward biased and current will start to flow through transistor Q.sub.30. This forward biases transistor Q.sub.25 which in turn pull the base electrode of transistor Q.sub.23 towards -V.sub.CC to thereby tend to turn transistor Q.sub.24 off. Thus, the output of high gain amplifier 34 rises, reducing the negative current, and the high gain amplifier 34 is short circuit protected. Frequency compensation is provided by capacitor C.sub.2. In a preferred embodiment, and referring to FIG. 1:

Having described a preferred embodiment of the invention, it will now be apparent to one of skill in the art that various changes may be made without departing from our inventive concepts. For example, while the circuitry described above has been shown to provide a phase comparator circuit, such circuitry may provide synchronous rectification by using as both the reference voltage input and the input voltage signal a common sinusoidal signal. Further, such circuitry may be used for various "steering" functions as when it is desired to pass the input voltage signal to the output line 36 with one polarity during one period of time and with an opposite polarity during a second period of time at the control of the signal applied to switch 32. Still further, because of the described characteristics of the disclosed circuitry such circuitry may be used as a mixer. It is felt, therefore, that this invention should not be restricted to its disclosed embodiment but rather should be limited only by the spirit and scope of the appended claims.