High Voltage System With Self-Test Circuitry

1. Field of the Invention

This invention relates to a high voltage sensing and control system, and more particularly to a high voltage system which provides a continuous self-test to detect errors in the communication of information within said system.

2. Description of the Prior Art

In the art, in high voltage systems it is often necessary to operate separate pieces of electronic equipment at both ground potential and the line potential. There exists a problem in communicating information between the different pieces of equipment across the high voltage gradient between them.

Self-test circuitry must also be provided in such a high voltage system, which takes into account that the data may change at a slow rate and may be subject to electromagnetic interference.

The high voltage and self-test system, in accordance with the invention, consists of current sensing means which detect the amount of current flowing through a high voltage line and transmit this information over a data link to control electronics which encodes the digital control commands from the control electronics and then transmits these commands via a plurality of communication links, then to be decoded and then delivered to actuator means which compensates for faults in the high voltage system or notifies the operator of such.

Also in this high voltage system is a continuous self-test which monitors the transmission of information over the various communication links and sends out a fault signal if there exists a malfunction. Such a self-test system consists of a clocked parity checking system in conjunction with the current sensing means described above.

Accordingly, it is an object of this invention to communicate the line current signal from line potential to a separate piece of electronic equipment at ground potential.

It is another object to communicate control commands from the ground potential control electronics to actuators at the line potential when the control electronics sends out a command signal to the actuators to activate the circuit breaker or to insert a current limiting resistor or to take whatever measure is necessary.

Another object is to provide a continuous automatic self-test of the communication equipments and paths and to detect any malfunction in said equipments and paths.

The features of the present invention which are believed to be novel are set forth with particularity in the appended claims. The present invention, both as to its organization and manner of operation, together with further objects and advantages thereof, may be understood best by reference to the following description, taken in connection with the accompanying drawings.

FIG. 1 is a high voltage system with two separate pieces of electronic equipment which transmit information optically.

FIG. 2 is a block diagram of the circuitry of the high voltage and continuous self-test system of the present invention.

FIG. 3 is a truth table for an exclusive OR gate.

Referring now to FIG. 1, the high voltage (HV) system has HV transmission line 10 and electronic circuitry 12 which senses the amount of current flowing through line 10 and transmits this information via communication link 16 to control circuitry 18. The electronic circuitry 12 being at the line potential and control circuitry 18 being at ground potential. One possible method of communicating this information is by means of fiber-optic bundles, which are excellent insulators, and free of electromagnetic and electrostatic interference. Control Commands and self-test information is then communicated from control electronics 18 over communication links 20, 80 and 82 to the electronic circuitry 12.

FIG. 2 shows the HV and continuous self-test system with its communication links of the present invention. Current sensor 14 senses the amount of current being transmitted on line 10 and sends a representative analog signal to analog input 40. Analog input 40 changes the amount of current sensed by 14 into a representative voltage signal which in turn is sent to voltage controlled oscillator (VCO) 42. VCO 42 has two outputs which are electrically the same; the first, which delivers a 1 megahertz carrier clock pulse to digital logic devices 98, 104, and 106 and the second output which is a frequency modulated (fm) carrier on which the modulation is the analog signal of the line current sensor 14. Transmitter 44 consists of an electro-optical converter which converts the electrical signal from VC0 42 to an optical signal, which is transmitted via communication line 16 to receiver 46 which converts the optical signal back to an electrical signal. The electrical signal from receiver 46 is then demodulated in demodulator 48; the carrier being transmitted as a clock pulse via line 50 to digital logic device, which in this case are exclusive OR gates 52, 54, and 56. And the analog signal of the line current sensor is sent via line 58 to control electronics 60. When there is a fault in the high voltage transmission line 10 or a surge of current in line 10, current sensor 14 senses this change and delivers a representative analog signal via line 58 to control electronics 60 which in turn delivers the appropriate control signal via lines 62, 64, 66, and 68, to read only memory (ROM) 70. Said control commands are encoded in electronics 12, transmitted to electronics 18, decoded and, if verified by self-test, tell actuator or fault correction means 100 to take the appropriate action; for example, to insert a current limiting resistor or to throw a circuit breaker or to take whatever measure is necessary. ROM 70 stores the digital control command from control electronics 60 and then reads out said information via lines 72, 74, 76, and 77.

Parity bit generator 78 is used in conjunction with parity check 102 to check to see if the digital information transmitted via lines 20, 80, and 82 is correctly received by receivers 84, 86, and 88, of electronic circuitry 12 and that communication link 16 is operating. That is, that there are no breaks or faults in the transmission of the information from control circuitry 18 to electronic circuitry 12 or from 12 to 18. This clocked parity check is based on the use of an additional bit, which is generated by parity bit generator 78, into each group of digital information delivered from ROM 70 via lines 76 and 77. The parity bit associated with each of these groups of digital information is in an "even parity-bit" checking system so that the total number of 1's in the digital information group plus the parity bit is always even. For example, if the information on lines 76 and 77 were 01, then the parity bit would be a 1, in order to make the total number of 1's even. Or if the digital information on lines 76 and 77 were 00, then the parity bit would be a 0 since there is already an even number of 1's.

The 1 megahertz carrier clock is transmitted to a first input of exclusive OR gates 52, 54, and 56 via line 50. Digital information is delivered from ROM 70 and parity bit generator 78 to said exclusive OR gates via a second input 72, 74, and 90.

FIG. 3 shows the truth table for an exclusive OR gate. CK represents the carrier clock and DB represents the data bit on lines 72, 74, and 90. Y represents the output from exclusive OR gates 52, 54, and 56. The information from these exclusive OR gates is transmitted by electro-optical transmitters 92, 94, and 96, via optical communication links 20, 80, and 82, respectively, to optical-to-electrical converters or receivers 84, 86, and 88. The digital data from said receivers is then inputed into a first input into exclusive OR gates 98, 104, and 106. The second input to said gates is a 1 megahertz carrier clock from VCO 42. Said gates output appropriate digital data corresponding to the outputs of the truth table of FIG. 3. Exclusive OR gates 98 and 104 transmit output data to R0M 108. And exclusive OR gate 106 delivers digital information to parity check 102 where it is compared with the digital data of lines 98 and 104 and if parity is verified, in turn delivers that information into R0M 108.

Finally, the information from R0M 108 is delivered via a plurality of output lines to actuator or fault correction means 100 which controls whatever function is needed, for example, if current sensor 14 senses an excess of current in the transmission line 10 then actuator 100 will insert a current limiting resistor or if the excessive current is too high, actuator 100 will throw a circuit breaker and shut down the line.

In normal operation, the control commands will input binary low information via lines 62 - 68 to R0M 70. The output of R0M 70 via lines 72 and 74 will be at a low binary level. With one input to the exclusive 0R gates low, the output from said gates will follow the carrier clock pulse which is on the other input to said gates. The output of exclusive 0R gates 54 and 54 will then be inputed into exclusive 0R gates 98 and 104, this high-low, high-low, etc. input will be in phase with the 1 megahertz carrier clock from V0C 42 which is being inputed into the other input to exclusive 0R gates 98 and 104. Therefore, the output from exclusive 0R gates 98 and 104 will be at a low level, thereby tracking the binary low information being inputed via lines 72 and 74 from R0M 70.

But if, for example, the current sensor 14 senses a surge in current which requires the actuator 100 to insert a current limiting resistor, the analog signal via line 58 would tell the control electronics 60 to output, for example, a 01 code via R0M 70 to exclusive OR gates 52 and 54. As discussed previously, the output from exclusive OR gaate 98 would track the binary low information inputed via line 72 from R0M 70. Whereas, the high level information via line 74 to exclusive 0R gate 54 in conjunction with the carrier clock on the other input to exclusive 0R gate 54 would output digital information which would be the inverse of the carrier clock from VC0 42. This information would be transmitted via optical communication link 80 through receiver 86 to one of the inputs to exclusive 0R gate 104. Since this information would be the inverse of the carrier clock from VC0 42 the output of exclusive 0R gate 104 would always be high, thereby tracking binary high information from R0M 70 via line 74. This 01 code would be sent through R0M 108 and if verified by parity check 102 is sent to actuator 100 which would have programmed the response that when it receives a 01 code to insert a current limiting resistor into the high voltage line 10, for example.

If one of the optical communication paths 16, 20 80, or 82 is broken or there is a malfunction in either electronic circuitry 12 or control circuitry 18, this fault will be detected by the clocked parity check apparatus. If for example the digital information is 110 on lines 20, 80, and 82, respectively, and link 20 was broken thereby delivering a 0 or low binary information to exclusive 0R gate 98, then the R0M 108 and parity check 102 would detect an error since even parity no longer existed, that is, the R0M would be receiving an alternating high-low-high-low binary level signal from exclusive 0R gate 98 and a high binary level from exclusive 0R 104 and a low data bit from parity check 102; R0M 108 would thereby be receiving an alternating data bit code 010-110-010, etc. since this is an even parity-bit checking system, the total number of 1's received by R0M 108 is alternating even-odd-even-odd, etc. and parity check 102 and R0M 108 would detect an error in the system. This error would be transmitted to actuator 100 which would alert the operator of the fault.

Although the device which has just been described appears to afford the greatest advantages for implementing the invention, it will be understood that various modifications may be made thereto without going beyond the scope of the invention, it being possible to replace certain elements by other elements capable of fulfilling the same technical functions therein.