Tracking Status Detector for a Digital Delay Lock Loop

The present invention relates generally to phase-locked loops and, more particularly, to detectors for monitoring the status of digital or analog phase-locked loops so as to provide an indication of their locked and unlocked conditions.

When a phase-locked loop is utilized in a satellite communication system for accomplishing precise time synchronism, for example, it is imperative to know whether or not the loop is properly tracking. Conventional detectors employed for this purpose usually rely on detecting the energy in the in-phase detector output after suitable filtering. Consequently, these detectors are not very reliable when the loop is operating near its threshold. Additionally, this type of detector is sensitive to the input signal level.

It is, accordingly, a primary object of the present invention to provide a detector for indicating the tracking status of a phase-locked loop.

Another object of the present invention is to provide a circuit for indicating whether or not a digital or analog phase-locked loop is in a locked condition.

Another object of the present invention is to provide a loop tracking status detector which estimates the instantaneous phase error over a specific length of time and uses this measurement to determine if the loop is locked or is in an unlocked condition.

A still further object of the present invention is to provide a tracking status detector for a phase-locked loop which also gives a measure of the frequency offset between an input signal frequency and a local reference frequency.

Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings wherein:

FIG. 1 is a block diagram of a digital delay locked loop monitored with a tracking status detector employing the operating principle of the present invention;

FIG. 2 shows the performance of the up-down counter of the detector when the loop is tracking;

FIG. 3 shows the behavior of this counter when the loop is not tracking;

FIG. 4 shows the operation of the counter when the loop is tracking with a frequency error;

FIG. 5 is a box diagram showing how the operating principle of the tracking detector may be employed to monitor an analog loop; and

FIG. 6 is an alternative arrangement for monitoring a similar analog loop.

Briefly, the tracking status detector of the present invention operates on the principle that the instantaneous phase error reflects the loop tracking status. More specifically, in the digital loop case, the instantaneous phase error between an input and reference code sequence is translated into binary signals which are sent to an up-down counter at a particular sampling rate. When the loop is in lock, the positive and negative counts registered in the counter essentially cancel leaving a residual error that is small. However, when the loop is unlocked, the counter quickly proceeds to accumulate to a value greater than a preset threshold value corresponding to a specific phase error. Thus, whenever this threshold value is reached within a selected time interval, an unlocked indication is given. A second up-down counter fed in a similar manner has its count averaged over a longer time interval to provide a measure of the drift between the input signal frequency and the reference signal frequency.

Referring not to FIG. 1 of the drawings, which illustrates the tracking status detector of the present invention associated with a .tau.-dither delay locked loop in a satellite communication system, it will be seen that the spacecraft part of the system, that is, that portion of the block diagram above the horizontal line, consists of a clock 10 which serves as the timing mechanism for a reference code generator 11 which produces a PN code sequence that is fed to one input of a correlator 12. This correlator consists of a multiplying circuit 13 and a bandpass filter 14 connected in series. The oher input to this correlator is the input code sequence from the ground terminal which is obtained from code generator 15 under the control of a local clock 16 and an incremental phase modulator 26. This code is .tau.-dithered by a square wave from source 17 there .tau. is the dither amplitude which is typically 0.1 chips.

The dither corrupted error signal present in the output of correlator 12, as a result of the phase misalignment between the correlated signals, is squared in circuit 18, and the DC value of the resultant is removed by a DC blocking device 19. Thereafter, the AC signal component is fed to a multiplier 20 which has as its other input a square wave signal obtained from dither circuit 21 which is the counterpart of circuit 17 at the ground terminal. Dither circuit 21 is under the control of the reference code generator 11, and the multiplication process removes the dither present in the error signal.

The output of multiplier 20 after low-pass filtering in 22 is transmitted to the ground terminal where it is processed by a loop filter 23 and a hard limiter 24.

It would be noted that the phase error is the algebraic difference of the reference code and the signal received from the ground terminal. However, due to the characteristics of the .tau.-dither loop, the actual loop control error signal is a non-linear function of the phase error. More specifically, the true timing error is linear for small errors, then limits and returns to zero just past the one full chip condition.

The output from hard limiter output 24 is applied to a sampler 25 which functions to form negative or positive pulses depending upon the sign of the phase error. These binary signals control an incremental phase modulator 26 which updates the phase of the signal produced by local code generator 15. In doing so, it adds or subtracts a fraction of a chip, .DELTA., to the nominal periodic output waveform of T seconds duration. The incremental phase modulator 26 is, thus, the functional equivalent of a limited-input analog voltage control oscillator, responding only to the algebraic sign of the pulse present at its input circuit.

The unlock detector portion of the system is essentially a counter which estimates the actual phase error. More specifically, the output of sampler 25 is fed to an up-down counter 27. When the loop is in lock, the up counts registered therein are essentially equal to the down counts except for any slow drift due to frequency differences between the satellite and ground terminal clocks 10 and 16. Since up-down counter 27 is reset every t.sub.o seconds, t.sub.o is selected such that the frequency error between these clocks .DELTA.f satisfies the relationship .DELTA.f t.sub.o << 1. Under these conditions, the drift is negligible and the counter's accumulated value is an estimate of the true code phase error.

Whenever the loop is unlocked, the counter quickly proceeds to register progressively higher values. A particular threshold count can be set to correspond to any desired positive or negative phase error value. Thus, counter 27 has associated with it a two-side threshold arrangement 28 which established these threshold values N and -N. Whenever either of these values are reached, unlocked indicator 29 is activated. At the same time, a search re-enter system 30 becomes effective to institute acquisition of the incoming signal by search techniques similar to those utilized in analog systems.

FIG. 2 illustrates the phase error expressed in error counts for the in-lock case. The delay in the loop due to, for example, filters or the propagation time between the ground terminal in the noiseless case produces a triangular shape phase error variation with time. The period of the triangular function is four times the loop delay. It will be seen that the count oscillates back and forth and never reaches the threshold .+-.N even without being reset.

FIG. 3 illustrates the situation where the loop is unlocked. Now the count quickly accumulates to the positive or negative threshold, and this occurs within a time interval that is short compared to t.sub.o, the period between reset pulses. For a threshold of .+-.1/2 chip, the time to respond to an unlocked condition T.sub.OL = 1/2/(R.sub.s .DELTA.), where R.sub.s equals the sampling rate and .DELTA. is the phase step modification size in chips.

When the loop is in lock and tracking, the incoming code sequence from the ground terminal and the reference code sequence may have different clock frequencies. To determine this drift, the output from sampler 25 is also fed to a second up-down counter 31. The count so registered is averaged over a predetermined time interval t.sub.1 which is longer than the reset time, t.sub.o, for counter 27. This average count is translated into a frequency offset measurement by circuit 33. Any suitable arrangement can be associated with this portion of the system to provide an appropriate display or alarm when this drift exceeds an acceptable amount. Manual or automatic means may be employed to correct the frequency of clock 16.

FIG. 4 illustrates the accumulated count when the loop is tracking but with such a frequency error. It will be appreciated that the triangular waveforms are now skewed with respect to the horizontal axis and the slope of axis 34 is indicative of the magnitude of the frequency drift.

The system discussed above has been analyzed by a MARKOV random walk model and two sets of probabilities were determined. The first was the probability of detecting the unlocked condition given that the loop was unlocked. At a signal-to-noise ratio 6 DB, it was found that the probability of detection was 0.9999. The second performance parameter was the probability of exceeding the threshold given that the loop was in lock. At the same signal-to-noise ratio, it was found that the probability of one or more false alarms in one year was less than 10.sup.-.sup.5. The frequency drift estimator was found to provide frequency estimates with root mean square errors on the order of 10.sup.-.sup.10.

The locked detector principle of the present invention can be utilized with analog loops as well as with digital loops. FIG. 5 illustrates one such arrangement similar to that employed in the digital loop case. Here, the loop, which is shown in simplified form, consists of a multiplier 40 having the input signal applied to one of its inputs, a low-pass filter 41 and a voltage control oscillator 42 connected in the usual manner. The analog phase error present in the loop is converted to a digital signal by an analog-to-digital converter 44. The resultant digital signal is sampled by switch 45 under the control of circuit 46 which periodically opens and closes this switch according to a predetermined schedule. In thie manner, the analog phase error signal is quantized to a fixed number of bits, and when these bits are summed in the adder/subtractor 47, the valve registered therein is proportional to the existing phase error at the current time.

FIG. 6 shows an alternative arrangement where the analog phase error signal is converted to a single bit by a one-bit analog-digital converter 51. This bit is sampled by switch 53 under the control of circuit 52 in a manner such that the sampling rate is determined by the magnitude of the error signal. The sample signals are sent to an up-down counter 54, and, again, the count registered therein is approximately proportional to the phase error. This arrangement has the advantage that the processing is confined to one-bit samples. However, it does not possess the accuracy of the method employed in the apparatus of FIG. 6.