Logical Solution for Mechanical Clutch Start/Stop Wear

The present invention relates to printers and more particularly to a method and apparatus for controlling the rate of printing by a serial printer.

Serial printers, such as dot matrix printers are well known in the prior art. A fairly common type of such printer involves a plurality of print wires or styli which are arranged in a vertical line. These wires are maintained in a spaced apart arrangement in a print head. The head is supported on a carriage which in turn is caused to traverse a line of movement across a record medium. A common type of dot pattern involves a five by seven matrix. As the carriage shifts the print head through successive columns across a line of movement on the record medum, a five by seven dot pattern of alphanumeric characters is produced on the record medium by selective displacement or extension of the individual print wires in their successive column positions for impacting the record medium through the inked ribbon.

In one type of printer the print head is moved at a constant rate of speed through five successive dot matrix positions and then stops. This process of stop-and-go operation of the print head is accomplished by the use of the motor drive acting through a selectively operable clutch mechanism for communicating driving power to the print head carriage. This stop-and-go operation for each character causes excessive wear of the clutch and driving mechanism and results in objectionable levels of noise. It also has the disadvantage of causing relatively slow printing. Another type of printer commonly referred to as a line printer has the ability to store in memory a full line of characters. The entire print head assembly is moved continuously across a full line on the record medium at a constant rate of speed under the control of a motor and clutch mechanism. At the end of the line the clutch is automatically operated to enable the print head to return to its initial column position but on a following line for printing the next line of stored information. The disadvantage of the line printer is the fact that it needs large memory capacity which results in higher cost and greater size. These and other objections experienced with prior art devices are overcome by the present invention.

It is, therefore, an object of this invention to provide an improved printing mechanism.

It is another object of this invention to provide an improved printer of balanced cost and speed advantages.

Another object of this invention is to provide an improved arrangement for controlling print head movement along a line of movement across a record medium.

A further object of this invention is to provide an improved printer which can print serially a character at a time with pauses to enable print viewing or to continuously print a plurality of characters serially at a given rate.

In accordance with one aspect of the invention, there is provided a printer for connection to a source of printable and control character signals which signals are normally available at a first rate. The printer includes provisions for storing three characters before releasing the signals to effect character printing or to execute control functions represented by such signals, such as carriage return, line feed, etc. The object of storing three characters is to limit the starting and stopping movements of the print head during the printing operation. Once printable character signals are released, the mechanism continues to print until all such character signals stored and all such character signals received in the interim are printed. The mechanism printing rate is designed to exceed the rate at which characters are normally available or received from a source, the percentage of the difference determining the number of characters printed before the mechanism must stop for lack of characters to print. In one embodiment where the printing rate exceeded the character signal receive rate by 10 percent, then for every character signal printed only nine-tenths of the time required for a character signal to be received would have elapsed. This means that approximately 30 characters are printed before the buffer or memory storing the character signals is empty of the initial three character signals and the additional character signals received during this period. This substantially reduces the wear of stopping and starting the print head mechanism. Several overrides are employed. The first is when the data received from the data source does not come to an exact multiple of three. In this case the data is held for a predetermined period of time, approximately 120 milliseconds in one particular embodiment, and then printed. This same delay is used to allow the typist to see the characters already printed by halting print head movement for this period of time. Secondly, any time a control code or delete code appears in the memory or register control circuitry as the next character to be printed, the mechanism will stop. After the control code is processed or delete discarded, the mechanical halt is released. If three character signals are received or the predetermined period of time delay has elapsed, the mechanism will begin movement and printing again.

While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, an illustration of several particular embodiments can be seen by referring to the specification in connection with the accompanying drawings in which:

FIGS. 1 and 2 are combination block and schematic diagrams of a generalized printer embodying the present invention;

FIG. 3 illustrates a typical printing of a character in dot matrix format;

FIG. 4 is a combination block and logic diagram of a detailed embodiment of a printer comprising the present invention.

FIGS. 5A, B and C illustrate graphically the functioning of the logic circuits to control receipt, storage and utilization of data.

Referring to FIG. 1 there is shown, in block diagram form, a generalized printer arrangement useful in explaining the present invention. Data available from a source, such as a keyboard, tape reader or data line, comprises printable character signals and control character signals. In a typical 300 baud type printer the character representing signals would appear at a 33 millisecond interval. The data is available in digital form over lead 2 at the controller portion of the printer arrangement. For purposes of illustration the data will be defined in terms of a 7 bit code, that is, the character is uniquely defined by one of two binary logic states in each of the 7 bit positions. The significance of this will become more apparent during the discussion of the digital logic system to be described for carrying out the particular functions of the invention. In this system there are two distinct signal levels. One of these signal levels will be referred to hereinafter as logic 1 and may be represented by a voltage such as -5 volts. The other logic level will be referred to as logic 0 and will be represented by a lower voltage, such as 0 volts. Binary coded data is applied over lead 2 to the controller portion 3 of printer 5 in bit serial, character serial form. Throughout the specification reference is made to a lead. This is intended to mean either a single or a plurality of connections depending on whether a data signal involves a single or a plurality of signal components. An example of the latter is data in bit parallel format. The controller 3 is shown to include a number of interconnections with the printing and control function execution portion 4. As shown, signals representing printable character and control function characters are supplied over lead 6 to block 4 which responds by printing characters or executing control functions. Printing of characters is controlled by a print command signal applied over lead 7, execution of control functions is controlled by the control code signals applied over lead 9'. Data executed signals applied over lead 9 indicate the printer had responded by printing or executing the control functions. System clock signals over 8 correlate the timing of functions carried out in 3 and 4.

Essentially, controller 3 comprises in one preferred embodiment a memory in the form of shift registers. The memory stores a selected number of character representing signals such as, for example, three character signals in the present illustration -- before the signals are released in sequence over lead 6 for printing or execution of the control functions represented by the signals. Referring to FIG. 2, if we consider the printing function initially, then a signal is furnished over lead 7 to a carriage control mechanism 60 to cause a printing head to move along a line on a record medium. This is illustrated by a carriage 10 carrying a print head 11. The carriage is driven by a mechanical connection 12, to be described, in the direction of the arrows to traverse a line of movement across a record medium 14. In the particular embodiment shown print head 11 comprises a series of 7 printing needles of styli arranged vertically and selectively operated under the control of signals available from 15 so as to be extended to or retracted from the record medium 14. Matrix encoder is any well known circuit for responding to character signals over lead 6 and a print command signal over lead 7 for converting the ASCII code formatted character signals to a 5 by 7 matrix code. Upon being extended, the needles impact onto the record medium through an inked ribbon 16 to produce a vertical dot pattern. As the carriage moves, after having been enabled by a print command 7 applied to 60, along the line of movement on the record medium, the needles are selectively operated in response to signals over 62 during each of the five column positions associated with any character to generate a dot pattern of that character. FIG. 3 illustrates one such dot pattern tracing out the character B.

The manner in which the needles are selectively operated in each of the column positions and along the entire line of print forms no part of this invention. Various well known techniques are available to accomplish this purpose. For example, in one application the pattern of needle movement is controlled by a matrix encoder and the placement of the pattern element by a shutter mechanism associated with the column movement of the carriage as it moves across a line on the record medium. Under the circumstances described, once the carriage is released for movement across a line of type on the record medium, the printer continues to print until all characters stored in the printable 3 character memory and all characters received in the interim are printed. The mechanism printing rate is designed to exceed the received character rate of 33 milliseconds by some 10 percent. This determines the number of characters written before the mechanism must stop for lack of characters to print. If the print rate exceeds the receive rate by 10 percent, then for every character printed only nine-tenths of the time required for a character to be received has elapsed. This means that approximately 30 characters must be printed before the memory or buffer is empty of the initial 3 characters and the additional characters received during this period. It is obvious that this drastically reduces the wear of stopping and starting the mechanism. The starting and stopping is controlled by the controller output signals available on lead 7. The driving means 17, such as a motor, normally drives the mechanical linkage 12 through a clutch 18 and a pulley 19a. In this particular embodiment when printing is to take place, the clutch is operated by 60 in response to signals available on 7 to couple a driving force from the driving means 17 over linkages 20 and 21 to the shaft of pulley 19a. Carriage 10 has attached to it one end of a linkage such as a belt 12. Linkage 12 has its ends connected to carriage 10 and being wrapped around driving pulley 19a and around return pulley 19b. Under these circumstances the carriage is caused to move from the start of the line of printing to the end of the line of printing on the record medium. When the end of the line is reached, clutch 18 is operated by 60 in response to a signal applied over lead 7 to disconnect the further means from driving the carriage and a return mechanism such as a wrap spring 22 is enabled to return the carriage swiftly to the start of line position for printing the next line. Signals available in the form of line feed signals cause the paper to advance to the next line in any well-known manner forming no part of this invention, for printing to resume. Under the circumstances described, several overrides are provided. The first is when the data group received by the controller 3 from the data source does not fill the 3 character register, for example, if it does not come to an exact multiple of three characters. In this case the data is held for a predetermined period of time, approximately 120 milliseconds in one particular embodiment, and then printed. The same delay is used to allow the typist to see his or her work by hesitating for this time. Secondly, any time a control code or delete code is seen by the controller's memory or shift register as the next character to be printed or executed, the mechanism for moving the print head across the record medium is stopped. After the control code is processed or the delete discarded, the print head is permitted to continue its travel across the record medium. If three characters are received or the time-out of the delay period occurs, the mechanism will begin printing again. This and other features of the present invention will be explained in greater detail later.

Before discussing one preferred embodiment of the invention as illustrated in FIG. 4, it will be helpful to set forth a few preliminary remarks concerning digital logic systems.

As previously mentioned, the present logic system involves binary signals in which there are two distinct levels. One of these signal levels will be referred to hereinafter as logic 1 and the other logic level will be referred to as logic 0. These are represented by two different voltages. Generally speaking, the data available from the source not only includes a start bit in the zero bit position but a parity bit in the eighth bit position and a stop bit in thee ninth position. Circuitry exists for separating out these various bits to effect the related control functions.

The logic element denoted with reference numeral 34 in FIG. 4 is a simple AND gate. AND gate 34 may have any number of inputs (designated by the arrows). The operation of AND gate 34 is such that its output will go to logic 1 if and only if all the inputs are at logic 1. Under all other input conditions, the output of the AND gate will be logic 0.

The logic symbol denoted with reference numeral 43 is a simple inverter. As is well known, inverter 43 operates such that its output (denoted by the circle) will be a logic 1 when its input (denoted by the arrow) is a logic 0 and vice versa.

The logic symbol denoted with reference numeral 32 is a simple steered flip-flop. It has three input terminals labeled SS, RS and T. The SS input terminal is the set steering input, the RS terminal is the reset steering input and the T input terminal is the trigger terminal. A logic 1 on the SS input terminal followed by a signal going to logic 0 (as indicated by the circle) on the T input terminal will cause flip-flop 32 to assume the set state. Similarly, a logic 1 on the RS input terminal followed by a signal going to logic 0 on the T input terminal causes flip-flop 32 to assume the reset state. The present state of flip-flop 32 is indicated by its two output terminals labeled 1 and 0. These labels are used to indicate the logic signal present at these outputs when flip-flop 32 is in the set state. That is, the one output terminal will be a logic 1 when flip-flop 32 is set and the zero output terminal will be a logic 0. When flip-flop 32 is in the reset state, the logic signals present at these two output terminals will be reversed so that the one output terminal will be a logic 0 and the zero output terminal will be a logic 1.

The logic element denoted with a reference numeral 41 is a simple OR gate. OR gate operates such that its output will be a logic 1 if any of its inputs are logic 1. Thus, OR gate 41 is a simple non-exclusive OR gate of the well known type. The logic element denoted with a reference numeral 39 is a NOR gate which means the output is a logic 0 instead of a logic 1 if any of its inputs are logic 1.

The serial in-to parallel out shift register 23 is an arrangement of cascaded stages of flip-flops of which only the input stage is steered by the data input and the subsequent stages are steered by its preceding stage. A bit clock input going to logic level 0 causes each stage to assume its steered state.

The parallel in-parallel out storage register 26 comprises a set of static latches which assume a state corresponding to the applied digital data when a logic level 1 control or load signal is applied thereto.

These logic symbols will be used throughout the description of the preferred emobodiment as set forth in FIG. 4.

Before going into a detailed description of one embodiment of the invention as set forth in FIG. 4, it may be desirable to review briefly the general functioning of this circuit arrangement. Data available from source 1 representing printable characters and control characters is applied to the shift register 23 in bit serial, character serial form and stored there under the control of a bit clock signal developed by 24 which will be described shortly. Bit clock 24 produces seven clock pulses in response to the start bit associated with the data available from source 1. Bit counter 25 counts up the seven clock pulses available on lead 100 and is used to control the transfer of the individual seven bit character signals stored in register 23 in succession to registers 26, 27 and 28 and to stop or reset the bit clock 24 to await the start bit of the next data. Clock pulses from clock 24 are related to the fixed bit rate of data available from source 1. These three last mentioned registers constitute the three character memory previously described. The execution of the printing and control functions represented by the individual character signals available at the output of register 28 in not performed by control block 4 unless a control code signal appears on lead 9' indicating that a control function is to be executed or a signal appears on lead 7 indicating that a print command is to be executed. A character signal group stored in the last stage 28 of the character memory remains there until one of two conditions develop. If all three registers 26, 27 and 28 indicate a data character stored therein, then a print command signal appears on lead 7 which in this particular embodiment causes the carriage containing the print head to start advancing across a line on the record medium. Movement of the print head continues along with related printing until either a nonprintable character or control function is detected at the output of the memory 28 or the absence of the character in this last stage is noted, as for example, if all of the characters have been printed. Thereupon the signal on 7 is removed, halting movement of the print head carriage. If the output of register 28 were a control function, then a control code would be developed on lead 9' resulting in the printer executing the related function. When this function has been executed, a data executed signal appears on lead 9. If there were no data in the output of register 28, then printing would halt and remain halted until a data character once again appeared at the output of block 28. The conditions for producing a print command on lead 7 are as follows. Where a character is sensed as being stored in the final stage of the memory, i.e. block 28, but the remaining stages of the memory, that is 26 and 27 are not both holding characters, then a timer 45 is initiated. The timer 29 is designed to produce a timing pulse after a predetermined time duration following the start of the timing sequence. This timing pulse then operates to produce a print command signal on lead 7. In one particular embodiment the predetermined time interval was selected to be 120 milliseconds. The figure of 120 milliseconds is dimensioned to be sufficiently long to enable three characters to be stored in the memory comprising registers 26, 27 and 28 but not too long to become a delay nuisance to the typist. In the situation where data is available from the source at 30 characters per second, about 66 milliseconds would be required to receive two characters which would complete the three characters stored in memory. Thus, the time delay was designed to be more than the 66 milliseconds, and 120 milliseconds was selected because of operating performance requirements. Thus, if a character is sensed in the last stage of the memory, timer 45 provides sufficient time for the earlier stages 26 and 27 to receive any new characters before producing a print command on lead 7. The end result of this arrangement is that as long as printable characters appear at the output of 28, the printer continues to print in response to carriage movement of the print head. Any time a control function character is detected, carriage movement is halted, printing stops and the control function is immediately executed. Printing is recommenced only if data appears in all three stages of the memory or the predetermined time delay has elapsed after a data character has been identified in the output stage 28. Under the circumstances previously described, the mechanism printing rate is designed to exceed the rate at which characters are normally available or received from the source 1 by a given percentage -- in this case 10 percent such that the printing rate is 33 characters per second. This means that approximately 30 characters could be printed in succession before the memory comprising 26, 27 and 28 is empty of three character signals. This substantially reduces the wear caused by stopping and starting of the print head mechanism. In addition, the invention permits the machine to operate on an incremental basis, that is printing a character at a time on a stop-and-go basis depending on the data stream. The present invention also permits the execution of a control function in the middle of a data stream, followed by a continuance of the printing on the same line when the control function is executed. For example, a stream of characters could be printed, then a reader or punch could be turned on or a bell rung and then printing resumed for the balance of the line. This feature is not readily available in prior art arrangements. The printing after the control functions have been executed can occur on a continuous rate basis or a stop-and-go basis, a character at a time, depending on how the data appears or is received from the source.

For purposes of simplicity, the data source 1 is shown as supplying data bits defining individual characters over one line to shift register 23 and the start bit associated with each character signal over a separate line to the bit clock 24. Generally speaking, the data available from the source not only includes a start bit in the zero bit position but a parity bit in the eighth bit position and a stop bit in the ninth position. Circuitry exists for separating out these various bits to effect various control functions. For the purposes of simplicity in explaining this invention, however, the source is shown as furnishing its start bit over a separate line to bit clock 24, and the parity and stop bits are ignored. Thus the start bit applied to bit clock 24 produces a set of seven pulses corresponding to the seven data bits available from the data source 1. These are applied over lead 30 in serial form to the register 23 to shift in the successive data bits associated with each character into its appropriate parallel bit position. Data shifted into register 23 appears in parallel form on the seven output leads shown associated therewith, and it remains there until it is replaced with the succeeding character data being applied from data source 1. The seven data bits representing a character stored in register 23 are then applied over the parallel lines for storage in register 26 under the control of a signal developed by AND gate 31. AND gate 31 has applied to its input the output from bit counter 25, the system clock signals available on lead 8 from source 4 and the signal developed at the zero output stage of flip-flop 32. When all three inputs to AND gate 31 to to a logic level 1, the data character in register 23 is stored in register 26. Bit counter 25 produces a logic 1 when it has counted in seven data bits as established by the bit clock 24. System clock pulses at a logic level 1 in one particular embodiment occurred at 100 kilohertz rate in order to properly time and process the data stream being fed to the printing and control function execution mechanism 4. Flip-flop 32 produces a logic 1 on its zero output lead when the flip-flop 32 goes to its reset state. This occurs when a data character in 26 has been stored in a subsequent register 27, and will be described shortly. Thus, when all signal input stages to AND gate 31 go to a logic level 1, data from 23 register is stored in register 26. Bit counter 25 produces an output pulse after a count up to seven bits. This signal which contributes to the transfer of data into storage register 26 is also applied to the SS input terminal of flip-flop 32 to cause the one output terminal to go to a logic level 1 and the zero output terminal of 32 to go to zero on the occurrence of the next zero in the output form system clock 8. And gate 33 has also applied to its input a signal from the zero output terminal of flip-flop 35. The output logic level is zero for the condition where there is a data character stored in register 27. Since no character is stored in register 27, the zero output terminal is at a one state. AND gate 33 responds to the level 1 logic signals applied to its input lead to produce a logic level 1 signal for application to AND gate 34. AND gate 34 responds to the output of gate 33 and the system clock signals available from 8 to supply a logic level 1 signal to register 27 causing the data character in 26 to be applied to register 27. The logic level 1 output of gate 33 is also stored in through a feedback loop to the reset RS input terminal of flip-flop 32 restoring the one output terminal of flip-flop 32 to a zero state at the next system clock zero. The same output is applied to the SS input terminal of flip-flop 35 causing its logic level 1 output terminal to go to the logic level 1 state. In effect flip-flop 32 has been reset and flip-flop 35 has been set. In a similar manner, AND gate 36 responds to the output signal from flip-flops 35 and 38 to control AND gate 37 for loading register 28 with the data available in 27 under the control of system clock pulses available over lead 8. AND gate 36 also reset flip-flop 35 and sets flip-flop 38. Heretofore we have described how the data characters are clearly received from data source 1 and tranferred in bit parallel character serial form successively through the various stages of the memory comprising registers 26, 27 and 28. Data character stored in register 28 is next evaluated to determine whether it represents a control function or a printable character. The present invention is described for purposes of simplicity as involving data bit coding in the ASCII format. This is an American Standard Code. In this Code the control function code is recognized as containing a logic level zero in the bit 6 and 7 positions and a delete code as containing level one in all seven bit positions. NOR gate 39 responds to logic level zeros in bit 6 and 7 positions state to produce a logic level 1 at its output for application to OR gate 41. AND gate 40 responds to logic level 1 signals appearing on all seven of its inputs to produce a logic level 1 at its output. OR gate 41 responds to either of these conditions to apply a logic level 1 signal to AND gate 42. AND gate 42 also has applied to its input a signal developed at the one output terminal of flip-flop 38. This one output terminal is at a logic level 1 when final stage of the memory contains a data character stored therein. Under the circumstances therefore that a data character is stored in 28 and that either this character is a control code or a delete code, OR gate 42 responds to produce a control code signal over lead 9'. Printer 4 responds to this control code to execute the particular control function represented by the data character stored in 28. When this control function has been executed, a data executed signal is applied over lead 9 to the RS input signal of flip-flop 38 to reset flip-flop 38, removing the control code signal from lead 9' to the logic level zero appearing at the one output terminal of 38 and applied to the AND gate 42.

A printable character appearing in the output stage of register 28 is identified by neither a control code nor delete code being detected by gates 39 and 40. Under these circumstances, a logic level zero signal is developed at the output of 41 which is applied to AND gate 44 after being inverted in inverter 43. AND gate 44 responds to this logic level 1 signal and to a logic level 1 signal appearing at the one output terminal of flip-flop 38 indicating that a data character has been sensed in storage register 28 to produce a logic level 1 signal on its output lead for application to the timer 45. Timer 45 responds to the signal applied to its start terminal to begin timing out a pulse which will appear 120 milliseconds after the start of the timer. This output pulse at logic level 1 is applied to the OR gate 46. OR gate 46 responds to the output of timer 45 to apply logic level 1 signal to the SS input terminal of 47. Flip-flop 47 produces a logic level 1 signal on its one output terminal upon the occurrence of the next system clock signal applied to its T input terminal. This output from 47 applied over lead 7 causes the carriage carrying the print head to start traversing a line on the record medium. Thus, when timer 45 had timed out to produce a pulse on its output lead under the circumstances where data character has been detected in 28 and no data characters have been received into registers 26 and 27 the 120 microsecond delayed pulse delivered by timer 45 through OR gate 46 actuates print control flip-flop 47. This permits the solitary character in 28 to be printed even though there are no characters in 26 and 27. On the other hand, if registers 26 and 27 also contained characters prior to the time out of timer 45, then this would have been noted by the three input signals applied to AND gate 48 from the one output terminal of flip-flops 32, 35 and 38. Under these circumstances, OR gates 48 produces a logic level 1 signal for application to OR gate 46. OR gate 46 applies a logic level 1 signal to the SS input terminal of print control flip-flops 47 resulting in a logic level 1 signal being applied from its one output terminal to the time 45 resetting the timer to its original start position and also demanding the printer 4 to commence printer in response to the signal developed on lead 7. As each printable data character is executed by printing in block 4, a data executed signal is applied over lead 9 to the RS input terminal of flip-flop 38 resetting it. As each character available from 28 is printed, flip-flop 38 is reset permitting the next character to be moved in from the preceding storage register. This process of printing continuously proceeds until the control or delete code is detected by gate 39 or 40 or no data character is sensed in registers 27 and 28. This latter situation is sensed by the NOR gate 49. When neither the one output terminal of 38 nor the one output terminal of flip-flop 35 is in a logic 1 state indicating that a data character is stored in 27 or 28, then NOR gate 49 produces a logic level 1 signal at its output for application to OR gate 50. OR gate 50 responds to the signal from 49 for applying logic level 1 signal to the RS input terminal of flip-flop 47 resulting in a removal of the print command signal from the one lead of flip-flop 47 thereby halting printing action. OR gate 50 also responds to detection of a control or a delete code being developed by gates 39 and 40 to halt printing by removing the print command signal from lead 7.

FIG. 5A illustrates graphically the functioning of the logic circuits of FIG. 4 to carry out the purposes of acquiring data into the registers by means including blocks 1, 24, 25 and 23.

FIG. 5B illustrates graphically the functioning of the logic circuits to move data through the three storage registers to the utilization means such as a printer taking into account whether printable or control characters are involved and data contents, if any, of the storage registers.

FIG. 5C illustrates graphically the functioning of the logic circuits to control printing or the execution of control functions by the printer.

The memory may be replaced with one in which data is processed in bit serial, character serial form, as for example a circulating memory with the desired data being extracted in proper succession for controlling the operation of the printer to print characters a character at a time or to execute the related control functions. The memory may be a delay line or a shift register with the data being stored by circulation until outputted. Generally speaking, this would involve storing and shifting serially "X" number of "N" bit characters, or for example, three characters of seven bits each. The dynamic storage register would be X times N bits capacity, would receive each bit serially and circulate it for storage purposes until gated out. The number of characters in the register would be monitored and the next character to be processed by printing or executing a control function would be sensed. The method of utilizing the circulating data would be as before. If the next character to be processed is a control code, the print head would be stopped, if moving, and the control function executed. If the next character is a printable character or code, the timer would be initiated which eventually would cause this character and any successive characters to be printed if the time out occurred or when the prescribed number of characters were stored in the register. The printable characters stored and any printable characters acquired while printing would be printed until the circulating register was cleared of all characters or a control code detected.