CW Interference Canceller (CWIC)

The present invention relates to doppler tracking systems and more particularly, to doppler tracking systems where interference signals are suppressed and a signal for tracking is generated.

Heretofore, doppler tracking systems have been highly susceptible to velocity deception jamming. Velocity deception jammers (sometimes called velocity-gate stealers) intercept the transmitted radar signal, introduce a frequency shift, and retransmit it at a very high power level. Initially the frequency shift is small so that the jamming signal enters the passband of the doppler filter of the victim radar and captures its doppler-tracking AFC loop. Then the frequency shift is increased and, since the AFC loop is now tracking the stronger jamming signal, it is pulled away from the target doppler signal. After sufficient separation is achieved, the jamming signal is turned off or its program is recycled, so that the AFC loop no longer has a signal to track. It must then attempt to reacquire the target doppler signal. It may fail to do so, or it may lock onto another deception signal transmitted by the jammer.

Various attempts have been made to counter velocity jamming. For example, sensing the presence of the jamming signals and opening the AFC loop for as long as the jamming signal is in the doppler filter passband; limiting the tracking capability of the AFC loop so that it will not follow jamming signals that are rapidly changing frequency; and providing information to the AFC loop from an external source to assist in maintaining lock on the target doppler signal. The first example has the disadvantage that the doppler signal from a maneuvering target can leave the doppler filter passband while the AFC loop is open. The second example essentially defeats the purpose of the AFC loop in that it will not be able to track highly maneuverable targets and could still track jamming signals that are of slowly changing frequency. The third example has the serious disadvantage of requiring a second radar.

The present invention provides a system which overcomes the disadvantages of prior known systems by detecting the presence of CW interference signals and generating a target signal which permits the AFC loop to track without a loss of capability when a weaker target doppler signal is in the presence of strong CW interference.

An object of the invention is to provide an AFC loop doppler tracking system with the capability of tracking without being degraded when strong CW interference is present.

Another object of the invention is to provide an AFC loop doppler tracking system that requires no target information provided by means external to the tracking system,

And still another object is to provide a tracking system which generates a filtered target signal in which CW jamming in the doppler filter passband has been essentially eliminated.

Other objects and many of the attendant advantages of this invention will become readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings wherein:

FIG. 1 is a block diagram of a conventional frequency-lock AFC loop used for doppler tracking modified in accordance with the teaching of the invention.

FIG. 2 is a block diagram of the interference signal detector and target signal generator for incorporation in the tracking system of FIG. 1.

Referring to FIG. 1, there is shown in block diagram form a doppler signal tracking loop including a voltage controlled oscillator 10 providing an output which is fed to mixer 12. Also fed to mixer 12 is the RF or IF target signal which appears at input terminal 14. The output of mixer 12 is fed to doppler filter 16 which provides an output to hard limiter 18 and output terminal 20 through switch 22 and to CW interference canceller 24. The output of hard limiter 18 is fed to frequency discriminator 26 which provides a control voltage to oscillator 10 through loop filter 28. One output of CWIC 24 is fed to switch driver 30 for controlling the position of switch 22. When there is no jamming signal (known as speed-gate stealer) present, switch 22 connects the output of doppler filter 16 directly to hard limiter 18. When there is a speedgate-stealer jamming present in the passband of doppler filter 16, it is sensed by CWIC 24 and a control signal is fed to switch driver 30 to move switch 22 to disconnect doppler filter 16 from hard limited 18 and to connect CWIC 24 in service between doppler filter 16 and hard limiter 18. CWIC 24 provides an output signal that is free of the jamming signal and a signal that is a near replica of the target doppler signal in manner described below.

Referring now to FIG. 2, the operation of CWIC 24 will be described by showing that: the primary output is a near replica of the weaker of two sinusoidal input signals; a switching signal is generated to configure a combining network so that it adds or subtracts as required depending on the order of the two input frequencies; and CWIC 24 is switched into or out of the AFC loop as appropriate depending on the presence or absence of the jamming signal.

Let the weaker desired signal be represented by S cos .omega..sub.S t and the stronger interfering signal be represented by J cos (.omega..sub.J t + .theta.), where S and J are constants such that S <<J, .theta. is an arbitrary constant, and .omega..sub.S and .omega..sub.J are the frequencies of the two signals (in radians per second). It is assumed that .omega..sub.S and .omega..sub.J are within the passband of doppler filter 16 in FIG. 1 but that they are not precisely equal. The input at terminal 110 to envelope detector 112 of FIG. 2 is thus

To simplify notation, let

Then, using trigonometric indentities, e.sub.1 can be written

where

With S<<J, J,

Thus,

Assuming .vertline. x-y .vertline.<<y, (that is, assuming .vertline. .omega..sub.S -.omega..sub.J .vertline.<<.omega..sub.J), the signal e.sub.1 will then have amplitude modulation S/Jcos(x-y), and phase modulation, S/Jsin (x-y).

The output of e.sub.2 of envelope detector 112 is proportional to the envelope of the input e.sub.1 :

High pass filter 112 should be designed to reject the dc term in Eg. 7, without introducing appreciable phase shift, so that its output e.sub.3 is proportional to the sinusoidal component of e.sub.2 :

Hard limited 116 removes the amplitude modulation on e.sub.1. Its output is

The signals e.sub.3 and e.sub.4 are applied to balanced modulator 118, the output of which is proportional to the product:

Also, the signals e.sub.3 and e.sub.4 are shifted by 90.degree., e.sub.3 by wideband 90.degree. phase shifter 120 and e.sub.4 by 90.degree. phase shifter 122. The outputs are, respectively, ##EQU1##

(To understand why there are two cases to consider in equation 11, note that

Suppose, for example, that .theta. = 0. Then whether .omega..sub.S >.omega..sub.J or .omega..sub.S <.omega..sub.J, the input cos[(.omega..sub.S -.omega..sub.J)t] is the same signal so long as .vertline..omega..sub.S -.omega..sub.J.vertline. is the same. Thus, the output of phase-shifter 122 must be the same signal in both cases. For example, suppose first

then from equation 13, x-y = 5t and cos (x-y) = cos 5t. Let the output of the phase-shifter with this input be sin 5t. Now suppose

then x-y = -5t and

The phase-shifter has the same input as before. Thus the output must again be sin 5t. But, in the first case its representation is

sin 5t = sin (x-y),

whereas in the second case its representation is

The outputs, e.sub.6 and e.sub.7, of the 90.degree. phase-shifters 120 and 122, respectively, are applied to balanced modulator 124. The signal out of balanced modulator 124 is then

by using the trigonometric identity

we have

From Eqs. 10, 14, and 16,

Thus, if the parameters are set so that

and if combining network 126 sums the balanced modulator outputs e.sub.5 and e.sub.8 when .omega..sub.S <.omega..sub.J and takes their difference when .omega..sub.S >.omega..sub.J, then the output of the combining network is

Signal e.sub.9 which appears at terminal 128 is one of the outputs of CWIC (FIG. 1, terminal 22) and has the same amplitude as the weaker component of the CWIC input e.sub.1. It also has the same frequency .omega..sub.S except for a small amount of frequency modulation.

The spectrum of e.sub.9 consists essentially of a line at frequency .omega..sub.S and two small sideband lines at frequencies .omega..sub.S .+-.(.omega..sub.S -.omega..sub.J). That is,

where, since S<<J, we have

so that

Thus, the output spectrum consists essentially of a desired component at frequency .omega..sub.S, plus two undesired components, one at frequency 2.omega..sub.S -.omega..sub.J, and one at frequency .omega..sub.J. With S<<J, the amplitude of the desired component will be much greater than the amplitudes of the undesired components.

In the above derivation, it has been assumed that the combining network 126 either adds or subtracts the balanced modulator outputs e.sub.5 and e.sub.8 according to whether .omega..sub.S, the frequency of the smaller, desired signal, is less than or greater than .omega..sub.J, the frequency of the larger signal. The relative magnitudes of the frequencies .omega..sub.S and .omega..sub.J are determined by means of frequency discriminator 130 and phase comparator 132.

The input to frequency discriminator 130 is e.sub.4, which by equation 9, is

The output of e.sub.10 of frequency discriminator 130 is proportional to the deviation of the instantaneous frequency of e.sub.4 from the center frequency of discriminator 130. That is,

where .omega..sub.0 is the center frequency of the discriminator 130. It is assumed that the dc component of e.sub.10 is eliminated so that

This signal is then compared in phase comparator 132 with signal e.sub.3, which by equation 8, is

In phase comparator 132, the inputs e.sub.3 and e.sub.10 are hard limited into constant amplitude square waves and then multiplied and filtered to produce a dc output proportional to the sign of (.omega..sub.J -.omega..sub.S):

The switching logic signal e.sub.11 is thus a positive voltage when .omega..sub.J >.omega..sub.S and a negative voltage when .omega..sub.J <.omega..sub.S. The signal e.sub.11 controls a switch in the combining network 126 that configures it into the required add or subtract mode.

The switching logic signal e.sub.11 is zero only when .omega..sub.S -.omega..sub.J, that is, when there is only one frequency component at the input to CWIC 24. The output of the absolute value circuit 134,

appears at output terminal 136 and is used to activate switch driver 30 in FIG. 1 to bring CWIC 24 into the AFC loop when two frequency components appear at input terminal 110.