Circuit Arrangement for Generating a Sawtooth Deflection Current Through a Line Deflection Coil

The invention relates to a circuit arrangement for generating a sawtooth deflection current through a line deflection coil in an image display apparatus, which circuit arrangement comprises a deflection network including the deflection coil, a trace capacitor and a retrace capacitor and a first diode through which the deflection current flows during part of the trace interval whilst during the remainder of the trace interval this current flows through a second diode and a controllable switch, which switch and which second diode are connected in parallel with the first diode, the circuit arrangement further comprising an inductive element which is connected to the switch and is coupled to the deflection network via a third diode, and a transformer which has a core of a magnetic material and a winding of which is coupled, in series with a capacitor, to the deflection network.

Such a circuit arrangement is described in "IEEE Transactions on Broadcast and Television Receivers," August 1972, volume BTR-18, Nr. 3, pages 177 to 182, and is a combination of a line deflection circuit and a switched-mode supply voltage stabilizing circuit, the controllable switch being used to perform both the said functions. This known circuit arrangement has the advantage that it can be fed with an unstabilised supply voltage and is capable of supplying a satisfactorily stabilized deflection current, a stabilized high voltage and, if desired, auxiliary voltages, the stabilization being obtained by control of the conduction time of the swtich.

When such a circuit arrangement is to be designed, amongst other problems the three following ones arise. Firstly care must be taken to ensure that the maximum voltage set up across the switch (a transistor) during the retrace interval does not exceed the permissible limit value for this element. Secondly the variation of the conduction time of the transistor must be capable of accommodating the supply voltage variations to be expected. Thirdly the (stabilized) trace capacitor voltage applied to the deflection coil during the trace interval must be selectable at will, for with a given deflection coil this voltage determines the intensity of the deflection current produced.

The said problems are not independent of one another. If, for example, the trace voltage is low, the maximum collector voltage of the transistor also is low; it may be further reduced by making the conduction time of the transistor as short as possible. It will therefore be clear that several degrees of freedom are required. One degree of freedom is available to a certain extent, namely the transformation ratio between two windings of the inductive element, one winding being connected between a terminal of the supply voltage source and the junction point of the collector and the second diode, whilst the other winding, which is coupled to the first one, is connected to the third diode, for the choice of the said ratio enables a freer choice of the trace voltage. However, the two other problems, specifically that of maximum collector voltage, are not solved thereby.

It is an object of the present invention to provide a circuit arrangement having one more degree of freedom, permitting the maximum permissible collector voltage to be freely determined, and for this purpose the circuit arrangement according to the invention is characterized in that the inductive element is connected via the third diode to the series combination of the abovementioned series capacitor and part of the transformer winding.

The introduction of a new parameter not only enables the maximum collector voltage to be reduced without the trace voltage being affected but also proves to enable a larger range of supply voltage variations to be accommodated. Hence, the step according to the invention permits of designing a circuit arrangement in which conflicting requirements can simultaneously be satisfied.

In a possible embodiment in which the inductive element has a winding the circuit arrangement is characterized in that the winding of the inductive element is wound on the transformer core.

Embodiments of the invention will now be described, by way of example, with reference to the accompanying diagrammatic drawings, in which

FIG. 1 is a circuit diagram showing schematically the basic elements of an embodiment of the circuit arrangement according to the invention,

FIG. 2 shows waveforms of voltages produced in said embodiment,

FIGS. 3a and 3b show graphs which may be used in the selection of the parameters, and

FIG. 4 is a circuit diagram of a modified part of the circuit arrangement of FIG. 1.

The circuit arrangement shown in FIG. 1 includes a driver stage Dr to which signals from a line oscillator, not shown, are applied and which delivers switching pulses to the base of a switching transistor Tr. One end of a primary winding L.sub.1 of a transformer T.sub.1 is connected to the collector of the transistor Tr, which is of the n-p-n type, the other end of the winding L.sub.1 being connected to the positive terminal of a direct-voltage source B to the negative terminal of which the emitter of the transistor Tr is connected. This negative terminal may be connected to the earth of the circuit arrangement.

A trace capacitor C.sub.t is connected in series with a line deflection coil L.sub.y of the image display apparatus, not shown further, of which the circuit arrangement of FIG. 1 forms part, the resulting series combination being shunted by a diode D.sub.1 having the conductive direction shown and by a retrace capacitor C.sub.r. The capacitor C.sub.r may alternatively be connected in parallel with the coil L.sub.y. The said four elements represent the schematic circuit diagram including the basic elements of the deflection section only. This section may, for example, in known manner be provided with one or more transformers for mutual coupling of the elements, with devices for centering and linearity correction and the like.

A secondary winding L.sub.2 of the transformer T.sub.1 is connected to the anode of a diode D.sub.3, and the anode of a diode D.sub.2 is connected to the junction point A of the elements D.sub.1, C.sub.r and L .sub.y. The cathode of the diode D.sub.2 is connected to the collector of the transistor T.sub.r whilst the cathode of the diode D.sub.3 is connected to a tapping Q on a winding L.sub.3 of a transformer T.sub.2. One end of the winding L.sub.3 is connected to the point A, the other end being connected to earth via a capacitor C.sub.1. The core of the transformer T.sub.2 carries further windings across which voltages are produced which serve as supply voltages for other components of the image display apparatus. FIG. 1 shows one of said windings, the windings L.sub.4 , which by means of a rectifier D.sub.4 produces a positive direct voltage across a smoothing capacitance C.sub.2. One of said windings, for example the winding L.sub.4, is the high voltage winding, so that the voltage set up across the capacitor C.sub.2 is the high voltage for the final accelerating anode of the display tube (not shown). The free ends of the windings L.sub.2 and L.sub.4 are connected to earth, and the winding senses of the windings shown are indicated in the Figure by polarity dots.

The operation of the circuit arrangement is similar to that described in the abovementioned paper and may be summarized as follows. During a first part of the line trace interval the diode D.sub.1 is conducting. The voltage across the capacitor C.sub.t is applied to the deflection coil L.sub.y through which a sawtooth deflection current i.sub.y flows. At a given instant the transistor TR becomes conducting. When in about the middle of the trace interval the current i.sub.y reverses direction the diode D.sub.1 is cut off, so that the current i.sub.y then flows through the diode D.sub.2 and the transistor Tr. At the end of the trace interval the transistor Tr is cut off. As a result an oscillation, the retrace pulse, is produced across the capacitor C.sub.r whilst the energy derived from the source B and stored in the winding L.sub.1 causes a current to flow through the diode D.sub.3. When the voltage across the capacitor C.sub.r has become zero again, the diode D.sub.1 becomes conducting: this is the beginning of a new trace interval. The diode D.sub.3 remains conducting until the transistor Tr is rendered conducting, the energy stored in the winding L.sub.2 being transferred to the winding L.sub.1. Stabilisation is provided, for example, by feeding back the voltage across the capacitor C.sub.t to the driver circuit Dr, in which a comparison stage and a modulator ensure that the conduction time of the transistor Tr is varied so that the said voltage and hence the amplitude of the deflection current remain constant. Compared with the known case in which the cathode of the diode D.sub.3 is connected to the point A instead of to the tapping Q operation is different, the difference being as follows. In the known case the current passed by the diode D.sub.3 flows to earth via the diode D.sub.1 during the first part of the trace interval. In the arrangement shown in FIG. 1, during this same part energy is stored in the series combination L.sub.3, C.sub.1. The voltage v.sub.A across the capacitor C.sub.r, the voltage v.sub.c at the collector of the transistor T.sub.r and the voltage v.sub.1 across the winding L.sub.1 are plotted against time in FIGS. 2 a, 2b and 2c respectively. The symbol T indicates the line period, .tau..sub.1 indicates the retrace interval, .tau..sub.2 that part of the period T in which the transistor Tr is non-conducting, and .tau..sub.3 = .delta. T indicates the part of the period T in which this transistor is conducting. The number .delta. is the ratio between the time .tau..sub.3 and the period T.

The voltage v.sub.A consists of the retrace pulse of amplitude V during the time .tau..sub.1 and is zero during the time .tau..sub.2. At the instant at which the transistor Tr is rendered conducting, i.e. the instant of transition t.sub.1 between .tau..sub.2 and .tau..sub.3, the voltage v.sub.C becomes substantially zero. Thus the volage V.sub.B of the source B is set up across the winding L.sub.1.

In the circuit arrangement of FIG. 1 two ratios are significant, namely the transformation ratio between the windings L.sub.1 and L.sub.2, i.e. the ratio between the number of turns of the winding L.sub.1 and that of the winding L.sub.2, which is equal to 1 : p, and the ratio of the turns number of the entire winding L.sub.3 and that of the part of this winding between the tapping Q and the end connected to the capacitor C.sub.1, which ratio is 1 : m. First it will be assumed that the points Q and A coincide (m = 1).

During the time .tau..sub.3 the voltage cross the winding L.sub.2 is equal to -pV.sub.B. During the time .tau..sub.1 the voltage v.sub.c is equal to V/p + V.sub.B. Let V.sub.o be the direct voltage across the capacitor C.sub.t, if the capacitance of this capacitor is large enough, or the direct voltage component of the voltage across this capacitor, if it has a comparatively small capacitance for the purpose of the S correction; in either case it is equal to the mean value of the voltage v.sub.A, for no direct-voltage component can be set up across the coil L.sub.y. The capacitor C.sub.1 has a large capacitance, so that a direct voltage equal to V.sub.o is set up across it. The following equation applies: ##EQU1##

The mean value of the voltage across the winding L.sub.3 also is zero, so that the equation applies: ##EQU2## In this formula the integral can be substituted, Yielding

At given values of the ratios .delta. and p the diode D.sub.2 will conduct during the time .tau..sub.1. Because during this time the diode D.sub.3 is conducting, the windings L.sub.1 and L.sub.2 will be short-circuited by the diodes D.sub.2 and D.sub.3 , causing the retrace pulse across the capacitor C.sub.r to be clipped and the deflection current to be distorted. U.S. Pat. Application No. 443,863 filed Feb. 19, 1974 describes steps for avoiding such an effect, for example by including in series with the diode D.sub.2 a transistor which is cut off during the time .tau..sub.1. A capacitor C.sub.3 is connected between the ends of the windings L.sub.1 and L.sub.2 or between tappings thereon for the purpose of preventing the occurrence of parasitic oscillations which may be produced by the leakage inductance between the said windings in a manner such that no line-frequency voltage is set up across the capacitor C.sub.3. FIG. 1 shows the case where p <1.

The maximum value of the collector voltage v.sub.c of the transistor is equal to ##EQU3## where .alpha. is the ratio V/V.sub.o which depends upon the retrace ratio Z = .tau.1/T. The maximum value of V.sub.c is obtained when V.sub.B has its maximum value V.sub.B max, for which .delta. has the value .delta..sub.min, for from the relationship (1) it follows that .delta. and V.sub.B are inversely proportional to one another because the voltage V.sub.o is maintained constant.

The voltage V.sub.o can be chosen by choosing the ratio p, so that the deflection current .sub.y is determined for a given deflection coil L.sub.y. However, from the above it follows that the maximum value of the voltage V.sub.c, which is highly critical for the transistor, is not controllable. Moreover, the relationship (1) can be written:

V.sub.o = p .delta..sub.min . V.sub.B max = p .delta..sub.max . V.sub.B min, where V.sub.B min is the minimum value of V.sub.B for which .delta. = .delta..sub.max, and from which follows: ##EQU4## The ratio .delta..sub.min has its minimum value .delta..sub.1 if the instant t.sub.1 coincides with the middle of the trace interval, and .delta..sub.max has its maximum value .delta..sub.2 if the instant t.sub.1 coincides with the beginning t.sub.o of the trace interval. Hence the above ratio cannot exceed 2, so that the arrangement cannot accommodate larger variations of the voltage V.sub.B.

According to the invention the points A and Q do not coincide. The voltage across the winding L.sub.3 is equal to v.sub.A - V.sub.o so that the voltage v.sub.Q in the point Q is equal to v.sub.Q = V.sub.o + m(v.sub.A - V.sub.o) = mv.sub.A + (1 - m) V.sub.o. With the aid of the waveform of the voltage v.sub.A of FIG. 2a the waveform of the voltage v.sub.1 across the winding L.sub.1 between the positive terminal of the source B and the collector of the transistor Tr can be plotted (FIG. 2c), allowing for the fact that the diode D.sub.3 is conducting during the times .tau..sub.1 and .tau..sub.2.

Thus we have: ##EQU5## during time .tau..sub.3 : v.sub.1 = - V.sub.B. Writing the condition for the mean value of the voltage v.sub.1 being zero after some calculations yields. ##EQU6## The maximum value of the collector voltage v.sub.c is ##EQU7## from which follows: ##EQU8## after substitution of the formula (2). It can be shown that this function steadily decreases with decrease of the ratio m. It is plotted in FIG. 3a for z = 0.2, from which follows .alpha. .apprxeq. .pi./2z .apprxeq. 7,8, and with .delta..sub.min = .delta..sub.1 = 1/2 (1 - z) = 0.4. The Figure shows that by making m less than 1 a reduction of the maximum collector voltage is obtained and that this result is independent of the ratio p.

From the formula (2) the following relationship can be derived: ##EQU9## ##EQU10## This function also is independent of the ratio p and it increases as m decreases. It is plotted in FIG. 3b for .delta..sub.min = .delta..sub.1 = 0.4 and .delta..sub.max = .delta..sub.2 = 0.8 (Z = 0.2), so that the entire .delta. range is used, whilst the Figure shows that a larger range of supply voltage variations can be accommodated, for when m is less than 1 the ratio V.sub.B max /V.sub.B min exceeds 2.

Similarly to the preceding case, the voltage V.sub.o can be determined by the choice of the ratio p. If the means described in the abovementioned U.S. Pat. Application No. 443,863 are to be dispensed with, it is found that an upper limit can be set to p. The diode D.sub.2 will just be conducting during the time .delta..sub.1 if the lowest value of the voltage V.sub.c which is found in practice, that is ##EQU11## is equal to the voltage V. In the above expression, according to the formula (2), ##EQU12## from which we can derive: ##EQU13##

The above will be explained by means of two numerical examples. If the voltage V.sub.B can vary between 230 volts and 345 volts (with a mains voltage of 220 volts) V.sub.B max /V.sub.B min is less than 2, so this does not provide difficulty. If the transistor Tr is not capable of withstanding a voltage exceeding 1200 volts, it will be seen from FIG. 3a that m = 0.64. From the formula (2) it follows that ##EQU14## with .delta..sub.min = .delta..sub.1 and ##EQU15## so that .delta..sub.max = 0.56 < .delta..sub.2. The formula (5) yields: ##EQU16## so that V.sub.o = 0.87 times 161 = 140 volts.

If now the voltage V.sub.B can vary between 115 volts and 345 volts (the mains voltage is 110 volts or 220 volts), then V.sub.B max /V.sub.B min = 3. FIG. 3b shows that m = 0.38, for which FIG. 3a yields V.sub.c max = 2.9 times 345 = 1000 volts. Formula (2) yields: ##EQU17## whilst ##EQU18## so that V.sub.o = 0.54 times 183 volts = 99 volts. Because m cannot be increased, a higher V.sub.o if desired requires p to exceed 0.54, and hence the step according to the abovementiond Patent Application must be used.

Similarly to what is the case in U.S. Pat. Application No. 473,771, filed June 1, 1973, the cores of the transformers T.sub.1 and T .sub.2 of FIG. 1 may be one and the same core, that is to say the windings L.sub.1, L.sub.2 and the winding L.sub.3 may be coupled to one another in spite of the fact that voltages of different waveforms are set up across the said windings. This is possible because the said voltage waveforms are not affected by the coupling, since the voltages V.sub.o and V.sub.B are "hard," that is to say they are externally impressed, and hence are not affected by the coupling. The currents flowing through the windings, however, are affected. In the lastmentioned Patent Application it is shown that the operation of the circuit arrangement is not adversely affected thereby, but on the contrary important advantages are obtained. It should be mentioned that instead of the tapping Q an additional winding may be wound on the same core as the winding L.sub.3, which additional winding has a smaller number of turns than the winding L.sub.3 and is included between the cathode of the diode D.sub.3 and the junction point of L.sub.3 and the capacitor C.sub.1.

Formula (5) shows that the ratio m should not be excessively small, because in this case the ratio p also is small, with the result that large currents flow on the secondary side of the transformer T.sub.1. In addition, large currents then will flow through the leakage inductance of the said transformer, which gives rise to ringing at the instant t.sub.1. Furthermore difficulties will arise in designing the abovementioned embodiment using a single transformer. If for these reasons the formula (5) is not complied with, that is to say if p is made greater than the preferred value p.sub.max, the steps according to the abovementioned U.S. Pat. Application No. 443,863 have to be employed. This requires an additional transistor, which is expensive, or an additional diode, which does not prevent the production of a high V.sub.c max, whilst it was the very purpose of using a low m to obtain a low V.sub.c max.

In practice there is a leakage inductance between the two parts of the winding L.sub.3. In FIG. 4, which shows only part of the circuit arrangement, this leakage inductance is shown as an inductance L.sub.5 between the point Q and an imaginary tapping Q' on the winding L.sub.3. The inductance L.sub.5 prevents abrupt current transistions which in conjunction with the stray capacitances may give rise to ringing. This can be avoided by connecting a capacitor C.sub.4 between points A and Q and a capacitor C.sub.5 between the point Q and the junction point of the winding L.sub.3 and the capacitor C.sub.1. If the ratio between the reactances of C.sub.4 and C.sub.5 is equal to that between the numbers of turns of the upper and lower parts of the winding L.sub.3, no alternating voltage is set up across the inductance L.sub.5 so that no ringing can occur. The parallel connection of the capacitor C.sub.r and of the network C.sub.4, C.sub.5 together with the inductive components of the circuit arrangement results in a resonant frequency the period of which is about equal to twice the time .tau..sub.1.

Hereinbefore it has been assumed that the capacitance of the capacitor C.sub.1 is sufficiently large to enable the voltage across it to be regarded as constant (= V.sub.o). It should be mentioned that this is necessary only if one or more of the auxiliary voltages produced by means of windings of the transformer T.sub.2 are obtained by means of trace rectification.