Integrating Component Measuring Device

As elements, resistors, inductors and capacitors are generally used. Though each of these elements is manufactured individually, it is difficult to manufacture pure elements. Capacitors, for example, have some leakage resistance, and resistors include some capacitance and inductance. In most cases, each of the three kinds of elements includes impurities of the two other units.

A.C. bridge method is usually applied to make precise measurement of value of the element including impure components. However, in order to balance the bridge circuit, for instance, the voltage across the standard component or the standard itself must be adjusted. Additionally, to minimize or compensate phase difference caused by the variable voltage source or the variable standard, expensive circuit parts or complicated circuit composition are needed. As a result, the conventional instrument is expensive and lacks reliability in spite of taking more time for adjustment.

The primary object of the present invention is to provide an improved instrument for measuring resistance, capacitance and inductance of elements.

The present invention eliminates above described disadvantages and provides a component measuring device having very simple circuit composition without losing the advantage of the null method in A.C. bridge method.

Another object of the present invention is to provide a component measuring device in which an integrator is charged by a voltage proportional to the resistance component or a voltage proportional to the reactance component and discharged by a reference voltage, the charging and discharging times being compared and the values of the components being displayed in digits.

In one embodiment of the present invention, the element to be measured (such as resistor, capacitor and inductor) and the reference element are connected in series, and a reference signal is provided at one end of the serial circuit while a variable signal is automatically adjusted to null at least one of the function voltage (and the current function) at the common junction of the element to be measured and the reference element. When the null voltage is balanced, the variable signal is divided into the in-phase component and the 90.degree. shifted component (both in view of the reference signal). The integrator capacitor is charged from initial level for a certain time with the D.C. signal corresponding to the value of the in-phase component or the 90.degree. shifted component, and then the charged integrator capacitor is discharged till the initial level with a certain D.C. signal corresponding to the reference signal. The ratio of the discharging time to the charging time is counted by the electric counter and the value of the component to be measured is displayed in digits.

FIG. 1A is the block diagram of a preferred embodiment of the present invention.

FIG. 1B shows a modification in the arrangement of the element to be measured and of the reference element, this modification being suitable for measuring inductances.

FIG. 2A is a time diagram illusrating measuring of the capacitance of a given element.

FIG. 2B is a time diagram illustrating measuring of the parallel conductance of the same element.

FIG. 2C is a time diagram illustrating measuring of the dielectric dissipation factor of the same element.

Referring to FIG. 1A, 10 is the element to be measured and 12, the reference component. The capacitor to be measured, 10, implies capacitance Cx and parallel equivalent conductance Gx, 12 is the reference conductance Gr. Numerals 14 and 14' indicate A.C. signal sources of common frequency. 16 indicates a voltage detective circuit, and 18 is a voltage control circuit. A.C. voltages e.sub.r and e.sub.x, in opposite phase of each other, are provided to both terminals "a" and "b" from the A.C. signal source 14 and 14' respectively. The voltage at the connection "c" of both components 10 and 12 is compared with the reference potential (or the ground potential) at the voltage detective circuit 16, and the control signal matching with the value of the difference voltage is transmitted to the A.C. signal source 14' over the voltage control circuit 18. If the voltage gain in said detective circuit is sufficiently larger than 1, the value of said voltage e.sub.x is automatically controlled so that the voltage at the said common junction "C" becomes zero.

The reference signal voltage e.sub.r and the variable signal voltage e.sub.x are supplied to the standard resistor 27 or the standard capacitor 29 through switches 21 and 23 and 25, and lead into the input of the synchronous rectifier circuit 33 and 35 through the current-voltage converter 31. The said reference signal e.sub.r is fed to the input of the first rectifier circuit 33 through 90.degree. phase shifting circuit 32, and the reference signal e.sub.r is fed to the input of the second rectifier circuit 35. 43 is the first integrator circuit including integrator capacitor 42, and 46 is the second integrator circuit including integrator capacitor 45, respectively, and 47 and 49 are null level detectors. The output voltage E1 of the said first rectifier circuit 33 is lead into the first integrator 43 through the switch 37, and the output of the said integrator 43 is connected to the null detector 47. The output voltage E2 of the second rectifier circuit 35 is, in the same manner, lead into the second integrator 46, and the output is connected to the null detector 49. 50 indicates a logic circuit to control said switches and a gate circuit of a counter according to the output signals of the said null detectors 47 and 49. The output pulse Pc of a clock pulse generator circuit 51 is fed to the said logic circuit 50 to synchronize the control operation with the period of the A.C. signal e.sub.r. 53 and 55 indicate gate circuits and 57 and 59 indicate digital displays. The measuring procedure according to the present embodiment of the invention is as follows:

First, if the voltage at the common junction "C" of the element to be measured, 10 and the reference element 12 is balanced to zero by the closed loop circuit including reference element 12, voltage detective circuit 16 and voltage control circuit 18. The current flowing to the element 10 by virtue of the reference signal voltage e.sub.r is proportional to the admittance of the said component 10, and then the value of the variable signal voltage e.sub.x is proportional to the said admittance. The relation between the reference signal voltage e.sub.r and the variable signal voltage e.sub.x when balanced, can be expressed as follows: ##EQU1##

Second, the contacts of switches at the time t.sub.0 are assumed as follows: 21-22b, 23-24a, 25-26b, 37-36a, and 39-38b. Then the output voltage of the current-voltage converter 31, e.sub.3, can be expressed as follows: ##EQU2## Here, K is a constant and Gs, the conductance of the standard resistor 27. Then the said signal voltage e.sub.3 is converted into the D.C. voltage E1, proportional to the capacitance Cx by means of the first synchronous rectifier circuit 33. If the A.C.-D.C. converting ratio at this time is .eta.1 (.eta.1=mean value of E1/r.m.s. of e.sub.3), the said D.C. voltage E1 can be expressed as follows: ##EQU3## The D.C. voltage E1 is charged to the capacitor 42 through the serial resistor 41. Assume the initial charge of the capacitor 42 at the time t.sub.0 is zero. Taking note of the integrator charging time (T1), the input voltage e.sub.3 of the rectifier circuit in this case is a sinusoidal voltage, and the output voltage is the pulsating voltage of the fullwave rectification and not complete D.C. Therefore, unless the input voltage to the integrator 43 is integrated for the complete one period of the pulsating voltage, an error will arise. Thus, the charging time T1 should be selected using the period .tau.m' (1/fm) of the A.C. signal as follows:

n.sub.1 here is a certain value selected, for example, 10,000 according to the full scale value of display 57 (59). This will be easily achieved by means of the clock pulse P.sub.c synchronized with the reference signal e.sub.r and by means of the logic circuit 50 using this synchronized clock pulse to control the switches. Thus, as illustrated in FIG. 2A, the output voltage E.sub.01 of the integrator 43 continues to increases from the time t.sub.0 to the time t.sub.1, the slope thereby being proportional to the capacitance Cx.

Next, at the time t.sub.1 switches connect 21 to 22a, 23 to 24b, 25 to 26a using the control signal from logic circuit 50 (except for 37 and 39). The input signal voltage e'3 of the first rectifier circuit 33 at the time is expressed as follows:

So, the output voltage E1 is

The D.C. voltage E'1 is in the opposite polarity to the D.C. voltage E1 and is constant. This means the charge of integrator capacitor 42 at the time t.sub.1 is discharged with a constant slope by said voltage E1. Then the output voltage E.sub.01 of the integrator 43 is detected to be zero by the null detector 47 (the time is then t.sub.2), and the logic circuit 50 is controlled by the null detector signal. Thus the first operation is completed.

In the integrator capacitor 42, the charged quantity of electricity in the time T1 and the discharged quantity of electricity in the time T2 (from t.sub.1 to t.sub.2) is the same, so capacitance Cx is directly read by counting the number of clock pulses Pc corresponding to discharging time T2. That is, gate circuit 53 is opened for the time T2 by the control signal from logic circuit 50, and the clock pulse Pc passing during the time is counted by the display 57 to indicate the result (n.sub.2).

The charging and the discharging quantity of the electricity q.sub.1 is as follows:

K1, here is the constant value of integrator 43. Thus, the following equation (8) can be derived from the above equation (7). ##EQU4## The unknown capacitance C.sub.x can directly be read on the display 57 by counting n.sub.2.

It is well understood from the above equations (7) and (8) that the characteristic values K, .eta., and k1 of the current-voltage converting circuit 31, phase discriminator circuit 33 and integrator 43, respectively, have the same effect upon charging cycle and discharging cycle of the capacitance 42, and that they cancel each other. Thus, measuring error will not occur unless the constant values change during a single measuring cycle (T1 + T2). Thus, the present invention makes best use of the advantage of the null method without having the disadvantages of using a galvanometer, the characteristic of which may cause measuring errors.

First, at the time t.sub.0, the relations between switches and junctions are as follows: 21-22b, 23-24a, 25-26b, 37-36b, and 39-38a. At this time, input signal voltage e.sub.3 of the second synchronous rectifier circuit 35 is obtained by equation (2), and the output D.C. voltage E2 is obtained as follows: ##EQU5## wherein .eta..sub.2 is the conversion efficiency of the second rectifier circuit 35. The above D.C. voltage E2 is charged to the integrator capacitor 45 for a certain period T1 through the serial resistor 44.

Next, at the time t.sub.1, after the period T1, switch 21 is changed over to the junction 22a. The output rectification voltage E2' is then as follows:

After the time t.sub.1, the integrator capacitor 45 is discharged by the said D.C. voltage E2', and output voltage E.sub.02 of the integrator 46 is detected to be zero level (the time is then t.sub.3) by the null detector 49, and with this null detect signal logic circuit 50 is controlled. As a result, the second gate circuit 55 is opened for the time T3 (from t.sub.1 to t.sub.3), and the number (n.sub.3) of the clock pulses Pc having passed the gate circuit 55 during the time T3 is displayed by the display 59.

The charging and discharging quantity of the electricity q.sub.2 in the integrator capacitor 45 is as follows:

k.sub.2 is the constant value of the second integrator 46. Gx is obtained from the above equation (11)

As the above equation (12) shows, the unknown conductance Gx can be directly read on display 59 afterr counting n.sub.3.

First, the relation between the switches and the junctions at the time t.sub.0 is 21-22a, 23-24b, 25-26a, 37-36a, and 39-38b. At this time, the output D.C. voltage E1 of the first rectifier circuit 33 is the same as the said equation (6). That is:

The time T4 to charge the above rectified voltage E1 to the integrator capacitor 42 is selected by multiplying said time T1 by the reference dielectric dissipation factor as follows:

The dielectric dissipation factor Ds is temporarily defined with the conductance Gs of the resistance 27 and the capacitance Cs of the standard capacitor 29 as follows:

If the frequency of the AC signal fm =1MHz, Cs=100pF, Gs=1m.nu., then Ds=1.592, and the time T4 of the above equation (13) is the constant value of 1.592 T1.

Next, at the time t.sub.4 when the above time T4 has ended, switches change as follows: 21-22b, 23-24a, 25-26b, and 39-38a (except for 37-36a). At this time, the D.C. voltages E1' and E2 obtained in the output of the rectifier circuits 33 and 35 are expressed as follows: ##EQU6## In the first integrator 43, the quantity of the electricity charged to the capacitor 42 during the time T4 by virtue of the D.C. voltage E1 is discharged by virtue of the rectified voltage E1' after the time t.sub.4. If the integrator output E.sub.01 is zero potential at the time t.sub.5 after the time T5, (the number of pulses during the time T5 is n.sub.5) the quantity of the electricity q.sub.3 in the charging and discharging cycle is as follows:

and from the above equation the following equation is obtained: ##EQU7##

Next, in the second integrator 46 during said time T5, the capacitor 45 is charged by D.C. voltage E2 shown in the said equation (14), and the quantity of the electricity q.sub.4 is expressed as follows: ##EQU8## and associated with the equation (16), the above equation (17) can be converted as follows: ##EQU9## Then, at the time T.sub.5, the positions of switches are 21-22a, 37-36b(23-24a, 25-26b, 39-38a are left unchanged). The integrator capacitance 45 is discharged by the D.C. voltage E2' shown by the equation (10) and if the quantity of the electricity is zero at the time t.sub.6, the discharging quantity q.sub.4 (corresponding to said charging quantity) can be expressed as follows:

From the above equation (17') and (18), following equation is obtained: ##EQU10## As above equation (19) shows, the second gate circuit 55 is opened during the time T6 (from t.sub.5 to t.sub.6), and the number n.sub.6 of the clock pulses having passed the circuit 55 is counted and indicated by the display 59 to read directly the unknown dielectric dissipation factor.

Above description relates to measuring of the capacitance Cx of a capacitor, parallel equivalent conductance Gx, and the dielectric dissipation factor Dx, and in the case of measuring either Cx or Gx, a single integrator circuit is sufficient. As a reference component 12, in this case, a resistor is used but a capacitor might be used too.

In the case of measuring the inductance Lx of an inductor element, its series equivalent resistance Rx and the magnetic ddissipation factor DL (=Rx/.omega.Lx) of the unknown element 10', (FIG. 1B), the reference signal e.sub.r is fed to a reference resistance 12' (its value is Rr) as shown in FIG. 1B, and the constant current (e.sub.r /Rr) flows to the element 10'. Thus, the voltage drop e.sub.x across said element 10' can be taken as a value proportional to (Rx + j.omega.Lx). As the measurement is almost the same as the above described capacitor, measurement further description can be omitted.

In the described embodiment of the present invention with for example, fm=1MHz and n.sub.1 =10,000 a LCR meter having a counting speed of 10ms and a resolution is 10.sup.-.sup.4 may be employed as counting device.