Waveform Synthesis Using Switching Circuits

This invention relates to electrical waveform synthesis using switching circuits and in particular but not solely switching circuit waveform synthesisers for use as AC motor drives.

An alternating current waveform can be derived or synthesised from a direct current by appropriately switching the DC source. Equipment for producing an AC waveform from a DC source are known as inverters. These inverters may be either static or non-static. Static inverters are much preferred and may be formed using suitable solid state devices such as thyristors or triacs. Whether the inverter be static or non-static the output is a complex waveform, whereas it is frequently desirable that the output be sinusoidal. Sinusoidal waveforms can be produced be suppressing unwanted harmonics contained in the switching circuit output waveform. For example, a low pass or integrating filter can be used to pass only the lower frequency or fundamental waveform which is generally a sinusoid. In some instances the electric circuit or load into which the waveform is injected acts as its own integrating filter. Such is the case with the AC electric motor. Such a motor can be driven from a simple inverter producing a square wave output. If, as would be expected to be the case, the motor was 3-phase then by the use of a 3-phase inverter the line voltage will have reduced low order harmonics even though the phase voltages are square waves. However, it is desirable to drive such motors by an AC waveform more closely approximating a sinusoid.

To allow for complete control over the inverter output waveform characteristics it is usual to use an external pulse source to switch the inverter. The inverter switching pulses are produced by low power circuitry and the output from this circuitry (which would normally be a unidirectional voltage waveform) is used to switch a static inverter per se which in turn switches the power to the load (as a bi-directional voltage waveform). The pulse source circuitry may be conveniently formed using integrated circuits. It is relatively easy using such techniques to synthesise a complex waveform having a variable fundamental frequency which may then be used to appropriately switch an inverter. This feature is particularly significant since the availability of high power variable frequency AC means that AC motors can be used in variable speed applications. In most situations the mains supply is AC and, accordingly, variable speed AC motor drives must normally include associated rectifier and smoothing equipment to produce the inverter input DC. This equipment is however already required for DC motor drives which at present predominate. A variable speed application where the use of an AC motor would be particularly attractive, and incidently where the mains supply is DC, is as a power source for vehicles.

A requirement of an AC motor is that if it is desired to vary motor speed by varying the supply frequency, the supply voltage should also be varied proportionally to ensure a constant voltage-time product and thus constant flux. A known method for satisfying this requirement is to vary the voltage of the inverter DC supply by the use of a chopper. For reasons of simplicity and economics it would be desirable to control the inverter output amplitude by appropriately controlling the low power switching pulses.

A known technique for synthesising a low frequency sinusoid using two state switching circuits is to generate a pulse width modulated waveform, the width of the pulses being related to the amplitude of the desired sinusoid at any instant. This pulse width modulated waveform is then passed through an integrating filter designed to pass only the desired sinusoid. A common method of obtaining the necessary pulse width modulated waveform is to compare a reference sinusoid with a high frequency carrier having a trianglular or saw-toothed waveform. This method requires complex linear and digital circuitry, particularly for 3-phase systems which require both phase balance and voltage amplitude control over wide frequency and amplitude ranges. It would be desirable for such a synthesiser to utilise purely digital circuitry especially as the derivation of a 3-phase sinusoidal signal is thereby simplified.

It is therefore an object of the present invention to provide a method and apparatus to go at least some way towards satisfying the abovementioned desiderata.

It is a further object of the present invention to provide a method and apparatus fo synthesising a complex waveform which upon integration will approximate a sinusoid the frequency and amplitude of which can be varied.

Accordingly, in one aspect the invention consists of a method for synthesising a waveform which upon integration will approximate a sinusoid of controllable amplitude and frequency. This is accomplished by generating at least one base square wave having the selected frequency and chopping this square wave once each half cycle with a chopping pulse. The chopping pulse width is set according to the desired amplitude of the sinusoid.

In a further aspect the invention consists in a waveform synthesiser for producing a waveform which upon integration will approximate a sinusoid of controllable amplitude and frequency. The synthesiser includes a square wave generator producing at least one base square wave and a variable width chopping pulse generator. Logic circuitry associated with the square wave generator sets the chopping pulse location relative to each half cycle of each square wave. Means are provided for mixing or gating each square wave with the chopping pulse to produce as an output a chopped square wave. The fundamental component of the integral of this output has an amplitude which is a function of the chopping pulse width.

Preferred forms of the invention include the following features:

1. a three-phase output waveform,

2. a high power static inverter output stage,

3. a second control square wave which is Walsh multiplied with the chopped base square wave to produce a pulse width modulated output waveform which contains lower hamonics and has a fundamental frequency equal to the difference between the fundamental frequencies of the base and control square waves, and

4. a tri-state static inverter output stage with appropriate switching circuits which reduces the demand on the switching capabilities of the static inverter power switches.

The invention is particularly useful as a variable frequency AC motor drive .

The preferred forms of the present invention will now be described with reference to the accompanying drawings in which:

FIG. 1 is a block diagram of one form of waveform synthesiser in use as a three-phase AC motor drive,

FIG. 2 is a set of waveform diagrams corresponding to the waveforms at selected points in the synthesiser of FIG. 1,

FIG. 3 is a block diagram of a second form of waveform synthesiser in use as a three-phase AC motor drive,

FIG. 4 is a set of waveform diagrams corresponding to the waveforms at selected points in the synthesiser of FIG. 3,

FIG. 5 is a block diagram of a third form of waveform synthesiser in use as a three-phase AC motor drive,

FIG. 6 is a set of waveform diagrams corresponding to the waveforms at selected points in the synthesiser of FIG. 5,

FIG. 7 is a set of waveform diagrams corresponding to the waveforms at selected points of a variation of the synthesiser of FIG. 5,

FIG. 8 is a block diagram of a timing pulse generator producing pulses for use in waveform synthesisers, particularly when used as three-phase AC motor drives,

FIG. 9 is a block diagram of a synthesiser of the type shown in FIG. 3 showing an alternative method of providing the synthesiser with timing pulses, and

FIG. 10 is a set of waveform diagrams corresponding to the waveforms at selected points in the synthesiser of FIG. 9.

In the first embodiment of the invention three-phase square waves are generated using a twisted ring counter from which three-phase square waves of exact phase balance may be obtained whatever the frequency at which they are generated. These square waves when integrated will approximate a sinusoid. Amplitude control of the resulting sinusoid is obtained by chopping the square waves from one amplitude state to the other twice during each wave period. The frequency of the sinusoid is varied by varying the frequency of the clock pulse generator feeding the counter.

If the wave period T is measured from the instant of transition from the lower to higher level, at least a portion of the first chopping pulse must be within the range T/6 to T/3 and at least a portion of the second chopping pulse must be within the range 2T/3 to 5T/6, such that the area of each segment in the resultant wave is dependent on the width of the chopping pulse.

Preferably, the maximum width of each chopping pulse is T/6, and if the chops lie entirely within the stated ranges, the mean line voltages will then decrease from a maximum to zero as the width of the chop increases from zero to its maximum value.

Referring now to FIGS. 1 and 2, the three-phase square waves from a twisted ring counter are chopped in the manner described, before being used to switch a static inverter. The chopping pulse generator produces a pulse y six times every period having a duration T.sub.s /6 where T.sub.s is a selected period. The pulse is then inverted and the inverted y chops each phase square wave twice during every period within the ranges and up to the maximum width stated above. Since the period of pulse y is fixed, the width of chop pulse y increases automatically as T is increased. The result is an automatic control of the mean of the variable frequency three-phase line voltage amplitude which is useful in achieving a simple variable speed, constant torque output, control of a three-phase AC motor. FIG. 1 is a block diagram of a circuit which realises this preferred embodiment. A variable frequency clock pulse generator 10 feeds clock pulses at a variable frequency 6f.sub.1 to a twisted ring counter 12 incorporating three J-K flip-flops FF.sub.1, FF.sub.2, FF.sub.3, having utputs Q.sub.1, Q.sub.2, Q.sub.3, and "complemented" or "inverted" outputs Q.sub.1, Q.sub.2, Q.sub.3, respectively. The three-phase square waves of period T.sub.1 = 1/f.sub.1 are obtained from the outputs Q.sub.1, Q.sub.3, Q.sub.2. The clock pulse generator 10 also triggers the chopping pulse generator 14 which produces positive going pulses y at the rate of one every T.sub.1 /6 . An example of a simple chopping pulse generator would be a monostable multivibrator. The chopping pulse period for each phase is selected by channelling the inverted pulse y through AND gates 16a, 16b, and 16c which are "opened" or "enabled" by signals from the EXCLUSIVE-OR gates 18a, 18b, and 18c, as shown. The latter EXCLUSIVE-OR gates are fed with signals from the ring counter 12 as shown in the figure, such that the AND gates are enabled in correct sequence twice during each period for each phase. The channelled y pulses from the AND gates 16 are then mixed with the three-phase square waves Q.sub.1, Q.sub.3, Q.sub.2 in EXCLUSIVE-OR gates 20a, 20b, and 20c respectively. The resulting chopped square wave phase signals V.sub.1, V.sub.2, V.sub.3 from the EXCLUSIVE-OR gates 20 which switch the static inverter 19 are shown in FIG. 2 together with the resulting line voltages V.sub.L1, V.sub.L2, V.sub.L3, across the AC load. At zero chop, when pulse y has width T.sub.1 /6, the original three-phase square wave trains Q.sub.1, Q.sub.3, Q.sub.2 emerge unaltered from their respective EXCLUSIVE-OR gates 20 while at maximum chop, when pulse y has width very much less than T.sub.1 /6, the original square wave trains are chopped to square wave trains of 1:1 mark-space ratio and of three times the original frequency so that the resulting line voltages from the inverter across the load are zero.

Such a simple waveform generator is only of use as an AC motor speed control over limited ranges of speed about the design speed of the motor because of the poor quality of the line voltage waveform.

In a second embodiment of the invention, the quality of the line voltage waveform is markedly improved when the phase voltages V.sub.1, V.sub.2, V.sub.3 are treated as chopped square wave Walsh functions of fixed frequency f.sub.1 and multiplied with another square wave Walsh function of variable frequency f.sub.2. Walsh functions are orthogonal functions analogous to sine and cosine functions and form the basis of a communication theory which is useful in dealing with binary information since Walsh functions may assume the values of .+-.1 only. As with sine functions multiplication of two Walsh functions will yield a difference frequency product. A suitable Walsh function multiplier is an EXCLUSIVE-OR gate (or EQUIVALENCE gate). Such multiplication of V.sub.1, V.sub.2, V.sub.3 as mentioned above will result in the production of three-phase chopped p.w.m. Walsh function waveforms of beat frequency the difference in frequency f.sub.2 - f.sub.1, and of sequency (one half of the average number of switchings per unit time) the sum of the frequencies f.sub.2 + f.sub.1.

Referring now to FIGS. 3 and 4 the same circuit is used to generate the chopped three-phase voltages V.sub.1, V.sub.2, V.sub.3 (these may be referred to as the base voltages) as is used in the simple system previously described except that pulse y of width variable from zero up to 1/6f.sub.1 seconds is used for the chop, and the frequency 6f.sub.1 of the clock pulse generator 10 is preset to a constant value. Another clock pulse generator 11 of variable frequency 2f.sub.2 feeds clock pulses to a twisted ring counter 13 incorporating one J-K flip-flop FF.sub.4 which has an output Q.sub.4. The output from Q.sub.4 is a square wave voltage V.sub.4 of frequency f.sub.2 (which may be referred to as the control voltage) which is mixed with each of the chopped three phase square wave voltages V.sub.1, V.sub.2, V.sub.3 in the respective EXCLUSIVE-OR gates 15a, 15b, 15c as shown in the block diagram of the circuit realisation, FIG. 3. The resulting three-phase chopped p.w.m. waves V.sub.m1, V.sub.m2, V.sub.m3 from the EXCLUSIVE-OR gates 15, which are used to switch the static inverter 19, are shown in FIG. 4, together with the resulting line voltages V.sub.mL1, V.sub.mL2, V.sub.mL3. With this embodiment it should be appreciated that:

a. The pulse width of each unchopped p.w.m. waveform Vm.sub.1, Vm.sub.2, or Vm.sub.3 at any instant of time relates to the instantaneous amplitude of a triangular waveform of fundamental frequency f.sub.2 - f.sub.1 rather than that of a sinusoid of this beat frequency, but this is a significant improvement over the square wave approximation to a sinusoid in the simple system already described.

b. The switching sequency f.sub.2 + f.sub.1 may be made as large or as small as desired so that the number of line voltage pulses per unit time may be adjusted at will.

c. Since the beat or difference frequency f.sub.2 - f.sub.1 may be positive or negative, the direction of rotation of a three-phase AC motor driven by this generator is dependant only on whether f.sub.2 is greater or less than f.sub.1. Reversal of rotation is thus possible without the need for any switching.

d. A programmable chop pulse y is used rather than its inverted form. When used as previously described it controls the balanced mean line voltages V.sub.mL1, V.sub.mL2, V.sub.mL3 between maximum and zero as the programmable chop pulse generator varies the chopping pulse width between 0 and 1/6f.sub.1 seconds. The amplitude of the harmonics are also reduced as the chop width is increased so that when the fundamental voltage amplitude is reduced to zero the three-phase load is not supplied with residual harmonics. When the chop is programmed to the requirements of a particular AC motor it ensures that the desired torque output is obtained from the machine at all machine speeds by controlling the voltage-time product of the supply voltage. This control is both positive and accurate.

In a less preferred variation the control square wave could be chopped before being multiplied with the respective phases of the base square wave.

Such a sophisticated switching system may, in practice, make heavy demands on the ability of the static inverter to switch power rapidly and efficiently. This is particularly so when chop is employed and the switching frequency f.sub.2 + f.sub.1 is high. If this is so, a practical improvement may be introduced to alter the mode of operation of the inverter and thus reduce the inverter switching rate.

The normal two-state mode of operation of the static inverter is that of a switching circuit with each output phase switched to one of two distinct voltage levels only, according to whether the upper level switch or the lower level switch is closed at that instant in time. If the static inverter incorporates a means of feedback across its switches, the switching rate of the inverter may be significantly reduced by a change to a tri-state mode of operation.

Accordingly, in a third embodiment of the invention the inverter phase output may be the result of:

a. The upper level switch being closed so that the output is connected to the upper level d.c. bus voltage, or

b. The lower level switch being closed so that the output is connected to the lower level d.c. bus voltage, or

c. Neither the upper nor the lower level switch being closed so that the output voltage is determined by the load current which will then flow through the feedback means across the switches. If these be feedback diodes and if the load is a significantly inductive circuit, then the phase voltage will swing either to the upper d.c. bus voltage or the lower d.c. bus voltage level so as to ensure the continuation of load current flow through the appropriate feedback diode.

Condition (c) allows an inverter drive circuit which need not produce high switching rate outputs to attain a waveform which upon integration will approximate a sine wave. The upper and lower level switches of the inverter must, of course, be switched independently and it has been found that by mixing the voltages V.sub.1, V.sub.2, V.sub.3 with voltage V.sub.4 in AND gates, both inverter switches will be turned off at appropriate times in the switching sequence. Other methods can of course be used to produce a suitable drive for the tri-state inverter.

Referring now to FIGS. 5 and 6 the same circuit is used to generate the chopped three-phase voltages V.sub.1, V.sub.2, V.sub.3 as is used in the simple system previously described. Like the sophisticated p.w.m. system just described, the frequency 6f.sub.1 of the clock pulse generator 10 is pre-set to a constant value and the pulse y of width variable from zero up to 1/6f.sub.1 seconds is used for the chop. Again, a clock pulse generator 11 of variable frequency 2f.sub.2 feeds clock pulses to a twisted ring counter 13 incorporating one J-K flip-flip FF.sub.4 which has an output Q.sub.4. The output from Q.sub.4 is a square wave voltage V.sub.4 of frequency f.sub.2 which is partially mixed with each of the chopped three-phase square wave voltages V.sub.1, V.sub.2, V.sub.3 in the respective AND gates 17a, 17b 17c and also partially mixed with each of the inverted chopped three-phase square wave voltages V.sub.1, V.sub.2, V.sub.3 in the respective AND gates 17d, 17e, 17f as shown in the block diagram of the circuit realisation, FIG. 5. The three-phase output voltages V.sub.S1, V.sub.S3, V.sub.S5 from AND gates 17a, 17b, and 17c are used to switch the upper level switches S.sub.1, S.sub.3, S.sub.5 respectively, of the static inverter 19 while the three-phase output voltages V.sub.S2, V.sub.S4, V.sub.S6 from AND gates 17d, 17e and 17f are used to switch the lower level switches S.sub.2, S.sub.4, S.sub.6 respectively, of the static invertor 19. The resultant phase voltages V.sub.A1, V.sub.A2, V.sub. A3 from the static inverter are shown in FIG. 6, together with the resultant line voltages V.sub.AL1, V.sub.AL2, V.sub.AL3. Since the phase voltages are load dependent while the inverter is switched off, the voltages at these times are represented by blurred lines. It is apparent that the performance of this system using the tri-state mode of operation of the inverter compares well with that of the sophisticated system already described, while the switching speed of the inverter is significantly reduced.

In another suitable low switching rate inverter drive circuit for switching the inverter in the tri-state mode, the inputs to AND gates 17a, 17b, 17c remain unchanged but the inputs to AND gates 17d, 17e 17f are changed to V.sub.1 and V.sub.4, V.sub.2 and V.sub.4, V.sub.3 and V.sub.4 respectively. In this case the resultant phase voltages from the static inverter are shown in FIG. 7 together with the resultant line voltages V.sub.AL1, V.sub.AL2, V.sub.AL3. Again, since the phase voltages are load dependent while the inverter is switched off, the voltages at these times are represented by blurred lines. Other means of switching the inverter in the tri-state mode are readily available but will not be detailed here.

In any system in which the difference of two frequencies f.sub.2 - f.sub.1 is taken, the difference frequency is very sensitive to small changes in f.sub.2 and f.sub.1. This is especially so when f.sub.2 - f.sub.1 is small and f.sub.1 and f.sub.2 are large. In the speed control of AC motors by the waveform synthesisers of the second and third forms of waveform synthesiser, the difference frequency should be able to be specified at the input and varied continuously or in constant increments through a range of frequencies. It is essential that whatever the difference frequency set at the input, the difference frequency of the output waveform is identical to this at all times. When a stable difference frequency is required, a common method of achieving this is to use one stable master oscillator of frequency f.sub.o and to divide this down to the two frequencies f.sub.1 and f.sub.2 required using digital dividers.

When f.sub.o is a fixed frequency this method is satisfactory for the generation of the fixed clock frequency 6f.sub.1 but it is unsatisfactory for the generation of variable clock frequency 2f.sub.2, since the frequency needs to be set and varied in constant increments throughout the required frequency range. Varying the divisor in constant increments will not of course achieve this. Thus with the second and third forms of the waveform synthesiser, clock pulses of an accurate and stable pre-set frequency nf.sub.2 /m may be generated by dividing the output frequency f.sub.o of a stable high frequency master clock pulse oscillator by f.sub.2 /m in a digital divider of variable divisor f.sub.2 /m. The output pulses of repetition frequency mf.sub.o /f.sub. 2 are then fed into a digital up/reset counter enabled n times/second for 1/n seconds to output in parallel form the serial pulse rate. The count accumulated here is proportional to the period of f.sub.2 and is of value m/n f.sub.o /f.sub. 2. This count is used as the variable divisor of a digital divider which divides the output frequency f.sub.o of the high frequency master clock oscillator. The output pulses of this divider are of the required clock pulse frequency ##EQU1## It should be noted that if n = f.sub.o /K.sub. 2 where K.sub.2 is the fixed divisor of a digital divider which divides f.sub.o to produce n, then the percentage drift of f.sub.2 is the percentage drift of f.sub.o.

Referring now to FIG. 8 (the lower half of the block diagram) and the waveform synthesisers described pulse frequency 6f.sub.1 is obtained by dividing the stable master dock frequency f.sub.o by a constant K.sub.1 made equal to the expected value of f.sub.o /6 f.sub.1 so that again percentage errors in f.sub.1 = f.sub.o /6 K.sub.1 are the percentage errors in f.sub.o. The variable clock pulse frequency 2f.sub.2 is obtained as described. Since frequency f.sub.1 is fixed, the input f.sub.2 may be calibrated exactly as difference frequency ##EQU2## where m is any required scale factor. The input digital latch store 21 accepts input frequency f.sub.2 /m and stores this as the variable divisor of the digital divider 23 which divides the output frequency f.sub.o of the master clock pulse oscillator 22. The clock pulse output of divider 23 of frequency mf.sub.o /f.sub. 2 is fed to count up the digital up-reset counter 24. This counter is enabled f.sub.o /K.sub. 2 = n times a second for 1/n seconds by the output of digital divider 25. Each accumulated count of the counter 24 of value mK.sub.2 /f.sub. 2 is fed to the digital latch store 26 which stores this number, proportional to the period of f.sub.2, as the variable divisor of digital divider 27. The output of this divider is f.sub.o f.sub.2 /mK.sub. 2 and if K.sub.2 = f.sub.o /2 m then the output clock pulses are of the required frequency 2 f.sub.2. Note that since the percentage error in both f.sub.1 and f.sub.2 are the same as the percentage error in f.sub.o and always in the same sense, the percentage error of f.sub.2 - f.sub.1 is simply the percentage error of f.sub.o, whatever the difference frequency.

As can be seen from the upper half of the block diagram of FIG. 8, the chop pulse y for a synthesiser as described may also be realised accurately by digital methods. Clock pulses of frequency f.sub.o /K.sub.c (where K.sub.c = K.sub.1 /N) from the fixed divider 29 are fed to a down/reset counter 30. This counter is reset by clock pulses from the fixed divider 28 which are of period K.sub.1 /f.sub.o = 1/6f.sub.1. Thus in any sixth of a period 1/6f.sub.1, f.sub.o /K.sub.c K.sub.1 /f.sub. o = N pulses count down the counter 30. During each reset period, a variable number K.sub.v which is stored in latch store 31, is read into the counter 30. Since this number K.sub.v is not greater K.sub.1 /K.sub.c = N, a pulse will be obtained from down counter 30 each sixth of a period 1/6f.sub.1 when counter 30 counts through zero. The reset pulse to the counter 30 also resets the NAND gate latch 32 so that y is level 1 and y is level 0. The output pulse from counter 30 which occurs when it counts through zero, sets the NAND gate latch again so that y is level 0 and y is level 1. Thus chop pulse y is accurately at level 1 for K.sub.v /N of a sixth of a period T.sub.1 and this occurs each T.sub.1 /6, where T.sub.1 = 1/f.sub.1. Input K.sub.v is from the input switches controlling beat frequency f.sub.2 - f.sub.1, so the chop y may be arbitrarily but accurately adjusted to any desired value at any beat frequency. This is necessary when the system is used to control the speed of an AC motor, since the chop may be accurately adjusted to obtain the desired amplitude/frequency relationship required for the motor characteristic.

When f.sub.o is a continuously variable frequency, then an alternative and much simpler realisation may be obtained in which two fixed digital dividers are used to generate frequencies f.sub.1 = f.sub.o /K.sub.1 and f.sub.2 = f.sub.o /K.sub.2 . The beat or difference frequency is then: ##EQU3## where the vertical lines imply "the magnitude of". The percentage error in f.sub.D is thus simply the percentage error in f.sub.o. When the master oscillator frequency f.sub.o is continuously variable over the range 0 - f.sub.o - f.sub.o MAX, the difference frequency will be continuously variable over the range 0 - f.sub.D - f.sub.o MAX ##EQU4##

Referring now to FIG. 9, the same circuit is used to generate the chopped three phase voltages V.sub.1, V.sub.2, V.sub.3 as is used in the systems previously described in FIGS. 1 and 3. Chopping pulse y of width variable as required from zero to 1/6f.sub.1 seconds, is used for the chop and the frequency of the clock pulse generator 10 is continuously variable between OHz and f.sub.o MAX. In this simple embodiment K.sub.1 = 6 and the divisor K.sub.2 is fixed at some appropriate value which permits suitable line voltage waveforms to be obtained from the inverter, while the inverter switching rate is kept within permitted limits. It should be appreciated that: ##EQU5## and thus if f.sub.D MAX = 50 Hz, K.sub.1 = 6, K.sub.2 = 8 then f.sub.o MAX = 1200 Hz. The waveforms obtained in this case are shown in FIG. 10.

b. For this simple realisation of the p.w.m. waveforms, while the difference frequency is directly proportional to the frequency of the clock pulse generator f.sub.o, so too is the switching sequency (the sum frequency). Unlike the other methods previously described, since K.sub.2 can be varied the number of line voltage pulses per period can be kept independent of f.sub.o but dependent on the values of K.sub.1 and K.sub.2. If K.sub.1 remains constant the number of pulses per period at any given value of difference frequency f.sub.D, may be adjusted to an appropriate value by switching K.sub.2, provided that the clock pulse frequency f.sub.o is simultaneously switched to maintain the desired f.sub.D. The effect of switching in this manner is akin to mechanical gear changing and can be thus termed "electronic gear changing".

c. If need be, the motor being controlled may be reversed by extending the range of f.sub.D to include: ##EQU6## as 0 .ltoreq. f.sub.o .ltoreq. f.sub.o MAX , by switching f.sub.1 = f.sub.o /K.sub.1 to f.sub.1 = f.sub.o /K.sub.2 at the same time as f.sub.2 = f.sub.o /K.sub.2 is switched to f.sub.2 = f.sub.o /K.sub.1 when frequency f.sub.o = 0 Hz. Alternatively for a three phase output, one pair of the three phase output voltages (preferably the low level logic output voltages) may be interchanged when f.sub.o = 0 Hz to achieve the same effect.

It should be understood that in this specification where a "phase" is referred to this includes the waveform of a synthesiser which has only one output (i.e. a single phase synthesiser) rather than a poly-phase output. Further, is should be understood that, while the preferred embodiments shop in the range of T/6 to T/3 and 2T/3 to 5T/6, chopping in other ranges of the base square wave period could be used.