Low Interelectrode Leakage Structure for Charge-Coupled Devices

This invention relates to charge-coupled devices and, more particularly, relates to a structure which tends to minimize leakage between adjacent electrodes in a charge-coupled device.

For efficient transfer of carriers in charge-coupled devices, it is known that the channel potential must be controlled in the regions between adjacent gate electrodes. This control may be achieved by utilizing overlapping gate structures with two layers of conductive materials. For simplicity of fabrication, however, it is sometimes desirable to utilize nonoverlapping gate structures. For nonoverlapped gate structures, the channel potential between adjacent gate electrodes may be controlled by utilizing a resistive gate structure as disclosed in U.S. Pat. No. 3,728,590, issued to Kim et al and assigned to the same assignee as this application, and as disclosed in "p-channel Charge Coupled Devices with Resistive Gate Structures," Appl. Phys. Lets., USA, Vol. 20, No. 12, pp. 514-516, June 15, 1972.

It has been found, however, that interelectrode material is subject to field-modulated interelectrode conductance. In effect, a series of conductor-insulator-semiconductor (MIS) transistors is formed with the substrate acting as a gate and the electrodes acting as sources and drains. Field-modulated interelectrode conductance has been found for standard charge-coupled structures as well as for the buried-channel structures disclosed in U.S. Pat. No. 3,739,140, issued to R. H. Krambeck.

A charge-coupled device comprises a semiconductor substrate, a layer of insulation covering the substrate, a plurality of spaced-apart electrodes fabricated from doped polycrystalline semiconductor material having a particular conductivity type formed on the surface of the layer of insulation, and regions of interelectrode material located between each of the plurality of spaced-apart electrodes and having a conductivity type opposite to said particular conductivity type.

For a more complete understanding of the charge-coupled device structure of the present invention, reference may be had to the accompanying drawings which are incorporated herein by reference and in which:

FIG. 1 is a cross-sectional view of a portion of a line of charge-coupled elements formed in a continuous semiconductor substrate with a buried-channel layer in the topmost portion thereof;

FIG. 1A is a schematic diagram of the spurious conductor-insulator-semiconductor structure of the prior art;

FIG. 2 is a qualitative graph depicting the relationship between voltage in the buried channel and current and voltage across the undoped interelectrode regions of the prior art; and

FIG. 3 is a graph depicting the relationship between voltage in the buried channel and the current and voltage across the slightly doped interelectrode regions of the present invention.

In FIG. 2, I is the current in the interelectrode material, V is the voltage difference between adjacent electrodes, and V.sub.B is the voltage in the substrate or buried layer. By reference to this Figure it can be seen that a leakage current I will flow between gate electrodes at low gate-to-gate voltages, V, whenever the potential difference, V.sub.B, between the channel and lower-voltage gate (the source of the MIS transistor) exceeds the threshold level of the effective MIS transistor. This field-effect transistor phenomenon is the primary factor affecting the flow of leakage current at low gate-to-gate voltages since (1) leakage current is miniscule below the threshold and (2) the clocking voltages on the polycrystalline silicon gate electrodes can in general be held low enough to not induce space-charge-limited current flow.

A typical charge-coupled device of the buried-channel type such as an area array or shift register will contain a multiplicity of charge-coupled elements such as the charge-coupled element described within the dotted line in FIG. 1. Each element will consist of a conductive gate electrode 20, the associated underlying insulator 30 and the associated underlying bulk substrate consisting, in this embodiment, of n-type layer 31 and p-type substrate 32. Packets of charge will be transferred along the line of charge-coupled elements in the well-known manner by varying the potential on the electrodes in alternating timed sequence. In the embodiment shown in FIG. 1, the elements 18, 20 . . . 26 and the regions of interelectrode material 21, 23 . . . 27 have been formed from a uniform planar layer of a polycrystalline semiconductor material such as polycrystalline silicon. Since a p-type substrate has been used, for bulk substrate 14, the buried-channel structure requires an n-type layer 14a to provide the appropriate conduction characteristics, i.e., to permit electrons to be conveyed along the buried channel. The insulator layer 16 will typically be fabricated from silicon dioxide. The conductive gate electrodes 18, 20 . . . 26 must be sufficiently doped (on the order of 10.sup.19 /cm.sup.3) to provide high conductivity. The regions of interelectrode material 21, 23 . . . 27 have been slightly doped with a p-type dopant such as boron so as to raise the threshold voltage of the effective conductor-insulator-semiconductor field-effect transistors. It should be noted that a pair of reverse-biased diodes is also created but this model is not particularly useful because the operating parameters of charge-coupled devices would not be such as to approach a condition for resistive current flow due to the high sheet resistivity of the regions of interelectrode material.

The relationship between the current I in the regions of interelectrode material and the voltage difference V between adjacent electrodes is shown in the family of constant V.sub.B curves shown in FIG. 2 for undoped polycrystalline silicon having a bulk resistivity of 2 .times. 10.sup.6 ohm cm. It is clear that for a given V.sub.B, the current increases with an increase in voltage difference V between adjacent electrodes; the rate of increase increases as V.sub.B is raised. Essentially, however, a family of constant V.sub.B curves exists with significant currents even for low values of V. It has been found that a slight doping of the regions of interelectrode material with an impurity of conductivity type opposite to the conductivity type of the electrodes causes the family of curves to be discontinuous, i.e., will allow current to flow only if the threshold of the effective conductor-insulator-semiconductor is exceeded.

In a charge-coupled device having a p-type substrate and an n-type buried-channel layer, the regions of interelectrode material between n-type conductive polycrystalline silicon electrodes were doped with boron with a concentration of 5 .times. 10.sup.13 /cm.sup.3. The buried-channel region was maintained at voltages of Ov, +5v, +10v and +15v. At 0v and 5v no appreciable leakage current (less than 10.mu.) between electrodes existed for an interelectrode voltage difference of +14v. At V.sub.B = 10v a leakage current of 120.mu.A was measured for an interelectrode voltage difference of 2v. At V.sub.B - 15v a leakage current of 120.mu.A was measured for an interelectrode difference of about 0.5v. This discontinuity in the family of constant V.sub.B curves is shown in FIG. 3.

In a charge-coupled device having a p-type substrate and an n-type buried-channel layer, the regions of interelectrode material between n-type conductive polycrystalline silicon electrodes were doped with boron having a concentration of 1 .times. 10.sup.15 /cm.sup.3. The buried-channel region was maintained at voltages of 0v, +5v, +10v and +15v. At V.sub.B = 0v and 5v no appreciable leakage current (less than 10.mu.A) between electrodes existed for an interelectrode voltage difference of 15 volts. At V.sub.B = 10v a leakage current of 40.mu.A was measured at V = 2 volts, 62.mu.A at V = 4 volts, 76.mu.A at V = 6 volts, 88.mu.A at V = 8 volts, 95.mu.A at V = 10 volts, 106.mu.A at V = 12 volts and 116.mu.A at V = 14 volts. At V.sub.B = 15 volts the leakage current was 120.mu.A for V.sub.B less than 1 volt.

In a charge-coupled device having a p-type substrate and an n-type buried-channel layer, the regions of interelectrode material between n-type conductive polycrystalline silicon electrodes were doped with boron having a concentration of 5 .times. 10.sup.16 /cm.sup.3. The buried-channel region was maintained at potentials of 0, +5v, +10v and +15v. At 0v and +5v no appreciable leakage current (less than 10.mu.A) between electrodes for an interelectrode difference of 15 volts. At V.sub.B = 10 volts a leakage current of 12.mu.A was measured at V = 2 volts, 18.mu.A at V = 4 volts, 24.mu.A at V = 6 volts, 27.mu.A at V = 8 volts, 29.mu.A at V = 10 volts, 32.mu.A at V = 12 volts, and 34.mu.A at V = 14 volts. At V.sub.B = + 15 volts, the leakage current was 120.mu.A for V equal to about one volt.

For charge-coupled devices of the type described above in Examples 1-3, it was found that boron doping of the regions of interelectrode material at concentrations on the order of 5 .times. 10.sup.17 /cm.sup.3 and greater produced a continuation of the trend towards higher MIS threshold voltages V.sub.B. However, for adjacent electrode voltages V greater than two volts, the so-called 'soft breakdown effect' intervened and the region of interelectrode material was conductive for virtually any finite substrate voltage V.sub.B. Thus, for practical charge-coupled devices, the effective range of boron doping to counteract the field-modulated conductance effect is 10.sup.13 to 10.sup.17 atoms/cm.sup.3. A preferred range would be 10.sup.15 to 10.sup.16 atoms/cm.sup.3 since this would permit substrate voltages of up to 10 volts to exist with limited conduction through the regions of interelectrode material.