Multi-Input Switching Means

1. Field of the Invention

The present invention relates to an isolating multiple input switching, or multiplexing, system.

2. Description of the Prior Art

In prior art multiplex systems, where transformers are used for isolation for the individual input circuits, the switching of the individual transformer circuits must be sufficiently slow to allow the switching transients in the transformer to decay whereby to obtain a reasonably accurate output signal. Further, when the multiplexed signals were amplified in a common, or time-shared, amplifier, it was necessary, in order to maintain the high order of accuracy, to use a very high quality and very expensive amplifier to avoid problems of offset and temperature drift voltages.

It is an object of the present invention to provide an improved isolated multiplexing system which avoids the shortcomings of the prior art systems.

It is another object of the present invention to provide an improved multiplexing system as set forth wherein the scanning of the output signals may be accomplished at relatively high speed.

It is a further object of the present invention to provide an improved multiplexing system as set forth wherein compensation is provided for offset and drift signals of the amplifier.

In accomplishing these and other objects, there has been provided, in accordance with the present invention, a multiple input, or multiplexing, switching system wherein input isolation is accomplished as by input transformer means. The input signals are sequentially switched into the input of a time-shared amplifier at a predetermined switching rate. The output of the amplifier is commutated, as by a plurality of commutating switch means, to a plurality of memory devices. The commutating switch means are actuated synchronously with the input signal switching means but with a shorter close-time than the input switching means. This allows the switching transients to be dissipated before the data signal is applied to the several storage devices. The data stored in the memory devices may be scanned by actuation of a plurality of output or read-out switching means. the read-out switching means may be actuated asynchronously with respect to the input and commutating switching means. These switching means may be actuated at a relatively high speed as required by whatever utilization devices may be connected thereto.

The multiplexing and commutating switches are actuated by a series of spaced pulses. Further switching means is arranged to be actuated during the interval between the actuation of the multiplexing and commutating switches. The further switching means effectively short-circuits the input of the amplifier and at the same time connects the output terminal of the amplifier to a storage capacitor. The signal thus applied to the storage capacitor is representative of the offset and drift signal of the amplifier. Upon subsequent actuation of the commutating switching means, the signal stored on the capacitor is superimposed upon the data signal to provide compensation for the offset and drift of the amplifier.

A better understanding of the present invention may be had from the following detailed description when read in connection with the accompanying drawings in which:

FIG. 1 is a schematic circuit diagram of a multiplexing system embodying the present invention;

FIG. 2 is a wave-form chart useful in explaining the present invention;

FIG. 3 is a schematic circuit diagram of a different embodiment of the present invention;

FIG. 4 is a schematic circuit diagram of another embodiment of the present invention; and

FIG. 5 is a schematic circuit diagram of yet another structure embodying the present invention.

Referring now to the drawings in more detail, there is shown in FIG. 1 a plurality of input circuits IN.sub.l through IN.sub.n, each connected to the primary winding of an isolating transformer T.sub.l through T.sub.n through associated first multiplexing switch elements SW.sub.1l through SW.sub.1n. The secondary windings of the transformers T.sub.l through T.sub.n are connected in parallel through second multiplexing switches SW.sub.2l through SW.sub.2n to the input of a time-shared operational amplifier A. While these switches just discussed have been illustrated as mechanical switches, it is anticipated that these will be solid state switch devices such as field effect transistors.

The output terminal of the amplifier A is connected to a plurality of commutating switches SW.sub.3l through SW.sub.3n, corresponding in number to the number of input circuits. A plurality of memory devices, again corresponding in number to the number of input circuits, represented by the capacitors C.sub.1l through C.sub.1n are connected, respectively, to the output of the amplifier A through the aforementioned commutating switches. A plurality of read-out scanning switches SW.sub.4l through SW.sub.4n are connected, respectively, between the capacitors C.sub.1l through C.sub.1n to an output circuit.

Reference to FIG. 2 will assist in the understanding of the operation of the circuit just described. The multiplexing switches and the commutating switches are controlled from a series of control signals from respective sources designated P.sub.o through P.sub.n. Referring to the chart of FIG. 2, it will be noted that the control pulses P.sub.1, P.sub.2 and P.sub.n are of a relatively long duration. These pulses are applied to control the actuation of the multiplexing switches SW.sub.1l through SW.sub.1n and SW.sub.2l through SW.sub.2n, the pulses being appplied to control those switches directly. It will be noted that the pulses P.sub.1, P.sub.2 . . . P.sub.n occur in time-spaced sequence whereby the switches controlled thereby are actuated sequentially on a predetermined time base as noted on lines A, B and C of the chart of FIG. 2. The control pulses P.sub.o, shown on line D of the FIG. 2 are applied as one input signal to each of a plurality of AND gates G.sub.l through G.sub.n. These pulses are in the nature of clock pulses and occur synchronously with the sum of the pulses P.sub.l through P.sub.n. It will be noted that the pulses P.sub.o are of shorter duration and timed to occur during the latter portion of the period of the pulses P.sub.l through P.sub.n. A second input to the AND gates G.sub.l through G.sub.n, respectively, are taken from the pulses P.sub.l through P.sub.n. Thus, the gates G.sub.l through G.sub.n are sequentially enabled by the pulses P.sub.l through P.sub.n and are turned on by the pulses P.sub.o. The output of the gates G.sub.l through G.sub.n, as seen on lines E, F and G of FIG. 2, are applied to control the actuation, sequentially, of the commutating switches SW.sub.3l through SW.sub.3n. The close time of the several switches is effectively coextensive with the pulse length of the corresponding actuating pulses. Thus, the close time of the commutating switches SW.sub.3l through SW.sub.3n is substantially shorter than the close time of the multiplexing switches at the input of the amplifier. With this arrangement, the switching transients incidental to the actuation of the switches in connection with the isolating transformers have been allowed to dissipate before the corresponding signals are transferred from the amplifier to the memory devices, or storage capacitors, C.sub.1l through C.sub.1n. The output scanning switches SW.sub.4l through SW.sub.4n are actuated independently and asynchronously with respect to the multiplexing and commutating switches. The switches SW.sub.4l through SW.sub.4n are individually actuated, respectively, from signals applied over channel select lines CH.sub.l through CH.sub.n. It may be noted that the actuation of the switches SW.sub.4l through SW.sub.4n may or may not be actuated in sequence and the rate of selection may be much faster or much slower than the predetermined actuation rate of the multiplexing and commutating switches.

Whereas in FIG. 1, the commutating switches SW.sub.3l through SW.sub.3n and the scanning switches SW.sub.4l through SW.sub.4n are active with respect to a post-amplification or high level signal; in the structure shown in FIG. 3, the commutating switches and the scanning switches are operative on a pre-amplification or low level signal.

In the structure illustrated in FIG. 3, the input circuits IN.sub.l through IN.sub.n are also connected to the primary winding of associated isolating transformers T.sub.l through T.sub.n through input multiplexing switches SW.sub.1l through SW.sub.1n, respectively. The secondary winding of the isolating transformers T.sub.l through T.sub.n are connected directly to the memory devices represented by the capacitors C.sub.1l through C.sub.1n by the commutating switches SW.sub.3l through SW.sub.3n, respectively. As before, the multiplexing and commutating switches are actuated by pulses from the pulse sources P.sub.o through P.sub.n. Here too, the actuation of the commutating switches SW.sub.3l through SW.sub.3n are operated synchronously with the multiplexing switches SW.sub.1l through SW.sub.1n but have a relatively shorter close time. In this structure, the data signal stored in the memory capacitors are the relatively low level signals derived directly from the transformer secondary windings. The plurality of scanning output switches SW.sub.4l through SW.sub.4n as before asynchronously scan the data stored on the storage capacitors C.sub.1l through C.sub.1n. Here, however, the scanned signals are applied as input signals to the operational amplifier A, the output of the amplifier then becomes the output of the system.

In FIG. 4, there is shown a structure which is substantially identical to that shown in FIG. 1 with the exception that the isolating transformers are replaced with so-called flying capacitors. Thus, the input circuits IN.sub.l through IN.sub.n are connected, respectively, to a plurality of double pole, double throw switches SW.sub.5l through SW.sub.5n. A plurality of input capacitors C.sub.2l through C.sub.2n are connected respectively across the common poles of the double pole, double throw switches. These switches serve both as multiplexing switches and as isolation means. As before, the switches are sequentially actuated by signals derived from the pulse sources P.sub.l through P.sub.n. In the switch condition shown, the capacitors C.sub.2l through C.sub.2n are connected to their respective input circuits and are charged to a value representative of the several input signals. As the switches SW.sub.5l through SW.sub.5n are sequentially actuated, the charge on the capacitors C.sub.2l through C.sub.2n are sequentially transferred as input signals to the operational amplifier A. The output of the amplifier A is commutated, stored, and subsequently scanned as in the system described in connection with FIG. 1.

In FIG. 5 there is shown another circuit which is substantially identical to that shown and described in connection with FIG. 1 with the addition of means for compensating the output signal from the amplifier for offset and drift voltages. A switch SW.sub.5o is arranged to connect the input of the amplifier A to ground, periodically. Simultaneously therewith, a second switch SW.sub.6o is arranged to connect the output of the amplifier to an error memory device represented by the capacitor C.sub.6o. The switches SW.sub.5o and SW.sub.6o are arranged to be closed during the interval between closure of the multiplexing switches. That is, the switches SW.sub.5o and SW.sub.6o are closed at a time when none of the multiplexing or commutating switches is closed. This is accomplished by connecting all of the pulse signals from sources P.sub.l through P.sub.n to the several inputs of a NOR gate G.sub.2o. The output of that gate is illustrated in line H of FIG. 2. Thus, between actuation of the successive multiplex switches, the input to the amplifier A is connected to ground or zero potential. When the input to the amplifier A is thus grounded, any signal appearing at the output thereof will represent inherent offset or drift in the amplifier. The charge thus stored on the capacitor is then superimposed upon the next output signal resulting from the operation of the output scanning switches SW.sub.4l through SW.sub.4n since the capacitor 60 will be successively connected in series with the storage capacitors C.sub.1l through C.sub.1n.

Thus, there has been provided, in accordance with the present invention, an improved isolated multiplexing system which includes means whereby the output signals can be scanned at a relatively high speed independently of the multiplexing rate, and in which the time shared amplifier includes means for compensating for offset and drift signals thereof.