Pulse Generator for Television for Generating at Least One Pulse Series Having Pulses of Different Duration and Repetition Period

In order that the invention may be readily carried into effect, some embodiments thereof will now be described in detail, by way of example, with reference to the accompanying diagrammatic drawings, in which:

FIG. 1 is a block diagram of a television pulse generator according to the invention,

FIG. 2 shows the pulse generator of FIG. 1 in greater detail,

FIGS. 3 and 4 show the relation of time between signals occurring in the pulse generator,

FIG. 5 serves to explain the generation of signals with pulses of field frequency,

FIGS. 6 and 7 serve to explain the generation and the influence of a signal with auxiliary pulses occurring at the line frequency and at the double line frequency,

FIG. 8 shows the pulses occurring in a blanking signal generator of the pulse generator of FIGS. 1 and 2,

FIG. 9 relates, similarly as FIG. 8, to a synchronizing signal generator in the pulse generator,

FIG. 10 shows a detail of a pulse generator according to the invention suitable for generating a PAL chrominance subcarrier gating signal,

FIG. 11 serves to explain the generation of the PAL gating signal occurring at the line frequency,

FIG. 12 shows a few auxiliary pulses,

FIG. 13 serves to explain the generation of a field-shifted PAL blocking signal of nine line periods,

FIG. 14 shows a block diagram of a pulse generator switchable between a plurality of television standards according to the invention, shown in the position for the RTMA standard (R),

FIG. 15 shows the pulse generator according to FIG. 14 in greater detail,

FIG. 16 serves to determine the relationship between a few signals laid down in accordance with the RTMA standard for colour television and generated with the aid of the pulse generator according to FIGS. 14 and 15,

FIGS. 17 and 18 show the time relation between signals occurring in the pulse generator according to FIGS. 14 and 15,

FIG. 19 serves to explain the generation of signals with pulses of field frequency,

FIGS. 20 and 21 serve to explain the generation and the influence of a signal with pulses occurring at the line frequency and at the double line frequency,

FIG. 22 shows the pulses for the RTMA standard occurring in a blanking signal generator of the pulse generator according to FIGS. 14 and 15,

FIG. 23 shows, similarly as FIG. 22, a synchronizing signal generator in the pulse generator,

FIG. 24 shows in greater detail a generator which can be connected to the pulse generator according to FIGS. 14 and 15, and which is suitable for generating an NTSC or PAL chrominance subcarrier gating signal for the RTMA or CCIR standard,

FIG. 25 serves to explain the generation of the NTSC gating signal occurring at the line frequency and of an auxiliary pulse to be used for generating the PAL gating signal,

FIG. 26 shows the time relation between signals in the pulse generator according to FIGS. 14 and 15, used in the position for the CCIR standard (C), and

FIG. 27 serves to explain the generation of signals with pulses of field frequency for the CCIR standard.

In FIG. 1 the reference A denotes a clock pulse generator an input of which is connected to a phase discriminator B for the purpose of synchronisation. A generator is denoted by the general reference G. An output of the clock pulse generator A is connected to a circuit of frequency dividers D, E and F. The frequency divider F which provides a signal f at a frequency of .nu..sub.H which represents the line frequency in a television system is connected to an input of the phase discriminator B to another input of which an external synchronizing signal of the frequency .nu..sub.H (not shown) is applied. For a choice of the clock pulse frequency of 80 .nu..sub.H, which choice has been made in accordance with an aspect of the invention, the signal a provided by the generator A undergoes a division by 5, 8 and 2, respectively, by the frequency dividers D, E and F, respectively.

An output of the divider E conveying a signal at double the line frequency is connected to a circuit of frequency dividers L and M having a dividend of 5 and 125, respectively. For a 625-line system employing interlacing the frequency divider M provides a signal of a frequency .nu..sub.V which represents the field frequency. The dividers L and M are provided with an input to which an external synchronizing signal s.sub.VES may be applied for purposes of synchronisation. In the signals shown in FIG. 1 a line period T.sub.H and a field period T.sub.V are shown in the signals occurring at the line and field frequencies, respectively.

Outputs of the frequency dividers L and M consisting of divider stages are connected to pulse generators denoted by the references, X, Y and Z, which are also mutually coupled. Under the influence of output signals from the dividers L and M, which signals will be further referred to hereinafter, the pulse generators X, Y and Z provide signals x, y and z including pulses occurring at the field frequency and having a pulse duration of 20 T.sub.H, 7.5 T.sub.H and 2,5 T.sub.H, respectively. These pulse periods in the signals x, y and z laid down in the so-called CCIR standard provide approximately the field blanking period, the equalizing and field synchronizing period and exclusively the field synchronizing period, respectively.

The signals y and z and the signal x are applied to a synchronizing signal generator P and to a blanking signal generator W, respectively, other inputs of which are coupled to divider stages of the frequency dividers in the circuit D, E, F. The outputs of the generators P and W convey signals p and w which correspond to a different pulse series including pulses of different duration and repetition period.

In addition to a certain choice of coupling the circuits D, E, F and L, M with the pulse generators X, Y, Z and the signal generators P and W, the pulse generator according to FIG. 1 is provided, in accordance with an aspect of the invention, with a pulse generator I forming part of the said coupling. The pulse generator I provides a signal i shown in FIG. 1, (and the inverse thereof i) which beyond the equalising and field synchronizing period of 7.5 T.sub.H laid down by signal y has auxiliary pulses occurring at the line frequency, which auxiliary pulses occur within this period at double the line frequency.

To explain the importance of the choice of the frequency of 80 .nu..sub.H of the clock pulse generator A and of the choice of coupling comprising the pulse generator I, FIG. 1 will be further described in combination with the detailed embodiment according to FIG. 2, and the signals shown in the following Figures. In FIG. 2 some components of FIG. 1 are not shown, whereas other components, such as for example the divider stages of the frequency dividers of the circuits D, E, F and L, M are shown separately. In FIG. 1 the direction of signal transmission in a general sense is denoted by a single arrow head, whereas, as will be apparent, signal paths giving an important trigger action on the generators X, Y, X, I, P and W are provided with double arrow heads. On the other hand the corresponding signal paths giving a trigger action are shown in FIG. 2 with single arrow heads for the sake of simplicity.

Generator Z shown in FIG. 1 is formed in FIG. 2 as a NAND gate and the frequency dividers D, E, F, L and M, and the generators X, Y, I, P and W are formed with JK flip-flops in FIG. 2. These digital circuit elements are bulk-manufactured and have a great accuracy and a long lifetime as is required for use in computers. In the description of FIG. 2 the flip-flop indication will be used instead of the divider and generator indication. For the chosen type all single-fold inputs and outputs of the flip-flop Y are used, so that this will be described in general in order to explain the operation of a JK flip-flop. As used in an embodiment of the pulse generator of FIG. 2, two JK flip-flops may be constitute one component such as, for example, in the type FCJ 121 one flip-flop of which is denoted by 1/2 FCJ 121. The JK flip-flop Y has a command input denoted by the reference T and an arrow head and two preparatory inputs denoted by the references J and K and determining whether the flip-flop changes over or does not change over. A reset input is denoted by the reference S.sub.2. Two outputs Q.sub.1 and Q.sub.2 convey inverse sig noted by y and y, respectively, for the flip-flop Y. Two combined flip-flops in one FCJ 121 have only the reset input S.sub.2 in common. The inputs J and K may alternatively be formed in a multifold manner through an AND gate such as is shown for the J inputs J.sub.1 and J.sub.2 of the flip-flops I and W and in which there applies that J = J.sub.1. J.sub.2.

Generally the following applies for a JK flip-flop while starting from the so-called positive logic having a high potential corresponding to a logic 1 and a low potential corresponding to a logic O, while an unconnected input conveys a logic 1 through internal couplings.

If a logic 1 is impressed on the S.sub.2 input of the flip-flop Y or if it is not connected (S.sub.2 (Y) = 1), then it does not exert influence. If a variation from a logic 1 to 0 (S.sub.2 (Y) 1 .fwdarw.o) at the S.sub.2 input or if there is a logic 0 (S.sub.2 (Y) = 0), the Q.sub.1 output must pass from the logic 1 to 0 (Q.sub.1 (Y) 1.fwdarw.0) or the Q.sub.1 output remains 0 (Q.sub.1 (Y) = 0). For the inverse Q.sub.2 output it follows that Q.sub.2 (Y) 0.fwdarw.1 or Q.sub.2 (Y) = 1.

The JK flip-flop Y changes over under the influence of the signals at the J and K inputs only when a logic 1 becomes a 0 at the T input (T (Y) = 1.fwdarw.0). For a logic 0 at the T input (T (Y) = 0) the signals at the J and K inputs do not exert influence and may vary arbitarily.

For a logic 1 at the T input (T (Y) = 1) the signal at the J and K inputs constitute the basis for causing the flip-flop to either change over or not when T (Y) 1.fwdarw.0, in which a logic 1 is predominant relative to a 0, that is to say, a logic 1 occurring for a short instant at the J or K input during T (Y) = 1 determines if the flip-flop either changes over or not rather than does a logic 0 which is present for a long period.

Taking the foregoing into account and using the introduced notation, the following applies generally for a JK flip-flop.

In the description of FIG. 9 and Table 5 reference will be made to the flip-flop P having 3 J and K inputs (type FCJ 201) which may alternatively serve as command or trigger inputs when T = 1.

The inputs and outputs which are connected to other outputs and inputs are shown for the JK flip-flops of FIG. 2. For connections which are important for the invention, FIGS. 1 and 2 show the output signals which are partly plotted as a function of time in FIGS. 3 - 9. Since the inverse signals of the Q.sub.2 outputs only differ in polarity from the signals of the Q.sub.1 outputs, only the latter are plotted in FIGS. 3 and 4.

Starting from the clock pulse signal a, FIG. 3 shows the signals d1, d2 and d3 of the 5-to divider D consisting of 3 flip-flops D1, D2 and D3, the signals e1, e2 and e3 of the 8-to-1 divider E consisting of 3 flip-flops E1, E2 and E3 and the signal f of the flip-flop F acting as a 2-to-1 divider. Furthermore FIG. 3 shows a few signals including pulses occurring at the line frequency and at the double line frequency which are in a close relation with the clock pulses in the signal a such as: in the signal i the auxiliary pulses occurring at the line frequency and during the 7.5 T.sub.H period at the double line frequency; a line synchronizing pulse shown in signal s.sub.HP, two equalizing pulses occurring at the double line frequency shown in signal s.sub.EP ; two raster serrations occurring in signal s.sub.VS at the double line frequency and a line blanking pulse occurring in signal s.sub.HW.

FIG. 2 shows by way of the instant t.sub.o a commencing instant of one line period and t.sub.80 shows the end which corresponds to the instant t.sub.0 of a subsequent line period. 80 Clock pulses occur in the signal a between t.sub.0 and t.sub.80 so that the difference between two successive instants (t.sub.0, t.sub.1, t.sub.2... t.sub.80) corresponds to one clock pulse period. FIG. 2 shows that the clock pulses of signal a are applied to the T input of the flip-flops D1 and D2, that is to say, to both inputs T(D1) and T(D2). B.sub.V Negatively directed edges in the signal a and other signals which are active as trigger edges and cause a flip-flop to change over the partially provided with arrow heads. To explain the operation of the 5-to-1 divider D including the 3 flip-flops D1, D2 and D3 and to give the mutual connections a Table 2 follows in which the variations shown in the signals d.sub.1, d.sub.2 and d.sub.3 of FIG. 3 are derived with the aid of Table 1.

In Table 2 delays occurring in the flip-flop D1, D2 and D3 are not taken into account. For the purpose of further explanation of Table 2 the following applies: The reference t.sub.0 - .DELTA. t denotes an instant which lies just before the instant t.sub.0. At the instant t.sub.0 - .DELTA. t the signal a has the value 1. It is desirable for the 5-to-1 divider D that at the instant t.sub.0 when there applies that T (D1) = T(D2) 1.fwdarw.0, the flip-flop D1 and D2 change over so that t.sub.0 - .DELTA. t J(D1) = 1 and K(D2) = 1. It follows therefrom that at t.sub.0 - .DELTA.t Q.sub.2 (D1) = K(D2) = 1 and Q.sub.1 (D3) = J(D1) = 1. To ensure that D3 certainly does not change over at the instant t.sub.0, T (D3) = 0 = Q.sub.1 (D2) at t.sub.0 - .DELTA. t. The rows and columns shown in Table 2 can subsequently be derived in a simple manner by considering for a certain instant the value of J (D1) = d.sub.3 of a previous instant.

Table 2 shows that the rows at the instants t.sub.0, t.sub.5, t.sub.10 .....; t.sub.1, t.sub.6 ......etc. are the same. In FIG. 3 it can be seen from signal d.sub.3 that the divider D thus dividing by five is active as an asymmetrical divider, while the edges are indicated over one arbitary period at the instants, t.sub.2, t.sub.4 to t.sub.7.

In Table 2 it has been stipulated that delays in the JK flip-flops D1, D2 and D3 have not been taken into account. It is found from data in the Handbooks that a JK flip-flop FCJ 121 has an average propagation delay time t.sub.pd of 105 ns at a maximum between a T input and a Q output. Measurements yielded at t.sub.pd of 70 ns at an average. For the sake of simplicity FIG. 3 mentions the propagation delay time t.sub.pd as t.sub.Q. As a reference value, relative to which the successive propagation delay times of the JK flip-flops will be considered, the edges in the signals d.sub.1 and d.sub.2 are taken which coincide with the instants t.sub.0, t.sub.1, t.sub.2, t.sub.3, etc. As a result the trigger edges, which are sometimes denoted by arrow heads, occur in the signal a in FIG. 3 at a time t.sub.Q before the instants t.sub.0, t.sub.1, t.sub.2, etc. As is indicated at the instant t.sub.9 in signal d.sub.3, the pulse edges in this signal have a delay time t.sub.Q.

After the detailed description of the frequency divider D including the flip-flops D1, D2 and D3 only the following connections are given for the following asymmetrical or symmetrical frequency dividers E, F. L and M:

T (e1) = q.sub.2 (d.sub.1) j (e1) = k (e1) = q.sub.2 (d3)

t (e2) = q.sub.1 (e1) t (e3) = q.sub.1 (e2)

t(f) = q2(e3)

t(l1) = t (l2) = q.sub.1 (e3) k (l1) = q2 (l2) d1 Q.

J(l2) = q1 (l3) k (l2) = q.sub.1 (l1)

t(l3) = q.sub.2 (l1) t (m1) = q.sub.2 (l2)

t(m2) = q.sub.2 (m1) t (m3) = q.sub.2 (m2)

t(m4) = q.sub.1 (m3)....t(m7) = q.sub.1 (m6)

s.sub.2 (m1) = s.sub.2 (m2) = q.sub.2 (m7) via differentiation.

Some important points are the following: As there applies for the JK flip-flop E1 that T(E1) = D1 the signal e1 only has a delay time of 1t.sub.Q while the subsequent successively connected flip-flops E2, E3 and F have a delay time of 2t.sub.Q, 3t.sub.Q and 4t.sub.Q.

FIG. 4 shows the result of the connection of the divider E3 with a trigger signal e3 to the 5-to-1 divider L (FIG. 1) consisting of 3 JK flip-flops L1, L2 and L3. The signals m1 to m7 inclusive are also shown, which signals are associated with 7 JK flip-flops M7 to M7 inclusive which constitute the 125-to-1 divider M.

The propagation delay times then range from 3t.sub.Q to 11t.sub.Q inclusive. The propagation delay time corresponds to a sequential number of the JK flip-flop calculated on the flip-flops D1 and D2 which determine the time scale t.sub.0 ..... t.sub.80 and are therefore also calculated on the clock pulse generator A.

In the signal e3 of FIG. 4 a line period T.sub.H has been shown from an instant t.sub.0 occurring periodically at the line frequency (the delay time 3t.sub.Q is left out of consideration). For obtaining in a similar manner a time scale of field frequency an instant t.sub.100 is shown at the signal m1 which gives the periodical instant of commencement of a field time scale calculated on the signal m1. The edges occurring in the signal e3 determine approximately the successive instants t.sub.101, t.sub.102...... t.sub.110... t.sub.120......t.sub.130, t.sub.131.......t.sub.1350 = t.sub.100 which apply to two different time scales for the signals e3, 11, 12, 13and ml..... m7.

Since the divider M consisting of 7 divider stages of FIG. 2 would divide further steps by 2.sup.7 = 128 instead of to 125, the output Q.sub.2 (M7) with the signal m7 is coupled for an internal resetting at the instant t.sub.740 to the reset inputs S.sub.2 (M1) and S.sub.2 (M2). This coupling is effected through a differentiating circuit which includes a capacitor C.sub.1 and two resistors R.sub.1 and R.sub.2 arranged in series between ground and a potential U. The junction of the resistors R.sub.1 and R.sub.2 is coupled through a diode T.sub.1 blocking the internal reset pulse to the reset inputs of the flip-flops L1, L2, L3, M3 ..... M7, the purpose (synchronizing purposes) being further referred to hereinafter. Either the complete potential U or a portion thereof corresponds to the already mentioned logic 1 while the ground potential corresponds to the logic 0.

As in FIG. 1, FIG. 4 shows the signals x, y and z, but in relation to the signals e3, l1....l3, m1...m7. The external synchronizing signal s.sub.VES is also shown.

Starting from the values already given for the pulse duration in the signals x, y and z for a certain television standard, namely the CCIR standard, these values may be produced with the connections shown in FIG. 2 by means of two JK flip-flops X and Y and one NAND gate Z, while FIG. 5 shows the signal variation.

FIG. 2 shows that the T input of flip-flop X is connected to the Q.sub.1 output of flip-flop M.sub.2 and that the J input is connected to the Q.sub.1 output of M4.

The K input of flip-flop X is connected to a differentiating circuit including a resistor R.sub.3 to ground and a capacitor C.sub.2 to the Q2 output of flip-flop M7. The signals shown in FIG. 5 occur at the inputs of flip-flop X, in which T = m2, J = m4 and K = m7'. The index notation relates to a differentiated signal.

In FIG. 5 the propagation delay times (a number of times t.sub.Q) shown in FIG. 4 are included in the graphic representation. As compared with the time scale with the instant t.sub.100 calculated on the signal m1, the edges of signals m2, m4 and m7 have a delay time of 1t.sub.Q, 3t.sub.Q and 6t.sub.Q. At the instant t.sub.100 + 6t.sub.Q the signal m7' has the logic 1 for a short moment, which value as given with reference to the general description and Table 1 of the JK flip-flop Y is predominant relative to the logic 0. The flip-flop X therefore assumes the state at which J(X) = 0, K(X) = 1, so that it follows with the aid of Table 1 that the Q.sub.1 output of X must convey the logic 0 after the instant t.sub.120 + t.sub.Q at which T(X) 1.fwdarw.0. At the instant t.sub.120 + 2t.sub.Q, the flip-flop X changes over and the logic 1 information on the K input is lost due to internal couplings. A subsequent trigger edge in the signal m2 occurs shortly after the instant t.sub.160. Then, however, J (X) = K (X) = 0 and the flip-flop X remains in the same state. For the trigger edge shortly after the instant t.sub.200 the J input of flip-flop X has gone from the logic 0 to 1. At the instant t.sub.200 + 1t.sub.Q there applies that J(K) = 1 and K(X) = 0 so that the Q.sub.1 output must convey the logic 1. For the remaining period of a field period T.sub.V there continues to apply that K(X) = 0 while J (X) may be either 0 or 1. It follows from Table 1 that when Q.sub.1 (X) = 1, the flip-flop X no longer changes over. The negatively directed edge in the singal m7 (not shown) occurring at the instant t.sub.740 (see FIG. 4) has no influence on the flip-flop X; the logic 0 remains present.

According to FIG. 2 the connections for the flip-flop Y are as follows:

T(Y) = Q.sub.2 (L.sub.2), J(Y) = Q.sub.1 (M.sub.2) and K(Y) to ground while the S.sub.2 input is connected to the Q.sub.1 output of the flipflop X through a differentiating circuit which comprises two resistors R.sub.4 and R.sub.5 arranged in series between ground and the potential U, and a capacitor C.sub.3.

The signals shown in FIG. 5 occur at the inputs of the flip-flop Y at which T = 12, J = m2, K = 0 and S2 = x' (signal x differentiated). Likewise as in the signals associated with the flip-flop X, a few propagation delay times are mentioned.

It follows with the aid of Table 1 for the flip-flop Y that for K = 0 and J = 0 or 1, the stable state of the flip-flop corresponds to a logic 1 on the Q.sub.1 output. At the instant t.sub.120 + 2 t.sub.Q an edge 1.fwdarw.0 appears in the signal x' at the S.sub.2 input so that in accordance with the description with reference to Table 1 the Q.sub.1 output must assume the logic 0. At the instants t.sub.130 and t.sub.140 negatively directed edges occur at the T input neither of which edges influence the state of the flip-flop Y. Particularly at the instant t.sub.140 - 1t.sub.Q there is shown that for J = K = 0 the flip-flop does not change over. At the instant t.sub.150 - 1t.sub.Q, however, J = 1, K = 0 so that at the instant t.sub.150 the Q.sub.1 output conveys the logic 1. The flip-flop Y remains in this state until an edge 1.fwdarw.0 active as a trigger edge occurs in the signal x' during a subsequent field period T.sub.v.

FIG. 2 shows the NAND gate Z whose inputs are connected in a manner not shown to Q.sub.2 (M1) and Q.sub.2 (Y). The output of the gate Z thus conveys a signal z = y.m1 = y + m1 which is shown in FIG. 5. Before further describing the generation of the signal i (FIG. 3) including auxiliary pulses occurring at the line frequency and at the double line frequency, the requirements which are imposed on the signals generated by a pulse generator which is suitable for the CCIR standard according to the embodiment shown in FIGS. 1 and 2 will first be dealt with so as to explain certain choices made in accordance with the invention. Already shown are a field synchronizing period of 2.5 T.sub.H (signal z) an equalizing and field synchronizing period of 7.5 T.sub.H (signal y) and a field blanking period of approximately 20 T.sub.H (signal x). In this case it is prescribed that 5 equalizing pulses of the double line frequency must precede and follow 5 field synchronizing pulses of the double line frequency. The duration of the field blanking period in the composite blanking signal must then be 20 T.sub.H .+-. 2 T.sub.H + 1 line blanking pulse duration. Furthermore, the requirements mentioned in the following Table 3 apply, which requirements are derived from the signals shown in FIG. 3. TABLE 3. (FIG. 3).

Such a number of requirements may be met in a simple manner by the embodiment of a pulse generator according to the invention shown in FIGS. 1 and 2. Here the recognition becomes manifest to determine the Highest Common Factor (H.C.F.) of the different pulse periods and time differences between the pulse leading edges and to relate the H.C.F. to the smallest pulse repetition period. As a result a few correctly chosen edges of the pulses in the frequency divider stages connected to the clock pulse generator A can determine in a direct manner the pulse edges accurately laid down in the standard in the signals to be generated.

A H.C.F. of the numbers 1.55; 2.3; 4.7 and 12.05 or an approximation thereof is to be found which H.C.F. must be divisible by the smallest pulse repetition period, which is half a line period 1/2T.sub.H = 32 .mu.s. The reason thereof is that the smallest pulse repetition period imposes the most stringent requirements on a smooth periodicity in the generation of signals. Starting from the number 32 the H.C.F. must be an integral multiple of the number 2. It follows that the number 0.8 reasonably satisfies as a H.C.F. while finding for the relevant numbers: 1.6; 2.4; 4.8 and 12.0. A period of 0.8 .mu.s and a frequency of 1.25 MHz corresponds thereto for the clock pulse generator A. Other possible values could be 0.4; 0.2; 0.1 .... .mu.s with a frequency of 2.5; 5; 10 .... MHz.

Both in Table 3 and in practice stringent requirements are imposed on the accuracy of the line synchronizing pulse duration in the signal s.sub.HP and particularly the equalizing pulse duration in the signal s.sub.EP. By using the propagation delay time t.sub.pd (= t.sub.Q in the Figures) occurring in the JK flip-flops of FIG. 2 and being 70 ns at an average, this time may be deducted from the pulse duration in the generated signals. Table 4 shows the pulse periods prescribed by the CCIR standard and reached in practice in a pulse generator according to the invention. TABLE 4

To determine a few pulse edges the signal i is generated which includes auxiliary pulses of line frequency and double line frequency. FIG. 2 shows the JK flip-flop 1 for which the associated signals are shown in FIG. 6.

In FIG. 2 the T input of the flip-flop I is connected to Q.sub.2 (D.sub.2) and the K input is connected to Q.sub.1 (E2). A J.sub.1 input of the J input formed in a twofold manner through an AND gate is connected to the output of a NAND gate N.sub.1 whose inputs are connected to Q.sub.1 (F) and Q.sub.1 (Y) A J.sub.2 input of flip-flop I is coupled through a differentiating circuit including a resistor R.sub.6 to ground and a capacitor C.sub.4 to Q.sub.2 (E3).

In FIG. 6 the signals T = d2, J.sub.1 = f+y are shown for the flip-flop I, for J.sub.1 = f.y = f + y, J.sub.2 = e3' and K = e2. In the first instance it is assumed that y = 1, that is to say, the operation of flip-flop I will be considered outside the equalizing and field synchronizing period of 7.5 T.sub.H. The J.sub.1 input then conveys the signal f (solid lines). The time scale t.sub.0.....t.sub.80 is derived from the signal d2. The edges in the signals f, e3' and e2 have delay times 4t.sub.Q, 3t.sub.Q and 2t.sub.Q. Further reference is made to Table 1 for the explanation of the operation of the JK flip-flop I.

At the instant t.sub.0 of FIG. 6 the J input has a logic 0 because J.sub.2 = 0. For K = 1 there applies for the stable state that Q.sub.1 = i = 0. At the instant t.sub.3 a negatively directed edge occurs on the T input. Meanwhile the J.sub.2 input as received a logic 1 so that for J.sub.1 = J.sub.2 = 1 = J and K = 0 there applies that Q.sub.1 must assume a logic 1. At the instant t.sub.3 + 1 t.sub.Q, Q.sub.1 has become = 1. The negatively directed edges in the signal T = d2 at the instants t.sub.5, t.sub.8 and t.sub.10 do not result in variations of the flip-flop I because for K = e2 = 0 there applies that Q.sub.1 = i = 1 is a stable state even when J.sub.1 and J.sub.2 vary between 0 and 1. At the instant t.sub.13, however, a trigger edge occurs when K has already previously become e.sub.2 = 1. It follows that the flip-flop I must change over which happens at the instant t.sub.13 + 1t.sub.Q and at which Q.sub.1 has become i = 0.

Due to the choice of K = e2 with a guaranteed delay time of 2t.sub.Q relative to the edges in signal T = d2, it has been achieved that at the instant t.sub.10 the flip-flop I certainly cannot change over, while it changes over as soon as possible after the instant t.sub.13.

Certain requirements are to be imposed on the signal e3' for the J.sub.2 input. Due to the choice of e3 it has been achieved by the delay time 3 t.sub.Q after the instant t.sub.0 that the flip-flop I at the instant t.sub.0 is certainly not changed over. The differentiated pulse in signal e3', which pulse is shown in a flattened manner and which may extend without any consequence to well above the value indicated by the logic 1, must not stop before the instant t.sub.2, for the predominant logic 1 is to occur between the instants t.sub.2 and t.sub.3 when T = d2 = 1. Before the instant t.sub.15 the pulse in signal e3' must have disappeared so as to avoid the predominant influence after the instant t.sub.15. The pulse in the signal e3' may thus vary between the broken lines in FIG. 6.

At the instant t.sub.20 a negatively directed pulse in the signal J.sub.2 = e3 occurs, which signal continues to represent the logic 0 and which does not exert influence on the action of a flip-flop I.

Shortly after the instant t.sub.40 a following pulse occurs in the signal J.sub.2 = e3'. However, the signal f at the J.sub.1 input has the logic 0 so that for J = 0 and K = O or 1 there applies that Q.sub.1 = i = 0 is the stable state.

The action of the flip-flop I in FIG. 2 during the equalizing and field synchronizing period of 7.5 T.sub.H may be explained by way of a combined consideration of FIGS. 6 and 7.

In FIG. 7a the signal y is shown in relation to the field time scale t.sub.100 ..... t.sub.1350 given in FIG. 4. FIGS. 7b and 7c apply for two successive fields, while FIG. 7b applies for a field ending at a half line and FIG. 7c for a field ending at a full line. The signal f and for the flip-flop I the signals J.sub.1 = f + y, J.sub.2 = e3' and Q.sub.1 = i are shown. The negatively directed pulses without any influence in the signal J.sub.2 = e3' of FIG. 6 have been omitted in FIGS. 7b and 7c for the sale of simplicity.

For FIG. 7b there applies that the instant t.sub.120 corresponds to the instant t.sub.40 + 5t.sub.Q in FIG. 6. In FIG. 6 it has already been explained what happens before the instant t.sub.120 in FIG. 6b. At the instant t.sub.120 + 3t.sub.Q in FIG. 7b, which is the instant t.sub.40 + 8 t.sub.Q in FIG. 6, the edge occurs which is shown in a broken line in FIG. 6. In the same manner as described in FIG. 6 for the pulse in signal Q.sub.1 = i occurring between the instants t.sub.3 + 1t.sub.Q and t.sub.13 + 1t.sub.Q, a pulse shown in a broken line is generated in the signal Q.sub.1 = i between the instants t.sub.43 + 1t.sub.Q and t.sub.53 + 1t.sub.Q. It is found that during the 7.5 T.sub.H period the pulses in the signal i are generated atvthe double line frequency. All this has also been shown for the signal i in FIG. 3.

After the description of FIG. 7b, FIG. 7c is self-evident.

The influence of the auxiliary pulses in the signal i is found in a simple manner with reference to the description of the action of the JK flip-flop W in FIG. 2. the signals for the flip-flop W which as a signal generator must provide the signal with a series of line and field blanking pulses are shown in FIG. 8. FIG. 8a shows the signals which are the same for each field and FIGS. 8b and 8c show in accordance with FIGS. 7b and 7c the signals which are different for successive fields.

In FIG. 2 the connections of the inputs of the flip-flop W are as follows:

T (W) = Q.sub.1 (D3), J.sub.1 (W) Q.sub.1 (E3) J.sub.2 (W) = Q.sub.1 (X) and K(W) = Q.sub.1 (I).

In FIG. 8a the signal T = d3 is partially indicated on two scales which are both derived from the time scale t.sub.O ...... t.sub.80 and which relative thereto have a delay time of 1t.sub.Q which is left out of consideration in FIG. 8. For the two-fold J input having an AND gate function the signal J follows from the signals J.sub.1 = e3 with delay time 3t.sub.Q and J.sub.2 = x with delay time 7t.sub.Q.

In FIG. 8b the signal K = i is shown for one field in relation to FIG. 8a. The period denoted by 7.5 T.sub.H (y = 0) is considered to end during the period of the time axis being shown interrupted. At the instant t.sub.2 a negatively directed edge occurs in the signal T = d3. In that case J = K = 0 so that in accordance with Table 1 the flip-flop W does not change over. If prior to the instant t.sub.2 it were allowed that J varies between 0 and 1, while as a result thereof the flip-flop W should not change over even once, then it follows from Table 1 that at this stable state the Q.sub.1 output must have the logic 1. This is the starting point.

At the instant t.sub.7 a subsequent negatively directed edge occurs in the signal T = d.sub.3. Meanwhile the signal K = i has received the logic 1 at the instant t.sub.3 so that for J = 0, K = 1, the flip-flop W changes over the Q.sub.1 = w changes from the logic 1 to the logic 0. A negatively directed edge in the signal T = d3 at the instant t.sub.12 does not exert influence on the flip-flop W. At the instant t.sub.13 the signal K = i changes back from the logic 1 to the logic 0. A negatively directed edge occurring at the instant t.sub.17 in the signal T = d.sub.3 has for J = 0 and K = 0 no influence on the flip-flop W. At the instant t.sub.20 the signal J.sub.1 = e3 receives the logic 1 and hence the signal J. At the negatively directed edge occurring at the instant t.sub.22 in the signal T = d.sub.3 there applies that J = 1, K = 0 whereafter the Q.sub.1 output must start to convey the logic 1. In that case J may change between 0 and 1 for K = 0 without the negatively directed edges in the signal T = d.sub.3 causing the flip-flop W to change over. This state was taken as a starting point.

In FIG. 8b the reference s.sub.HW indicates a second pulse following the described pulse in the signal Q.sub.1 = w which second pulse is also generated in the manner described.

The generation of the pulse in the signal Q.sub.1 = w and denoted by the reference s.sub.HW follows in the same manner for the signal K = i shown in FIG. 8c. To emphasize the fact that FIG. 8c is shifted relative to 8b over half a line period T.sub.H/2, a few instants t.sub.40,..... t.sub.80 = t.sub.0,....... t.sub.7,.....t.sub.22 have been indicated.

The auxiliary pulses in the signal i occurring at the line frequency determine in one field or in the other field approximately the position of the line blanking pulses s.sub.HW to be generated in the signal w according to FIGS. 8b and 8c. The exact position of the edges of the line blanking pulses s.sub.HW in the signal w are determined by the trigger edges in the signal d.sub.3. In FIG. 3 the instants t.sub.7 + 2t.sub.Q and t.sub.22 + 2t.sub.Q are shown for the signal s.sub.HW for the edges. The line blanking pulses in the signal s.sub.HW are found to have a pulse duration of 15 .times. 0.8 .mu.s = .mu.s and fall within the limits imposed by the CCIR standard. (Tables 3 and 4)

In FIG. 8a an instant t.sub.40 is indicated in the signal J.sub.1 = e3 with the signal having the logic 0 at the instant t.sub.40 + 3t.sub.Q which value becomes manifest in the signal J. At the instant t.sub.40 + 7t.sub.Q the logic 0 occurs in the signal J.sub.2 = x from which instant the period 20T.sub.H begins. What has been described with reference to the instants t.sub.2 and t.sub.7 now applies for the instants t.sub.42 and t.sub.47 because in the signal K = i of FIG. 8b the first auxiliary pulses occurring at the double line frequency begins at the instant t.sub.43. The previous auxiliary pulse in the signal K = i is then considered to be the last pulse normally occurring at the line frequency.

With respect to FIG. 8c there applies that the first auxiliary pulse in the signal K = i after the instant when J.sub.2 = x receives the logic 0 appears as the last pulse occurring normally at the line frequency.

After the logic 0 has been obtained in the signal Q.sub.1 = w the signal J of FIG. 8a is found to maintain the logic 0 during a period of approximately 20 T.sub.H while K changes between 0 and 1. It is found from Table 1 that the signal Q.sub.1 = w of FIGS. 8b and 8c maintains the logic 0 because this represents the stable state.

The flip-flop W changes over at the first negatively directed edge in the signal T = d3 after the signal J receives the logic 1 under the influence of the signal J.sub.1 = e3. The subsequent occurrence of an auxiliary pulse in signal K = i of FIGS. 8b or 8c provides the opportunity for some negatively directed edges in the signal T = d3 of FIG. 8c to cause the line blanking pulses s.sub.HW to be generated by the flip-flop W. The flip-flop W generates a field blanking pulse at a duration of 20 T.sub.H plus one line blanking pulse duration (t.sub.22 - t.sub.7 and t.sub.62 - t.sub.47).

The JK flip-flop P of FIG. 2 generates a signal Q.sub.1 = p shown in FIG. 9, which includes a series of line synchronizing pulses s.sub.HP, equalizing pulses s.sub.EP and field synchronizing pulses s.sub.VP. The number of field synchronizing pulses s.sub.VP is constituted by a single long field pulse which is cut into pieces by means of the said raster serrations s.sub.VS.

The flip-flop P deviates from the type (FCJ 121) described so far and is a JK flip-flop of the type FCJ 201 which is formed with three J and K inputs having and AND gate function on which a trigger action may be performed.

The connections of the flip-flop P (in FIG. 2) are as follows: T (P) = Q.sub.2 (D1), J1(P) = Q.sub.1 (E1), J.sub.2 (P) = Q.sub.2 (D3), J.sub.3 (P) = Q.sub.1 (I) and K.sub.1 (P) = Q.sub.1 (E2). The input K.sub.2 (P) is connected to the output of a NAND gate N2 with Q.sub.1 (I) and Q.sub.1 (Y) being connected to inputs thereof. The input K.sub.3 (P) is connected to the output of the NAND gate Z. The input S.sub.2 (P) is coupled to Q.sub.2 (I) through a differentiating circuit including a capacitor C.sub.5 and two resistors R.sub.7 and R.sub.8 arranged in series between the potential U and ground.

In addition to the Table 1 for the trigger action on the input T(P) and the description given with reference thereto a Table 5 also applies for the JK flip-flop P of the type FCJ 201 in which Table for T(P) = 1 a trigger action on the J and/or K-input may be performed in case of a transition from the logic 1 to the logic 0.

The influence of the input signals according to FIG. 9 may be explained with the aid of Tables 1 and 5.

FIG. 9 relates to 19 half line periods T.sub.H /2 occurring in and near the equalizing and field synchronizing period. The periods of time 1, 2, 3, 4; 7, 8, 9; 12, 13 and 17, 18, 19 are shown for the numbered half line periods. Only the first 16 .times. 0.8 .mu.s = 12.8 .mu.s are shown for each half line period T.sub.H /2 of 32 .mu.s. The time axis in the signal J.sub.1 = e1 is interrupted after the instant t.sub.16 so as to show that the signal has the same periodical character after this instant. The time axis in the signal J.sub.3 = i is shown in a broken line after the instant t.sub.16 so as to show that the signal can occur once at a maximum during one of the periods of time 1......19, considering the fact that the signal i has pulses of line frequency and double line frequency. The signal J.sub.2 = d3 is shown near the signal J so as to emphasize that the signals J.sub.1 = e1 and J.sub.3 = i exert an inaccurate place-determining influence while an edge in the signal J.sub.2 = d3 has an accuracy-determining influence. Due to the periodicity of the two television fields the time scale t.sub.0,.....t.sub.40,,,,t.sub.80 = t.sub.0 given with signal J may alternatively be considered as t.sub.40.....t.sub.80 = t.sub.0.....t.sub.40.

The signal K.sub.3 = z is shown in an uninterrupted manner so as to clarify that it includes a pulse of field frequency which has the logic 0 during the periods of time 8.....12 (2.5 T.sub.H). In the signal K.sub.2 = i . y = i + y the same applies for the periods of time 3.....17 (7.5 T.sub.H) in which the signal y has the logic 1. The total signal K is constituted through an AND function together with the signal K.sub.1 = e2.

Analogously to the signal J.sub.3 = i, signal S.sub.2 = i' (signal i differentiated is shown. The signal T = d1 and the signal S.sub.2 = i' may be found to have an accuracy-determining influence while the signal K only has a choice influence.

During the periods of time 1, 2 and 18, 19 the signals J.sub.3 = i and J, K.sub.2 = i + y and K, and the signal S.sub.2 = i' are shown with portions consisting of broken lines and chain-link lines as well as the portions in the signal Q.sub.1 = p resulting therefrom due to the action of the flip-flop P. The reason thereof resides in the periodicity of the two television fields. The chain-link line portion in the periods of time 1, 2 and 18, 19 is associated with the field which ends with a full line prior to the equalizing and field synchronizing period, as has been described with reference to FIGS. 7c and 8c. The broken line portion corresponds to the state described with reference to FIGS. 7b and 8b.

The consideration of the period of time 1 with the chain-link line portion in the signals of FIG. 9 leads to the following: around the instant t.sub.0, J = 0 and K may have the logic 1 or 0. It follows from Table 1 that for the stable state of flip-flop P the requirement is that Q.sub.1 has the logic 0. It follows from Table 5 that with a variation of K from 1 to 0 for T = 1, the stable state also occurs for Q.sub.1 = 0. It is found that without a variation in J the flip-flop P cannot change over.

At the instant t.sub.3 the logic 1 occurs in the signal J.sub.3 = i, whereafter the signal J.sub.1 = e1 follows at the instant t.sub.5. The result is that a logic 1 in the signal J.sub.2 = d3 becomes manifest between the instants t.sub.7 and t.sub.9 in the signal J. At the instant t.sub.9 an edge going from the logic 1 to 0 occurs in the signal J while at the same time the signal T = d1 has the value 1. It follows from Table 5 that the flip-flop P will change over because the signal Q.sub.1 = p must assume the logic 1.

The reset pulse at the instant t.sub.3 occurring in signals S.sub.2 = i' does not exert any influence because the signal Q.sub.1 = p has the logic 0 at t.sub.3.

After the instant t.sub.9 the signal K may exert influence on the flip-flop P. At the instant t.sub.13 the signal K assumes the logic 1 under the influence of the then occurring logic 1 in the signal K.sub.2 = i + y.

After the instant t.sub.9 two negatively directed edges occur in the signal T = d1, the instant t.sub.12 being denoted at the second edge. At the instant t.sub.12 there applies that J = K = 0 so that it follows from Table 1 that the flip-flop P does not change over. The subsequent negatively directed edge in the signal T = d1 occurs at the instant t.sub.15. Now, however, J = 0 and K = 1 so that according to Table 1 the output Q.sub.1 (P) must convey the logic 0 so that the flip-flop P changes over at the instant t.sub.15.

During the rest of the period of time 1 and the entire period of time 2, J remains 0 which follows from the chain-link line portion in the signal J.sub.3 = i. As a result the flip-flop P remains in the same state as has been shown at the instant t.sub.0.

Comparison of FIGS. 3 and 9 shows that the periods of time 1 and 2 in FIG. 9 correspond to the 2 half line periods T.sub.H /2 of FIG. 3. The signal s.sub.HP in FIG. 3 corresponds to the pulse s.sub.HP in FIG. 9. It is found from FIG. 9 that a trigger edge in the signal J.sub.2 = d3 (having a delay time of 1t.sub.Q relative to the time scale t.sub.0......t.sub.80) determines the leading edge of the pulse s.sub.HP while the trailing edge is determined by the trigger edge in the signal T = d1 (without delay time relative to the time scale t.sub.0.....t.sub.80). The result is shown in FIG. 3 in which the leading edge in the signal s.sub.HP is located at the instant t.sub.9 + 2 t.sub.Q while the trailing edge is located at the instant t.sub.15 + 1t.sub.Q. The line synchronizing pulse s.sub.HP therefore has an accurately determined pulse duration of 6 .times. 0.8 .mu.s minus approximately 70 ns, that is to say, 4.73 .mu.s.

What has been described for the period of time 1 in FIG. 9 likewise applies to the period of time 2 for the signals which are shown by means of broken lines so that a detailed description is omitted.

It is to be noted that the signal J.sub.3 = i has a keying function for generating or not generating line synchronzing pulse s.sub.HP during half a line period. The presence of the signal i in the signal K.sub.2 = i +y becomes manifest in the signal K by giving an edge at the instant t.sub.13 instead of an edge at t.sub.10 under the influence of K.sub.2 = e2. The edge in the signal K occurring at the instant t.sub.10 does not exert any influence on the generation of the pulses s.sub.HP occurring at the line frequency.

During the periods of time 3....17 of FIG. 9 constituting the equalizing and field synchronizing period (7.5 T.sub.H) the auxiliary pulses occur each period of time in the signal J.sub.3 = i and then provide in signal J the pulse keyed from the signal J.sub.2 = d3. The signal K is determined in the periods of time 3.....7 and 13.....17 by the signal K.sub.1 = e2 because only the component y = 1 becomes manifest in the signal K.sub.2 = i + y. During the periods of time 8........12 (the field synchronizing period of 2.5 T.sub.H) the signal K.sub.3 = z = 0 is predominant in the signal K.

Analogously as described with reference to the period of time 1, the flip-flop P changes over during the period of time 3 at the instant t.sub.9. Subsequently, at the instant t.sub.10, a negatively directed edge occurs in the signal T = d1. At the instant t.sub.10 the signal K still has the logic 0 whereafter it obtains the logic 1 at the instant t.sub.10 + 2t.sub.Q due to the signal K.sub.1 = e2. The subsequent negatively directed edge in the signal T = d1 at the instant t.sub.12 causes the flip-flop P to change over. The same is effected during the periods of time 4.....7 and 13.....17. The result is that the equalizing pulses s.sub.EP is generated in the signal Q.sub.1 = p. The edges of the equalizing pulse s.sub.EP are determined in the same manner as those in the line synchronizing pulse s.sub.HP. In FIG. 3 two equalizing pulses occurring at double the line frequency are shown in signal s.sub.EP. The pulse duration of the first pulse ranges from t.sub.9 + 2t.sub.Q to t.sub.12 + 1t.sub.Q, that is to say, 3 .times. 0.8 .mu.s minus approximately 70 ns makes 2.33 .mu.s which value also applies to the other pulse.

During the period of time 8 of FIG. 9 the flip-flop P changes over at the instant t.sub.9 analogously as described with reference to the period of time 1. The signal K.sub.3 = z results in the signal K having the logic 0 during theperiods of time 8......12. It follows from the foregoing that consequently the signal K during these periods of time does not exert influence on the state of the flip-flop P. From the instant t.sub.9 the signal Q.sub.1 = p continues to convey the logic 1 throughout the period of time 8 and even up to the period of time 9.

During the period of time 9 a reset pulse going from the logic 1 to 0 occurs at the instant t.sub.3 in the signal S.sub.2 = i'. It follows from Table 1 that this reset pulse gives the output Q.sub.1 (P) the logic 0. Subsequently the signal J results in a change-over of the flip-flop P at the instant t.sub.9. The same is repeated in the periods of time 10, 11 and 12. A pulse generated in this manner in the signal Q.sub.1 = p is denoted by s.sub.VS. The pulse s.sub.VS occurring at the double line frequency and being denoted at a raster serration has its leading edge at the instant t.sub.3 determined by the signal i and its trailing edge at the instant t.sub.9 is determined by the signal d3. In FIG. 3 the instants t.sub.3 + 2t.sub.Q and t.sub.9 + 2 t.sub.Q are denoted in the signal s.sub.VS and the pulse duration is 6 .times. 0.8 .mu.s = 4.8 .mu.s.

During the period of time 13 of FIG. 9 the flip-flop P is reset to the input S.sub.2 (P) of FIG. 2 at the instant t.sub.3 whereafter the equalizing pulses are generated during the periods of time 13.....17 as described with reference to the periods of time 3....7.

It is to be noted that during the period of time 13 an edge 1.fwdarw.0 occurs at the instant t.sub.0 + 2t.sub.Q in the signal K.sub.1 = e2. Subsequently, an edge 0.fwdarw.1 occurs at the instant t.sub.0 + 5t.sub.Q in the signal K.sub.3 = z. The result is that the signal K certainly maintains the logic 0 until the instant t.sub.10 + 2t.sub.Q. This result has been achieved by the choice that the K.sub.1 and K.sub.3 inputs of the flip-flop P are connected to the flip-flop E2 and through the NAND gate Z to the flip-flop M1 each hacing a different added propagation delay time (2t.sub.Q relative to 5t.sub.Q). This added propagation delay time depends on the sequential number of the JK flip-flop calculated relative to the clock pulse generator A or, considering the introduced time scale of line frequency, relative to the flip-flops D1 and D2. Such a choice ensuring satisfactory operation has also been made for other connections in the pulse generator according to FIG. 2 such as has been described with reference to FIG. 6 at the instant t.sub.10 for the flip-flop J with K (J) = Q.sub.1 (E2) (delay time 2t.sub.Q) and T(J) = Q.sub.2 (D2) (no delay time).

The description of the periods of time 18 and 19 corresponds to that of the periods of time 2 and 1, respectively, so that this description is omitted.

In the pulse series generated by the flip-flops P and W of FIG. 2 the line synchronizing pulse in one series occurs inter alia in the signal s.sub.HP of FIG. 3 and the line blanking pulse in the other series occurs in the signal s.sub.HW of FIG. 3.

The front porch is the time difference between the instants when the leading edges of the pulses occur in the signals s.sub.HW and s.sub.HP, that is to say, between t.sub.9 + 2 t.sub.Q and t.sub.7 + 2t.sub.Q which is a time difference of 2 .times. 0.8 .mu.s = 1.6 .mu.s.

It is found that pulse series can be generated with the pulse generator according to FIGS. 1 and 2 which series include pulses of different duration and having a determined time difference between the series which satisfy the limits given in Table 4 for the CCIR standard.

In FIG. 1 the phase discriminator B is shown for synchronizing the clock pulse generator A at the line frequency. The 5-to-1 dividers and the 125-to-1 dividers L and M may be synchronized at the field frequency by the external field synchronizing signal s.sub.VES if this is present. In FIG. 2, a synchronizing circuit is shown in detail for the signal s.sub.VES which will be described in combination with the signals given in FIG. 4.

The external field synchronizing signal s.sub.VES is applied through an isolating capacitor C.sub.6 and a resistor R.sub.9 in series to the base electrode of an npn-transistor T.sub.2, which base electrode is connected through a resistor R.sub.10 to the potential U. The base electrode of a second npn-transistor T.sub.3 is connected to the collector electrode of the transistor T.sub.2 while the two emitter electrodes are connected to ground. The collector electrode of transistor T.sub.3 is directly connected to the S.sub.2 inputs of the flip-flops L1....L3, M3.....M7 and is indirectly connected through the diode T.sub.1 to the inputs of the flip-flops M1 and M2. The collector electrode of transistor T.sub.2 is connected to ground through a capacitor C.sub.7 and to the output of a NAND gate N.sub.3 through a resistor R.sub.11. The inputs of the gate N.sub.3 receive the signals m1 and y so that the output conveys a potential corresponding to the signal z of FIG. 4.

Starting from the assumption that the supply for the synchronizing circuit (T.sub.2, T.sub.3) is provided through the gate N.sub.3 and that the signal s.sub.VES is absent or that no synchronizing pulse occurs in the signal s.sub.VES, the transistor T.sub.2 is conducting. Approximately the ground potential is impressed on the base electrode of the transistor T.sub.3 so that transistor T.sub.3 is cut off. The S.sub.2 inputs of the flip-flops L1......L3, M1.....M7 convey the logic 1 due to internal couplings and due to the resistor R.sub.2 being connected to potential U.

If in the presence of the supply through the gate N.sub.3 a negatively directed edge of a synchronizing pulse occurs in the signal s.sub.VES, the transistor T.sub.2 is cut off while transistor T.sub.3 becomes conducting so that the ground potential occurs at its collector electrode. As a result a pulse going from the logic 1 to the logic 0 occurs at the S.sub.2 inputs of the flip-flops L1....L3, M1......M7. The result is that all Q.sub.1 outputs of the flip-flops L1......L3, M1.......M7 should convey the logic 0. A consideration of the signal s.sub.VES in relation to the signals l1.....l3, m1......m7 of FIG. 4 leads to the conclusion that the negatively directed resetting edge in the signal s.sub.VES can only occur between the instants t.sub.136 and t.sub.138 without exerting influence, which corresponds to the synchronized state. If the resetting edge occurs in the signal s.sub.VES beyond the instants t.sub.136 and t.sub.138, the circuit of frequency dividers including the flip-flops L1......L3, M1......M7 is brought in the said synchronized state. The time difference between the instants t.sub.136 and t.sub.138 corresponds to a half line period within which the synchronisation is ensured by the phase discriminator B of FIG. 1.

The supply of the transistor T.sub.2 through the gate N.sub.3 whereby the signal z of FIG. 4 is impressed on the collector electrode results in the supply dropping out during the period between the instants t.sub.130 and t.sub.140 in the synchronized state of the circuit of frequency dividers including flip-flops L1.....L3, M1....M7. The transistor T.sub.3 of FIG. 2 then remains cut off, even when the resetting edge occurs in the signal s.sub.VES. It has been achieved that in the synchronized state the then superfluous signal s.sub.VES does not result in needless switching on the S.sub.2 inputs of the flip-flops L.sub.1....L.sub.3, M1....M7 and through the resistor R.sub.2 on potential U.

In a practical embodiment the pulse generator of FIG. 2 is formed as follows:

In a twofold JK flip-flop of the type FCJ 121 the combinations: D1-D2, D3-E1, E2-E3, F-I, L1-L2, L3-W, M1-M2, M3-M4, M5-M6, X-Y; M7 1/2 FCJ 121. A JK flip-flop of the type FCJ 201 for P. A fourfold NAND gate of the type FCH 191 for the gates Z, N.sub.1, N.sub.2 and N.sub.3. A diode BAX 13 for T.sub.1. Two transistors BSY 39 for T.sub.2 and T.sub.3. A potential U of + 6V.

R.sub.1, r.sub.4, r.sub.7 = 2.2 k .OMEGA.

R.sub.2, r.sub.5, r.sub.8 = 3.9 k .OMEGA.

R.sub.3, r.sub.6 = 1 k .OMEGA.

R.sub.9 = 330 .OMEGA.

r.sub.10 = 10 k .OMEGA.

R.sub.11 = 4.7 k .OMEGA.

C.sub.1, c.sub.5, c.sub.6 = 1 nF.

C.sub.2, c.sub.3 = 2.2 nF

C.sub.4 = 4.7 nF

C.sub.7 = 10 nF.

In the combination of the flip-flops X and Y it is noted that the S.sub.2 input which is common for both flip-flops influences with the signal x' the action of Y but not the action of the flip-flop X, which may be derived from FIG. 5.

It will be evident that the invention is not restricted to the embodiment of a pulse generator suitable for the CCIR standard and shown in FIGS. 1 and 2. The H.C.F. of the pulse periods in and the time differences between the synchronizing and blanking signals in relation to a half line period may be determined for any other television standard. The connections for the generator I of the auxiliary pulses of line frequency and double line frequency may be chosen in a simple manner dependent on the desired pulse period with its keying influence.

FIG. 10 shows a PAL chrominance subcarrier gating signal generator formed with five JK flip-flops denoted by the references FF.sub.1 to FF.sub.5. Arrow heads are shown for a few T, J, K and S.sub.2 inputs of the flip-flops FF.sub.1.....FF.sub.5 on which a trigger action is performed. For some inputs of the flip-flops FF.sub.1.....FF.sub.5 signals are shown which occur in the pulse generator which is shown in detail in a block-schematic diagram in FIGS. 1 and 2. These signals are derived from the circuits of frequency dividers (D, E, F or L, M) dividing to the line or field frequency, the pulse generators I and Y and the clock pulse generator A. The time relation between the different signals follows from the time diagrams given in FIGS. 3 to 7. The flip-flops FF.sub.1 and FF.sub.2 of FIG. 10 will be described in combination with the signals shown in FIG. 11 after the commencing instant t.sub.0 of a line period T.sub.H. As indicated in FIG. 11, the starting point in this case is the state at which the S.sub.2 input of the flip-flop FF.sub.1 has the logic 1 (S.sub.2 = 1).

The signal i is applied through a capacitor C.sub.8 to the J-input of the flip-flop FF.sub.1 coupled to ground through a resistor R.sub.12. The capacitor C.sub.8 and the resistor R.sub.12 constitute a differentiating circuit whose action follows from the signal J = i' shown in FIG. 11. The connected K input which is further not shown has the logic 1 (K = 1) due to internal couplings. The T input of the flip-flop FF.sub.1 receives the signal d1.

With the aid of Table 1 regarding the action of a JK flip-flop, the signal Q.sub.2 of FIG. 11 follows at the output Q.sub.2 (FF.sub.1). For J = 0 and K = 1 it follows that Q.sub.2 = 1 provides the stable state of the flip-flop FF.sub.1. A negatively directed edge in the signal J = i' at the instant t.sub.3 does not have any influence, the logic 0 remains present. After the instant t.sub.13 a positively directed edge occurs at a propagation delay time of 1t.sub.Q in the signal J = i'. The logic 1 occurs in the signal J = i' until after the instant t.sub.15 when the signal T = d1 has an edge 0.fwdarw.1. At the instant t.sub.16, with an edge 1.fwdarw.0 in the signal T = d1, there consequently applies that J = K = 1 so that the flip-flop FF.sub.1 must change over. (Table 1). At the instant t.sub.16 + 1 t.sub.Q the signal Q.sub.2 has the logic 0. In the signal T = d1 a subsequent negatively directed edge occurs at the instant t.sub.18 for which applies that K = 1 and J = 0 or 1. It follows from Table 1 in both cases that the flip-flop FF.sub.1 changes over again. The signal J = i' is accompanied by the tolerance within which the trailing edge of the possibility directed pulse should be located, namely from and including the instant t.sub.15 up to before the instant t.sub.20. Negatively directed edges in the signal T = d1 occurring after the instant t.sub.20 therefore do not exert influence on the flip-flop FF.sub.1. A pulse having the logic 1 appears at the Q.sub.2 output of the flip-flop FF.sub.1 between instants t.sub.16 + 1 t.sub.Q and t.sub.18 + 1t.sub.Q.

The Q.sub.2 output of flip-flop FF.sub.1 is connected to the S.sub.2 input of the flip-flop FF.sub.2. The input T(FF.sub.2) receives the signal a. The K input is connected to ground and the J input is floating so that K = 0, J = 1. For J = 1, K = 0 it follows from Table 1 that Q.sub.1 = 1 and Q.sub.2 = 0 is the stable state of the flip-flop FF.sub.2 before the signal Q.sub.2 of flip-flop FF.sub.1 exerts a trigger action at the instant t.sub.16 + 1t .sub.Q on the input S.sub.2 (FF.sub.2). As a result the output Q.sub.1 (FF.sub.2) obtains the logic 0 at the instant t.sub.16 + 2t.sub.Q. During the pulse in the signal Q.sub.2 of the flip-flop FF.sub.1 the signal T = a does not exert influence on the flip-flop FF.sub.2, but the first occurring negatively directed edge at the instant t.sub.19 - 1t.sub.Q causes the flip-flop FF.sub.2 to change over to the stable state. The output Q.sub.1 (FF.sub.2) therefore conveys a signal having a pulse ranging from the instant t.sub.16 + 2t.sub.Q to t.sub.19 which is indicated by means of signal Q.sub.1 = s.sub.CC in FIG. 11.

The signal s.sub.CC generated by means of the flip-flops FF.sub.1 and FF.sub.2 has a duration of (t.sub.19 - t.sub.16) -2t.sub.Q = 3 .times. 0.8 .mu.s - 2 .times. 70 ns = 2.26 .mu.s. The leading edge at the instant t.sub.16 + 2 t.sub.Q is located 7 .times. 0.8 .mu.s = 5.6 .mu.s later relative to the leading edge of the line synchronizing pulse s.sub.HP shown in FIG. 3 (occurring at the instant t.sub.9 + 2t.sub.Q). The signal s.sub.CC is therefore the chrominance subcarrier gating signal described in the PAL standard which must start 5.6 .mu.s after the leading edge of the line synchronizing pulse and has a duration of 10 periods of the chrominance subcarrier signal at a frequency of 4 433 618.75 Hz being 2.26 .mu.s. The PAL gating signal s.sub.CC generated by the flip-flops FF.sub.1 and FF.sub.2 may be applied to a gating circuit (not shown) another input of which may be connected to a chrominance subcarrier oscillator.

Without further steps a gating signal generator including only the flip-flops FF.sub.1 and FF.sub.2 would generate a gating pulse for each line period T.sub.H in the signal s.sub.CC. However, the PAL standard stipulates that the gating pulse must not occur over a duration of nine line periods around the equalizing and field synchronizing period. The instant of beginning and ending of this blocking duration is different for successive fields and has a cycle of four field periods. This cycle will become clearly apparent from the following description. The action of the flip-flops FF.sub.1 and FF.sub.2 may be blocked by applying the required blocking pulse with the logic 0 to the S.sub.2 input of the flip-flop FF.sub.1. During the pulse duration (logic 0) of the blocking signal indicated by a signal s.sub.C at the input S.sub.2 (FF.sub.1) the output Q.sub.2 (FF.sub.1) maintains the logic 1 as well as Q.sub.1 (FF.sub.2).

The PAL blocking signal signal s.sub.C is generated at the Q.sub.1 output of the flip-flop FF.sub.3. The flip-flop FF.sub.3 is of the type using multiple formed command J and K inputs. The inputs J.sub.1 and K.sub.3 receive the signals y and l2, respectively, of FIG. 4. The J.sub.2 and J.sub.3 inputs of the flip-flop FF.sub.3 are connected to the Q.sub.2 outputs of the flip-flops FF.sub.4 and FF.sub.5, respectively. The K.sub.1 and K.sub.2 inputs of the flip-flop FF.sub.3 are connected to the Q.sub.1 outputs of the flip-flops FF.sub.4 and FF.sub.5, respectively. The flip-flops FF.sub.4 and FF.sub.5 serve for generating auxiliary pulses for the flip-flop FF.sub.3 and all three flip-flops combined constitute a blocking signal generator (FF.sub.3, FF.sub.4, FF.sub.5). The interconnected J and K inputs of the flip-flop FF.sub.4 receive the signal f and the T input receiver the signal i. The input T (FF.sub.5) receives the signal m1. The input J (FF.sub.5) is connected to ground through a resistor R.sub.13 and receives the signal m7 (m7') through a capacitor C.sub.9, which signal is differentiated.

In FIG. 12 the signals are shown for the flip-flop FF.sub.4 around the commencement of an equalizing and field synchronizing period. This is apparent from a comparison of the signal T = i with the signals of FIG. 7, particularly of FIG. 7c. For the signal J = K = f with the logic 1 it follows from Table 1 that the negatively directed edge in the signal T = i which is active as a trigger edge at the periodically occurring instants t.sub.13 causes the flip-flop FF.sub.4 to change over. An edge 1.fwdarw.0 in the signal T = i when J = K = f has the logic 0 has no influence as is shown in FIG. 12 at the instant t.sub.53. The signal J = K = f has a keying function while the signal T = i gives exactly the instants of the edges. The flip-flop FF.sub.4 which is active as an auxiliary pulse generator generates an auxiliary signal Q.sub.1 = ff.sub.4 shown in FIG. 12, which signal is a blocking signal of half the line frequency.

In FIG. 12 the signals for the flip-flop FF.sub.5 are shown after the instant of commencement t.sub.100 of a field period T.sub.V. The signals T = m1 and J = m7' follow from FIG. 4. At the instant t.sub.100 a positively directed edge 0.fwdarw.1 occurs in the signal T = m1. Subsequently, an edge 0.fwdarw.1 occurs at a time difference of 6t.sub.Q in the signal J = m7'. As has been described with reference to the flip-flop X in FIG. 5 for K (X) = m7', the result is that due to the negatively directed edge 1.fwdarw.0 in the signal T = m1 at the instant t.sub.110 the flip-flop FF.sub.5 changes over because J = K = 1. After the instant t.sub.110 there applies that J = 0 and K = 1 so that the next edge 1.fwdarw.0 causes the flip-flop FF.sub.5 to change over to its stable state at the instant t.sub.130 in the signal t = m1. The flip-flop FF.sub.5 generates a signal Q.sub.1 = ff.sub.5 which shows a pulse at the field frequency between the instants t.sub.110 and t.sub.130 (+1t propagation delay time).

The operation of the flip-flop FF.sub.3 follows from the time diagrams of FIG. 13. In FIG. 13 the beginning of a field period T.sub.V is shown from the instant t.sub.100 during fourteen line periods T.sub.H. For the signal K.sub.3 = 12 a few periodically occurring instants t.sub.0....t.sub.80 = t.sub.0 .... t.sub.40.......etc of the line frequency time scale are shown. A delay time of 4t.sub.Q relative to this time scale is not shown, but the delay of 2t.sub.Q of the edges in the signal K.sub.2 = ff.sub.5 is shown relative to that in the signal K.sub.3 = 12. In the signals J.sub.1 = y and J.sub.3 = ff.sub.5 the edges of the pulses occurring at the field frequency are also shown.

For the 625-line standard employing interlacing there applies that a field period T.sub.V corresponds to 312.5 line periods T.sub.H. The signal K.sub.3 = 12 has a period of 2.5 T.sub.H so that in each field period T.sub.V 312.5/2.5 = 125 periods of the signal K.sub.3 = 12 occur. In FIG. 12 the auxiliary signal Q.sub.1 = ff.sub.4 is shown for the flip-flop FF.sub.4 as a blocking signal having a period which is equal to two line periods T.sub.H. In a field period T.sub.V 312.5/2 = 156.25 periods of the signal ff.sub.4 consequently occur so that the signal ff.sub.4 exhibits a phase shift in a cycle of four field periods T.sub.V. In FIG. 13 the signals K.sub.1 = ff.sub.4 and J.sub.2 = ff.sub.4 are shown in a cycle of four field periods T.sub.V by means of V.sub.1, V.sub.2, V.sub.3 and V.sub.4 . Calculated on the time scale determined at the signal K.sub.3 = 12 the edges in the signals K.sub.1 = ff.sub.4 and J.sub.2 = ff.sub.4 are found to occur at the instants t.sub.53 and t.sub.13 in successive fields V.sub.1, V.sub.2 etc. The signal Q.sub.1 = ff.sub.4 of FIG. 12 corresponds to the signal K.sub.1 = ff.sub.4 of the flip-flop FF.sub.3 in FIG. 13 for the field V2.

The signals at the multifold J and K inputs of the flip-flop FF.sub.3 are combined through an AND gate function to form a signal J and a signal K, the fields V1, V2, V3, V4 being indicated. It is found from the signal K that the signal K.sub.2 = ff.sub.5 has a keying function while the edges in the signal K are determined by the signals K.sub.1 = ff.sub.4 and K.sub.3 = 12. The same applies to the signal J with the signal J1 = y and the signals J.sub.2 = ff.sub.4 and J.sub.3 = ff.sub.5.

The T input (not shown) of the flip-flop FF.sub.3 is not connected and conveys a logic 1. For the operation of the flip-flop FF.sub.3 Table 5 applies with reference to the action of a JK flip-flop having a command J and K inputs for T = 1.

It is found that prior to the instant t.sub.110 there applies for all fields V1..V4 that K = 0 and that J varies between 1 and 0. A stable state Q.sub.1 = 1 (Table 5) is associated therewith such as is shown for the signal Q.sub.1 = s.sub.C with fields V1, V2, V3 and V4. After the instant t.sub.110 pulses appear in the signal K up till the instant t.sub.130 while the signal J has the logic 0. For J = 0 and K 1.fwdarw.0 there follows that Q.sub.1 must start to convey the logic 0. The first occurring edge 1.fwdarw.0 in the signal K is supplied for the fields V1, V2 and V3 by the signal K.sub.1 = ff.sub. 4 (t.sub.53, t.sub.13) and is supplied for the field V4 by the signal K.sub.3 = 12 (t.sub.0).

Up till the instant t.sub.150 (signal J.sub.1 = y) the signal J maintains the logic 0. After the instant t.sub.150 J pulse appear in the signal. For K = 0 and J 1.fwdarw.0 there follows that Q.sub.1 must convey the logic 1 so that the firsy occurring edges 1.fwdarw.0 cause the flip-flop FF.sub.3 to change over. All these trigger edges are supplied by the signal J.sub.2 = ff.sub.4 with fields V1, V2, V3 and V4 and instants t.sub.13 and t.sub.53.

It is found that the signal Q.sub.1 = s.sub.C conveys a pulse having a duration of 9 T.sub.H in the fields V1, V2 and V3 and of 9.16 T.sub.H in the field V4. This difference of 0.16 T.sub.H caused by (t.sub.13 - t.sub.0) has no detrimental influence on the signal path in a PAL colour television system and may therefore be allowed. The instant of commencement varies in a cycle of 4 fields in a manner as stipulated in the PAL standard for blocking over 9 line periods the series of chrominance subcarrier periods to be transmitted for burst purposes. The flip-flop FF.sub.3 in FIG. 10 applies the PAL blocking signal s.sub.C to the S.sub.2 input of the flip-flop FF.sub.1 so that it must convey the logic 1 at the Q.sub.2 output during the period 9 T.sub.H from an instant t.sub.13 for, for example, the field V2. As a result no gating pulse (t.sub.16......t.sub.19) will occur in the signal Q.sub.1 = s.sub.CC of FIG. 11 after this instant t.sub.13 in connection with the predominance of the signal at the S.sub.2 input of the flip-flop FF.sub.1.

The gating signal s.sub.CC generated by the PAL chrominance subcarrier gating signal generator (FF.sub.1.....FF.sub.5) must have edges which are determined as accurately as possible. To this end it is favourable to take trigger signals for the flip-flops FF.sub.1 and FF.sub.2 at the highest possible frequency. Starting from the signal a provided by the clock pulse generator A as a trigger signal T = a for the flip-flop FF.sub.2, the signal d1 directly derived from the signal a is taken for the flip-flop FF.sub.1 so that for the gating pulse in the signal Q1 =s.sub.CC a most accurately determined duration of 3 clock pulse periods minus 2 propagation delay times of the JK flip-flops FF.sub.1 and FF.sub.2 follows.

A practical embodiment of the PAL chrominance subcarrier gating signal generator according to the invention shown in FIG. 10 is as follows.

Ff.sub.1, ff.sub.2, ff.sub.4, ff.sub.5 = 1/2 fcj 131

ff.sub.3 = fcj 201

c.sub.8, c.sub.9 = 2.2 nF.

R.sub.12, r.sub.13 = 1 k.OMEGA..

In the pulse generator according to FIGS. 14 and 15 the greater part of the components shown is denoted in a similar manner as in FIGS. 1 and 2. The block schematic diagram according to FIG. 14 will be described in combination with the detailed circuit diagram according to FIG. 15. In FIG. 14 the direction of the signal transmission in a general sense is denoted by a single arrow head; signal paths having a considerable trigger action on generators still to be described are provided with double arrow heads.

An output of a clock pulse generator A in FIG. 14 provides a signal a at a frequency of 80 .nu. .sub.H to a circuit of frequency dividers D, E and F11. The frequency divider F11 provides a signal f11 of the frequency .nu..sub.H to a phase discriminator B to which also an external synchronizing signal of the frequency .nu..sub.H is applied, while an output signal thereof synchronizes the clock pulse generator A. For the CCIR standard .nu..sub.H is the line frequency of 15,625 Hz and for the RTMA standard for colour and monochrome television .nu..sub.H is equal to 15,734.265.... Hz. Dependent on the external synchronizing signal applied to the discriminator B for the CCIR or RTMA standard, the generator A is synchronized. When, as is shown in FIG. 15 for the sake of simplicity, there is no external synchronisation, the generator A provided with two outputs may supply the signal a at the frequency of 80 .nu..sub.H for the RMA or CCIR standard at an output indicated by R or C. The standard may be chosen by means of a selector switch not further shown. In FIGS. 14 and 15 more selector switches having an R and a C position are shown and on and off-switches R and C are shown. Since FIGS. 14 and 15 will be described in the first instance for the RTMA standard, the switches which are mutually coupled mechanically or in a different manner are shown in the position R applying to this standard. Further Figures, which provide signals occurring particularly in the RTMA or CCIR position of the pulse generator or are of importance are likewise denoted by R or C.

The frequency dividers D and E of FIG. 14 are together active as a 40-to-1 divider which is built up from a 3-to-1 divider D and a 14-to-1 divider E from which the 40-to-1 divider is obtained by means of a feedback. For the positions R and C a different switchable feedback is realized. As is shown in greater detail in FIG. 15, the 3-to-1 divider D consists of two divider stages D11 and D12 and the 14-to-1 divider E consists of four divider stages E11, E12, E13 and E14. Each divider stage is formed as a JK flip-flop. For the RTMA standard the stage of flip-flop E13 is fed back to D11 and for the CCIR standard E14 is fed back to D12.

An output of the divider E conveying a signal e14 at double the line frequency is connected to a circuit of frequency dividers L and M employing a dividend of 21 for the divider L for the RTMA standard, or 25 for the CCIR standard and a fixed dividend of 25 for the divider M. For the RTMA standard employing 21 .times. 25 = 525 interlaced lines the frequency divider M provides a signal of the field frequency .nu..sub.V. For synchronisation purposes an external synchronizing signal s.sub.VES is applied to the dividers L and M.

The divider L is built up from a 3-to-1 divider, a 2-to-1 divider and a 5-to-1 divider together including six divider stages which are denoted by means of JK flip-flops L11....L16 in FIG. 15. the 21-to-1 divider is obtained by feeding back the flip-flop L16 to the flip-flops L13 and L14, so that the 3-to-1 divider is combined with a 7-to-1 divider. The 25-to-1 divider is obtained by feeding back the flip-flop L13 to L11 so that two 5-to-1 dividers are combined. The divider M consists of an 8-to-1 divider and a 3-to-1 divider consisting of five flip-flops M71....M15, the flip-flop M11 being switches in a particular manner and receiving at a blocking input an auxiliary pulse y of field frequency for realizing the 25-to-1 divider.

Outputs of the circuit of frequency dividers L and M are connected to pulse generators X, Y, Z and ZZ which provide signals x, y, z and zz or inverse values thereof (for example zz). The signals x, y, and z are already given for the CCIR standard and in that case they include pulses occurring at the field frequency at a pulse duration of 20T.sub.H, 7.5 T.sub.H and 2.5 T.sub.H, respectively, in which T.sub.H is the line period in the CCIR standard. It will be apparent that the additional signal zz in the CCIR standard also has a 2.5 T.sub.H pulse of field frequency which, however, occurs at an earlier instant in a field period T.sub.V than the pulse in the signal z. The pulse generator ZZ is of importance for generating the PAL gating signal and is also used for generating the signals x and y.

For the RTMA standard the pulse generators X, Y, Z and ZZ provide signals x, y, z and zz having pulses occurring at the field frequency at a pulse duration of 20 T.sub.H, 9T.sub.H, 3T.sub.H and 1.5 T.sub.H, in which T.sub.H is the line period in the RTMA standard. These signals are shown inter alia in FIG. 18.

The pulse generators Y, Z and ZZ are controlled by the frequency dividers L and M without the interposition of change-over switches; in the generator X two coupled change-over switches having positions R and C are required.

A synchronizing signal generator P and a blanking signal generator W receive the signals y and z and the signal x respectively, while they are both connected to outputs of the circuit of frequency dividers D and E. The generator according to FIGS. 14 and 15 is provided with a pulse generator I1 controlled by the circuit D, E, F11, which generator applies a signal i1 and/or i1 to the generators P and W which exhibits auxiliary pulses occurring at the line frequency beyond the equalizing and field synchronizing period of 9 T.sub.H (RTMA) or 7.5 T.sub.H (CCIR) determined by the signal y, while the auxiliary pulses occur at the double line frequency within this period.

Prior to describing the signal path in the pulse generator switched on according to FIGS. 14 and 15 for the RTMA standard with the aid of FIGS. 17 to 23, the requirements which are imposed on the blanking and synchronizing signals according to the RTMA standard will be described first with the aid of FIG. 16.

Unlike the CCIR standard the steepness of the pulses are taken into account for the RIMA standard. The steepness of the edges must be smaller than or may be equal to 0.004 T.sub.H at most. In practice a steepness of the edge of 0.002 T.sub.H occurs generally. The pulse periods are then given between points on the edges which are located at 10% and 90% of the signal amplitude. For the sake of simplicity of FIG. 16 the 0 and 100% values are taken in this case. Starting from infinitely steep edges shown in solid lines during and around the line blanking period. FIG. 16 shows the possible steep edges by means of broken lines. The times laid down in the RTMA standard are shown by solid distance lines, while the chain-link distance lines indicate the times obtained in practice with the aid of the generator. The instants which are laid down in the generator and are also shown in FIGS 17 are denoted by means of cresses.

For the RTMA standard there applies a field synchronizing period 3T.sub.H (signal z), an equalizing and field synchronizing period of 9T.sub.H (signal y) and a field blanking period of approximately 20 T.sub.H (signal x). In this case it has been prescribed that 6 equalizing pulses of the double line frequency must precede and follow 6 field synchronizing pulses of the double line frequency. The duration of the field blanking period in the composite blanking signal must then be 20 T.sub.H .+-. 1 T.sub.H + 1 line blanking pulse duration. Furthermore the requirements imposed in the following Table 6, which requirements are derived from the signals shown in FIGS. 16 and 17, apply. TABLE 6 (FIG. 16, 17)

1. Line blanking pulse duration, signal s.sub.HW : 0.18 T.sub.H.

2. Front porch: .gtoreq.0.02 T.sub.H.

3. Line synchronizing pulse duration, signal s.sub.HP : 0.075 .+-. 0.005 T.sub.H.

4. Back porch to chrominance subcarrier gating signal: .gtoreq.0.006 T.sub.H.

5. Chrominance subcarrier gating signal (burst gate), signal s.sub.CR : .gtoreq.8 periods of chrominance subcarrier = 0.0352 T.sub.H.

6. Synchronizing pulse up to and including gating signal: .ltoreq.0.125 T.sub.H.

7. Synchronizing pulse up to and including blanking pulse: .gtoreq.0.145 T.sub.H.

8. Raster serration duration, signal s.sub.VS : 0.07 .+-. 0.01 T.sub.H.

9. Equalizing pulse duration/line synchronizing pulse duration: 0.45 to 0.50 T.sub.H in which there applies: chrominance subcarrier frequency 3579545 .+-. 10 Hz. Line frequency .nu..sub.H : 2/455 . 3579545 = 15734. 265...... Hz. Line period T.sub.H : 63.55.....mu.s.

Starting from the method of finding the Highest Common Factor H.C.F. for the determined pulse periods and the smallest pulse repetition period of 1/2T.sub.H, a lowest clock pulse frequency of 80 .nu..sub.H is found to be satisfactory also for the RTMA standard. The clock pulse generator A then has a frequency of 12588441.2 Hz and a period of 0.79446 .mu.s .apprxeq. 795 ns.

With reference to FIGS. 16 and 17 in which a time scale of line frequency t.sub.0, t.sub.1.... t.sub.80 = t.sub.0, t.sub.1... derived from the clock pulse periods in the signal a is shown, in which t.sub.Q indicates in accordance with the Handbooks the propagation delay time t.sub.pd occurring in the JK flip-flops of FIG. 15, a Table 7 is given. In this case a clock pulse period is equal to T.sub.H /80 = 0.0125 T.sub.H and a number thereof is given while t.sub.Q is rounded off to 0.001 T.sub.H (63.5 ns) and the maximum steepness of the edges of 0.004 T.sub.H is taken.

It is found that even with the maximum steepness of the edges all requirements are still satisfied, with the values of the synchronizing pulse and the synchronizing pulse up to and including the gating signal reaching the allowed limit values as mentioned under points 3 and 6 of Table 7. For the edge steepness of 0.002 T.sub.H occurring in practice the requirements imposed are amply satisfied.

In a manner analogous to that of FIG. 3, FIG. 17 shows as a function of time a few signals having a logic 0 and 1 during one line period T.sub.H which signals are associated with the generator according to FIG. 15 in the RTMA position. The signals a, d11, d12, e11, e12, e13, e14 and f11 follow with the aid of the description of Table 1 for the operation of a JK flip-flop in a simple manner from the circuit diagram according to FIG. 15 with:

T(d11) = t(d12) = a

k(d11) = q.sub.1 (d12) k(d12) = q.sub.2 (d11)

t(e11) = t(e12) = t(e13) = q.sub.2 (d12)

j(e11) = q.sub.1 (e12)

k(e11) = j(e12) = q.sub.2 (e13) k(e12) = t(e14) = q.sub.1 (e11)

k(e13) = q.sub.2 (e12) j(e13) = q.sub.2 (e11).q.sub.2 (e12)

j(e14) = k(e14) = q.sub.1 (e13)

t(f11) = q.sub.2 (e14).

in the RTMA position S.sub.2 (D11) receives the signal e13' because Q.sub.2 (E13) is connected through a capacitor C.sub.10 and a resistor R.sub.14 to ground to an input of a NAND gate N.sub.4 a further input of which is free and conveys a logic 1 due to internal couplings, while the output is connected to the reset input S.sub.2 of the flip-flop D11. If the free arranged input of the gate N.sub.4 had been connected through a switch to ground with the logic 0, the output would convey a logic 1 independent of the signal e13' applied to the other input; the gate N.sub.4 would then be blocked.

The line frequency time scale t.sub.0. . . .t.sub.40. . . . t.sub.80 = t.sub.0. . . . . shown in FIG. 17 is calculated on the edges in the signals d11 and d12. The edges in the signal a therefore occur 1t.sub.Q earlier, while successive JK flip-flops each introduce an additional propagation delay time 1t.sub.Q.

When considering the 40-to-1 divider D, E over half a line period T.sub.H /2 it is found that negatively directed edges occur in the signal e13 at two instants t.sub.19 + 1 t.sub.Q and t.sub.39 + 1 t.sub.Q (or t.sub.59 + 1t.sub. Q and t.sub.79 + 1t.sub.Q) which are active in the signal e13' at the reset input S.sub.2 (D11). The result is that at these instants the divider D and the subsequent divider E go one pulse further, that it to say, they count one more pulse so that the circuit of dividers D, E adapts a cycle of 40 pulses instead of having its own cycle of 42 pulses without feedback.

Due to a pulse edge displacement obtained the certain choice of the feedback is of importance for generating the trailing edge of the line blanking pulse in the signal s.sub.HW at the instant t.sub.21 + 2t.sub.Q. As is shown in FIGS. 14 and 15, edges may occur in the signal e11 as trigger edges for the blanking signal generator of flip-flop W. As will be apparent from the description of FIG. 22 these are the edges at the instants t.sub.7 + 2t.sub.Q and t.sub.21 + 2t.sub.Q, the latter being obtained by the special feedback. Without the previously occurring feedback and the pulse edge displacement, the edge would have occured at the instant t.sub.22 + 2t.sub.Q (as is necessary for the CCIR standard and as is apparent from FIG. 3).

FIG. 17 shows a few signals described with reference to FIGS. 16 and Table 7 in a time relationship with the circuit of dividers D, E, F11 dividing to the line frequency. In addition to the signal s.sub.HW the line synchronizing pulse occurring at the line frequency from t.sub.9 + 2t.sub.Q to t.sub.15 + 1t.sub.Q in the signal s.sub.HP and the chrominance subcarrier gating pulse occurring from t.sub.16 to t.sub.19 are shown in the signal s.sub.CR. For generating the signal s.sub.CR the pulse generator shown in FIGS. 14 and 15 is to be provided with an additional pulse generator which is shown in FIG. 24 and which will be further described hereinafter.

Furthermore FIG. 17 shows pulses occurring at the double line frequency, namely the equalizing pulse from t.sub.9 + 2t.sub.Q to t.sub.12 + 1t.sub.Q in the signal s.sub.EP and the raster serration from t.sub.3 + 2t.sub.Q to t.sub.9 + 2t.sub.Q in the signal s.sub.VS. Outside the equalizing and field synchronizing period of 9T.sub.H the signal i1 has a pulse occurring at the line frequency from t.sub.3 + 1t.sub.Q to t.sub.9 + 1t.sub.Q and a pulse occurring at double the line frequency within this period from t.sub.43 + 1t.sub.Q to t.sub.49 + 1t.sub.Q. As compared with the auxiliary pulse in the signal i described with reference to FIG. 3, the pulse in the signal i1 has been chosen to be shorter so that, as will be apparent from the description of FIG. 23, this pulse directly provides the raster serrations in the signal s.sub.VS.

The signal e14 of the circuit of dividers D, E is applied to the circuit L, M. In the signal e14 negatively directed edges which are active as trigger edges for the divider L occur at the instants t.sub.1 + 2t.sub.Q and t.sub.41 30 2t.sub.Q of each line period T.sub.H.

Apart from connections of the reset input S.sub.2, the circuit diagram for the JK flip-flops L11. . . . . L16 in the divider L is as follows:

T(l11) = t(l12) = q.sub.1 (e14)

k(l11) = q.sub.2 (l12) j(l12) = q.sub.2 (l11)

t(l13) = q.sub.1 (l12)

t(l14) = t(l15) = q.sub.2 (l13)

k(l14) = q.sub.2 (l15) j(l14) = q.sub.2 (l16)

t(l16) = q.sub.1 (l15) j(l15) = q.sub.2 (l14).

in the RTMA standard S.sub.2 (L13) and S.sub.2 (L14) receive the signal 116' in a feedback because Q.sub.1 (L16) is connected through a capacitor C.sub.11 and a resistor R.sub.15 to ground to an input of a NAND gate N.sub.5 another input of which is free and conveys a logic 1 due to internal couplings, while the output is connected to the reset inputs S.sub.2 of the flip-flops L13 and L14.

The inputs S.sub.2 (L13) and S.sub.2 (L14) are connected to the anode of a diode T.sub.4, while S.sub.2 (L11) and S.sub.2 (L12) are connected to the anode of a diode T.sub.5 whose interconnected cathodes are connected to S.sub.2 (L15) and S.sub.2 (L16). The diode T.sub.4 (and T.sub.5 for the CCIR position to be described) blocks the negatively directed pulse obtained by the feedback so that it acts only on the inputs S.sub.2 (L13) and S.sub.2 (L14).

The divider M following the divider L has the following connection diagram:

T(m11) = q.sub.1 (l14)

j.sub.1 (m11) = q.sub.2 (l16) and J.sub.2 (M11) = Q.sub.1 (Y)

T(m12) = q.sub.1 (m11) t(m13) = q.sub.1 (m12)

t(m14) = t(m15) = q.sub.1 (m13)

j(m14) = q.sub.2 (m15) j(m15) = q.sub.1 (m14).

all reset inputs S.sub.2 are interconnected and are connected to S.sub.2 (L15) and S.sub.2 (L16) and to the collector electrode of an npn-transistor T.sub.3 whose emitter electrode is connected to ground.

Transistor T.sub.3 forms part of an external synchronizing circuit which is formed in the same manner as the circuit described with reference to FIG. 2, so that a further description thereof is not necessary. Normally the transistor T3 is cut off during synchronization and the logic 1 is impressed on all the said S.sub.2 inputs due to internal couplings.

In FIG. 18 the signal path is shown by means of two time scales in the circuit of frequency dividers L, M dividing to the field frequency and the signals zz, x, y, z and s.sub.VES are shown for giving the time relation.

The signal e14 has a trigger edge at each line period T.sub.H at the instants t.sub.1 + 2t.sub.Q and t.sub.41 + 2t.sub.Q from which theh signals l11. . . . . . .l16 follow.

In FIG. 4 a time scale t.sub.100 etc. of field frequency is introduced which has been derived from pulse edges having a propagation delay time of 5 t.sub.Q and, as seen in one line period, commencing at the instant t.sub.0 = t.sub.100 at which t.sub.20 = t.sub.101, t.sub.40 = t.sub.102, t.sub.60 = t.sub.103, t.sub.80 = t.sub.0 = t.sub.104 etc. up to t.sub.1350 = t.sub.100. In FIG. 18 a time scale of field frequency is introduced in a similar manner, but a time index notation has been used only to emphasize that, as seen in one line period, the scale begins at t.sub.1 under the influence of the signal e14. The instant t.sub.100 ' of a field period T.sub.V is the instant t.sub.1 of a line period T.sub.H in which t.sub.104 ' is one line period later, etc. up to t.sub.1150 ' = t.sub.100 ' for the end of a field period T.sub.V in the RTMA standard employing 262.5 lines per field.

In the signal l 16 a few edges are denoted by way of arrow heads which influence the signals l 13 and l14 directly through the signal 116' (now shown) on the inputs S.sub.2 (L13) and S.sub.2 (L14).

The divider M controlled by signal l14, which divider is formed with the 8-to-1 divider M11, M12, M13 and 3-to-1 divider M14, M15 is active as a 25-to-1 divider due to the signal J (M11) = y.116. It has been achieved with this signal combination that the input J(M11) between the instants t.sub.116 ' and t.sub.152 ' (y = 0) has and maintains the logic O. The flip-flop M11 will therefore not change over when t.sub.152 ' a negatively directed edge occurs in the signal l14. The input J (M11) serves as a blocking input for the divider M so that an increase in the dividend is achieved. One pulse is skipped, as it were, in the signal l14 during counting, that is to say, the divider M is stopped during one pulse so that the counter or the divider M has a cycle of 8 times 3 + 1 = 25 pulses.

As has been explained in the description of the external synchronizing signal S.sub.VES with reference to FIG. 2, the negatively directed trigger edge in the signal s.sub.VES in the synchronized state of the pulse generator can only occur around the instant t.sub.137 ' (from t.sub.136 ' to t.sub.138 ') because then only all signals l11....l16, m11....m15 have the logic 0. If there were no synchronisation, the dividers L and M would be forced to take up this state.

FIG. 19 serves for illustrating the manner in which flip-flop ZZ, Y, Z and X of FIG. 15 are active.

The connection diagram of the flip-flop ZZ follows from FIG. 15

T(ZZ) = Q.sub.2 (L15) J(ZZ) = 1, K(ZZ) = 0 and S.sub.2 (ZZ) is connected to Q.sub.1 (M15) through a differentiating circuit which includes two resistors R.sub.16 and R.sub.17 arranged in series between ground and potential U, and a capacitor C.sub.12.

It follows from Table 1 regarding the action of a JK flip-flop in general that for J = l and K = 0 the flip-flop ZZ in the stable state conveys the logic 1 at the Q.sub.1 output and conveys the logic 0 at the inverse Q.sub.2 output. The stable state means that a negatively directed edge at the T input which edge may be active as a trigger edge does not change over the flip-flop. As in the generator according to FIGS. 14 and 15 only the signal Q.sub.2 = zz is used, this signal is shown in FIG. 19.

At the instant t.sub.100 ' the flip-flop ZZ is in its stable state with the logic 0 in the signal Q.sub.2 = zz. It follows from FIG. 18 that at the instant t.sub.110 ' + 4t.sub.Q a negatively directed edge occurs in the signal m15 which, while occurring in the signal S.sub.2 = m15' causes the flip-flop ZZ, to change over. The signal Q.sub.2 = zz has obtained the logic 1 at the instant t.sub.110 ' + 5t.sub.Q. Since the condition J = 1, K = 0 has not changed, the result is that the next negatively directed edge (t.sub.116 ') in the signal T = 115 causes the flip-flop ZZ to change back again. At the instant t.sub.116 '+ 1t.sub.Q the logic 0 is present again in the signal Q.sub.2 = zz, which 0 is maintained until the next field period with a new cycle. A signal zz has been generated with a pulse lasting 1.5 line periods T.sub.H and occurring after 2.5 line periods T.sub.H from the commencement of a field period T.sub.V.

The connection diagram for the flip-flop Y is: T(Y) = Q.sub.2 (L16), J(Y) = 1, K(Y) = 0 and S.sub.2 (Y) connected to Q.sub.2 (ZZ) through a differentiating circuit which includes two resistors R.sub.18 and R.sub.19 arranged in series between ground and potential U, and a capacitor C.sub.13.

The same stable state as described for the flip-flop ZZ applies to the flip-flop Y with J = 1 and K = 0 so that the signal Q.sub.1 = y has the logic 1 at the instant t.sub.100 '. After the instant t.sub.110 ' the signal S.sub.2 = zz' has a positively directed edge and at the instant t.sub.116 '+ 1t.sub.Q it has a negatively directed edge to the logic 0 so that the flip-flop Y changes over. From the instant t.sub.116 ' + 2t.sub.Q until the instant of occurrence of the next negatively directed edge (t.sub.152 '+ 1t.sub.Q) in the signal T = 116 the signal Q.sub.1 = y maintains the logic 0. In the signal Q.sub.1 = y a pulse appears from t.sub.116 + 2t.sub.Q to t.sub.152 ' + 2t.sub.Q which pulse thus lasts 152 - 116 = 9 line periods T.sub.H and commences a 4 line periods T.sub.H after the commencement of a field period T.sub.v.

The generator Z in FIG. 15 is formed as a NAND gate whose inputs are connected to Q.sub.2 (Y) and Q.sub.2 (L15). The output of the gate Z therefore conveys a signal z = y. l15 = y + l15. The signal z has a pulse lasting three line periods T.sub.H which is desired as is shown in FIG. 18, and which pulse lasts from t.sub.128 ' to t.sub.140 ' but has an unwanted additional pulse in FIG. 19, but as will be apparent this additional pulse is harmless for the action of the pulse generator. Since a negatively directed edge occurs in the signal l15 at the instant t.sub.152 ', while in the signal y the positively directed edges does not occur until the instant t.sub.152 ' + 2t.sub.Q, a narrow pulse of 2t.sub.Q (for example, of 140 ns) appears in the signal z.

The generator X in FIG. 14 is formed with switchable inputs to which end a few NAND gates are applied for the flip-flop X in FIG. 15. Two inputs of two NAND gates N.sub.6 and N.sub.7 are interconnected which are free for the position R, but are connected to ground through a change-over switch in the position C. In the position R the gates N.sub.6 and N.sub.7 pass the signal l11 and m11 applied to another input onto the inputs T(X) and J(X), respectively.

For the position R the effective connection diagram of the flip-flop X, in which the inverting action of the gates N.sub.6 and N.sub.7 is taken into account, would be:

T(X) = Q.sub.1 (L11), J(X) = Q.sub.1 (M11), K(X) = 0 and S.sub.2 (X) connected to Q.sub.2 (ZZ) through the differentiating circuit (R.sub.18, R.sub.19 and C.sub.13).

Since in the signal J = m11 of FIG. 19 the logic 1 occurs until the instant t.sub.110 ' and K = 0, the signal Q.sub.1 = x in the stable state of the flip-flop X has the logic 1 before this instant. The logic 0 appearing in the signal J = m11 does not give the negatively directed edges in the signal T = l11 any opportunity to change over the flip-flop X because for J = 0 and K = 0 the flip-flop X is never changed over through signals on the T-input. At the instant t.sub.116 ' + 1t.sub.Q the flip-flop X changes over under the influence of the negatively directed pulse in the signal S.sub.2 = zz'. As long as the signal J = m11 maintains the logic 0, the flip-flop X in the signal Q.sub.1 = x also maintains the logic 0. In the signal J = m11 the logic 1 occurs at the instant t.sub.194 ' + 2t.sub.Q so that the edge in the signal T = 111 occurring at the instant t.sub.196 ' - 2t.sub.Q is active as a trigger edge so as to bring the flip-flop X in the stable state associated with J = 1 and K = 0. A signal x is generated with a pulse of 20 line periods T.sub.H and occurring from t.sub.116 ' + 2t.sub.Q until t.sub.196 '- 1t.sub.Q.

For the flip-flop I in FIG. 15 there applies that:

T(I1 = Q.sub.2 (D11), K(I1) = Q.sub.2 (E12), J.sub.1 (I1) connected to Q.sub.2 (E14) through a differentiating circuit including a resistor R.sub.20 to ground and a capacitor C.sub.14, and J.sub.2 (I1) connected to the output of a NAND gate N.sub.8 whose inputs are connected to Q.sub.1 (F11) and Q.sub.1 (Y).

In FIG. 20 the signals T = d11, J.sub.1 = e14', J.sub.2 = f11.y = f11 + y and K = e12 are shown for the flip-flop I1. These signals are comparable with those given in FIG. 6 because the action of the flip-flop I1 is in principle not different, even if a different signal choice has been made. A considerable difference is, however, that in the signal Q.sub.1 = i1 the pulses are shorter than in the case of the pulse generator according to FIGS. 1 and 2 which is of importance for the signals present at the synchronizing signal generator P.

Since the pulses in the signal i1 have the same number of clock pulses of the signal a, in the RTMA and CCIR standards, which clock pulses are, however, of different duration the R-notation in FIG. 20 has been omitted.

Briefly, the following applies to the signals in FIG. 20:

During each line period T.sub.H the signal J.sub.1 = o14' has two pulses with the logic 1 obtained by differentiation, the first pulse occurring from t.sub.1 + 2t.sub.Q to t.sub.2 at a minimum and t.sub.11 at a maximum and the second pulse occurring from t.sub.41 + 2t.sub.Q, etc. Beyond the equalizing and field synchronizing period with y = 1, the signal f11 in the signal J.sub.2 = f11 + y only has the logic 1 during the first pulse so that only this first pulse in the signal J.sub.1 = e14' provides the logic 1 at the input J(I1). For J = 0 or 1, caused by the signal K = e12, the stable state of the flip-flop I1 is that the Q.sub.1 output conveys the logic 0 as is shown at the instant t.sub.O.

After the logic 1 has appeared at the input J(I1) in the signal J.sub.1 = e14' at t.sub.1 +2t.sub.Q the next negatively directed edge in the signal T = d11 causes the flip-flop I1 to change over at t.sub.3. A subsequent negatively directed edge in the signal T = d11 at the instant t.sub.6 does not have any influence because for K = 0 and J = 1 or 0 the Q.sub.1 output conveys the logic 1 in the stable state. Before the edge in the signal T = d11 at t.sub.9 the condition K = 1 is given by the signal K = e12 while J = 1 or 0. For K = 1 and J = 1 a change-over is effected at each trigger edge while for K = 1 and J = 0 there applies for the stable state that the Q.sub.1 output must convey the logic 0. In both cases a changeover of the flip-flop I1 is effected and a pulse is thus generated in the signal Q.sub.1 = i1 between the instants t.sub.3 + 1t.sub.Q and t.sub.9 + 1t.sub.Q.

During the equalizing and field synchronizing period with y = 0 during 9T.sub.H both pulses in the signal J.sub.1 = e14' become manifest at the input J(I1) and a pulse between the instants t.sub.43 + 1t.sub.Q and t.sub.49 + 1 t.sub.Q is generated during the second half of one line period T.sub.H in the signal Q.sub.1 = i1.

For the sake of simplicity of FIG. 20 the pulses produced by differentiation in the signal J.sub.1 = e14' at the instants t.sub.21 and t.sub.61 which continue to represent the logic 0 and do not exert any influence on the flip-flop I1 are only shown incompletely in broken lines.

FIG. 21 serves for illustrating the operation of the flip-flop I1 at and near the equalizing and field synchronizing period of 9T.sub.H for the RTMA standard. FIG. 21a shows the signal y in relation to the field time scale t.sub.100 ' ,...t.sub.1150 ' given in FIG. 18. FIGS. 21b and 21c apply to two successive fields in which FIG. 21b applies to the field ending in a full line and FIG. 21c applies to the field ending in a half line. The signals f11, J.sub.2 = f11 + y, J.sub.1 = e14' (without the superfluous negatively directed pulses) and Q.sub.1 = i1 are shown for both fields. FIGS. 21b and 21c are self-evident, certainly after what has been described with reference to FIG. 7.

Starting from the definition for a so-called first field for which there applies that the last occurring line synchronizing pulse occurs over an integral number of line periods before the commencement of the field synchronizing period. FIG. 21b is associated with the first field in accordance with the RTMA standard, while FIG. 7b is associated with the first field in accordance with the CCIR standard.

The operation of the blanking signal generator or flip-flop W of FIG. 15 is illustrated by way of FIG. 22 in which FIG. 22a shows the signals which are the same for each field and FIGS. 22b and 22c show signals which are different for successive fields.

For the connection diagram of the flip-flop W in FIG. 15 active as a blanking signal generator there applies that

T(w) = q.sub.1 (e11), k(w) = q.sub.1 (i1),

j.sub.1 (w) = q.sub.1 (e13) and J.sub.2 (W) = Q.sub.1 (X).

In FIG. 22a the signal T = e11 is shown on two scales and partly only negatively directed edges are shown occurring with a delay of 1t.sub.Q after the instants t.sub.1, , t.sub.7, t.sub.21, t.sub.27, T.sub.41, t.sub.47, t.sub.61 and t.sub.67. For the J input a signal J follows from the signals J.sub.1 = e13 also having a delay time of 1t.sub.Q and J.sub.2 = x at an instant t.sub.41 + 7 t.sub.Q for the leading edge and t.sub.41 + 4t.sub.Q for the trailing edge of the pulse lasting 20 T.sub.H.

The signal K = i1 in FIGS. 22b and 22c follows from FIGS. 21b and c with the signal Q.sub.1 = i1. Since there is a shift of half a line period T.sub.H between FIGS. 22b and 22c a few instants are shown in these Figures in which t.sub.o, ..... in one Figure corresponds to t.sub.40, ...... in the other.

For the flip-flop W there applies that for K= 0 and J = 1 or 0 the Q.sub.1 output conveys the logic 1 in the stable stae as may be derived from Table 1. When considering FIG. 22c it is found that a pulse with the logic 1 occurs in the signal K = i1 between the instants t.sub.3 and t.sub.9 while a negatively directed edge occurs at the instant t.sub.7 in the signal T = e11, which edge is active as a trigger edge. The signal Q.sub.1 = w has obtained the logic 0 at the instant t.sub.7 + 2t.sub.Q. At the instant t.sub.13 the signal t = e11 obtains the logic 1 while the logic 0 then occurs in the signal K = i1 and the logic 1 occurs in the signal J. Associated therewith is a stable state with the logic 1 in the signal Q.sub.1 = w. Although under the influence of the signal e13 of FIG. 17 the logic 0 appears in the signal J at the instant t.sub.19, the logic 1 information is maintained in the flip-flop W so that the negatively directed edge in the signal T = e11 causes the flip-flop W to change over at the instant t.sub.21. This mechanism is denoted by means of a dot in the signal J. The result is that a line blanking pulse denoted by s.sub.HW appears in the signal Q.sub.1 = w which pulse appears between t.sub.7 + 2t.sub.Q and t.sub.21 + 2t.sub.Q, that is to say, a duration of 14 clock pulse periods of the signal a, hence 14 .times.0.0125 = 0.175 T.sub.H.

For FIG. 22b there applies that the signal K = i1 approximately determines the position of the leading edge in the same manner and the signal J.sub.1 = e13 determines the position of the trailing edge, while the edges of the line blanking pulses s.sub.HW are exactly determined by the signal T = e11.

In FIGS. 22b and 22c the first pulse in the signal K = i1 occurring after the signal J.sub.2 = x in the signal J has given the logic 0 causes the flip-flop W to change over at the instant t.sub.7 or T.sub.47. Subsequently, the logic 0 in the signal J is maintained during approximately 20 line periods T.sub.H. During the first 9 line periods T.sub.H with y = 0 pulses of double line frequency occur in the signal K = i1 and during the rest of the time with y = 1 pulses of line frequency occur only so that K = 1 or 0. For J = 0 and K = 1 or 0 the flip-flop W is in the stable state with the signal Q.sub.1 = w conveying the logic 0.

At the end of the 20 line periods T.sub.H the next pulse with the logic 1 in the signal J.sub.1 = e13 becomes manifest in the signal J. Due to the condition J = 1 and K = 0 the next negatively directed edge in the signal T = e11 occurring at the instant t.sub.61 (FIG. 22a) causes the flip-flop W to change over. The flip-flop W thus generates a field blanking pulse which in FIG. 22b lasts from t.sub.7 + 2t.sub.Q to t.sub.21 +2t.sub.Q and in FIG. 22c from t.sub.47 + 2t.sub.Q to t.sub.61 + 2t.sub.Q plus 20 full line periods T.sub.H. The field blanking pulse thus lasts 20 line periods T.sub.H and 14 clock pulse periods of the signal a, that is to say, one line blanking period (s.sub.HW).

Subsequently, the auxiliary pulses in the signal K = i1 of FIGS. 22b and 22c provide the opportunity for the negatively directed edges in the signal T = e11 of FIG. 22a to generate the line blanking pulses s.sub.HW by means of the flip-flop W, while these edges are active as trigger edges.

For the connection diagram of the flip-flop P of FIG. 15 active as a synchronizing signal generator there applies that: T(P) = Q.sub.2 (D11),J3(P) = Q.sub.1 (E13) K = 0, S.sub.1 (P) = Q.sub.2 (I1), S2(P) connected to Q.sub.1 (I1) through a differentiating circuit having two resistors R.sub.21 and R.sub.22 arranged in series between ground and the potential U, and a capacitor C.sub.15 ; J.sub.2 (P) connected to the output of a NAND gate N.sub.9 to inputs of which Q.sub.2 (E11) and Q.sub.1 (Y) are connected, and J.sub.1 (P) connected to the output of the NAND gate Z.

For the input S.sub.1 of the JK flip-flop not yet used in the description there applies that for S.sub.1 = 0, Q.sub.1 must be 1. As already noted there applies for the reset input S.sub.2 that for S.sub.2 = 0, Q.sub.1 must be 0.

FIG. 23 shows the signals for the flip-flop P and relates to 22 half line periods T.sub.H /2 occurring during and near the equalizing and field synchronizing period. The periods of time 1, 2, 3; 8, 9, 10; 14, 15, 16 and 20, 21, 22 are shown for the numbered half line periods. Due to the periodicity of the signals in the half line periods, the time scale t.sub.O....t.sub.40 is taken for each half line period T.sub.H /2.

Since there applies for the flip-flop P that K==0, the signal J is of importance so as to give the negatively directed edges in the signal T = d11 the possibility to be active as trigger edges. For K = 0 and J = 0 there applies that the signal T = d11 can never make the flip-flop P change over. If J = 1 when K = 0, there applies that Q.sub.1 = 1 for the stable state of the flip-flop P; if this state is not present, a changeover to this state is effected.

The signal J in FIG. 23 causes the flip-flop P to generate other pulses in the (synchronizing) signal Q.sub.1 = p during the field synchronizing period, the equalizing period and the period beyond these intended for the line synchronisation. The signal J.sub.1 = z provides the logic 0 during the field synchronizing period of 3T.sub.H in the signal J so that the edges in the signal T = d11 do not exert any influence. The signal J.sub.2 = e11 + y together with y = 1 causes the signal J.sub.3 = e13 to become manifest in the signal J during the equalizing and field synchronizing period of 9 T.sub.H. Outside the period of 9 T.sub.H a combination of the signals e11 (of the signal J.sub.2 = e11 + y with y = 0) and J.sub.3 = e13 becomes manifest in the signal J, the leading edges of the pulses in the signal J being determined by e11 (t.sub.13 relative to t.sub.10).

The signals S.sub.1 = i1 and S.sub.2 = i1' and the signal Q.sub.1 = p derived therefrom are partly shown in solid, broken and chain-link lines so as to indicate the periodicity results of the two television fields in one Figure. In FIGS. 21 and 22 the FIGS. 21b, 21c and 22b, 22c are given for this purpose. When a pulse denoted by chain-link lines occurs in the signal S.sub.1 = i1 as corresponds to FIGS. 21b and 22b during the period of time 1 of FIG. 23 as well as in the signal S.sub.2 = i1', the following is effected: starting from the stable state of the flip-flop P with Q.sub.1 = 1 for the condition that K = 0 and J = 1 or 0, the pulse with the logic 0 occurring from t.sub.3 + 1t.sub.Q to t.sub.9 + 1t.sub.Q in the signal S.sub.1 = i1 will not cause the flip-flop P to change over because Q.sub.1 is 1 already. After the instant t.sub.9 a pulse with the logic 0 obtained by differentiation occurs in the signal S.sub.2 = i1' for which there applies that Q.sub.1 = 0; the flip-flop P changes over and the logic 0 appears in the signal Q.sub.1 = p. The next negatively directed edge in the signal T = d11 occurs at the instant t.sub.12. The signal J has the logic 0 at the instant t.sub.12 under the influence of the signal e11 in J.sub.2 = e11 + y. Since the condition K = 0 and J = 0 applies, the flip-flop P cannot be changed over by the signal T =d11. In the signal J a logic 1 occurs due to the signal e11 at the instant t.sub.13 + 1t.sub.Q. A second negatively directed edge in the signal T = d11 at the instant t.sub.15 causes the flip-flop P to change over to the stable state with Q.sub.1 = 1 in case of the condition J = 1 and K = 0.

The same description applies to the period of time 2 for the pulses shown in broken lines and associated with the signals of FIGS. 21c and 22c.

The result is that in the signal Q.sub.1 = P line synchronizing pulses s.sub.HP are generated which last from t.sub.9 + 2t.sub.Q to t.sub.15 + 1t.sub.Q, that is to say, 6 .times. 0.0125 T.sub.H -0.001T.sub.H = 0.074T.sub.H as already given with reference to FIGS. 16 and 17 and Table 7.

During the period of time 1 a time variation .delta. t has been given for the signals S.sub.1 = i1 and S.sub.2 = i1' between the instant t.sub.9 and the exact instant of occurrence of the negatively directed edge in the signal S.sub.2 = i1' while the positively directed edge occurs in the signal S.sub.1 = i1 within the time variation .delta.t. Up till now the propagation delay time t.sub.Q has been given to correspond with a propagation delay time t.sub.pd of a JK flip-flop. There are flip-flops which have a difference in propagation delay time between an input and the two outputs Q for a positively or negatively directed edge occurring. The time t.sub.pd is then distinguished in t.sub.pdr (rise propagation delay time) and t.sub.pdf (fall propagation delay time) in which t.sub.pdr is generally smaller than t.sub.pdf. The positively directed edge then commences at an earlier instant than the negatively directed edge which has, however, a steeper slope and which reaches the final value at a quicker rate than the positively directed edge, but relative to a measuring reference potential of 1.5 V the positively directed edge having a more gentle slope reaches this final value earlier than the negatively directed edge. For a JK flip-flop I1 of the type FCJ 121 the practical measurement was that t.sub.pdr = 50 ns and t.sub.pdf = 70 ns = .delta.t in FIG. 23. The difference of 20 ns guarantees that the signals S.sub.1 = i1 and S.sub.2 = i1' having an opposite action at the instant t.sub.9 do not yield any uncertainty for the flip-flop P, while this effect will be used in a positive manner in the field synchronizing period of 3 T.sub.H.

During the periods of time 3.....8 the signal J.sub.3 = e13 becomes completely manifest in the signal J because the logic 1 is present in both signals J.sub.1 = z and J.sub.2 = e11 + y. During the period of time 3 a short pulse of 1t.sub.Q having the logic O occurs in the signal J.sub.2 = e11 + y because the negatively directed edge in the signal e11 occurs at t.sub.1 + 1t.sub.Q and the positively directed edge in the signal y occurs at t.sub.1 + 2t.sub.Q ; this pulse does not appear in the signal J.

When commencing with the period of time 3, the signal S.sub.2 = i1' causes the flip-flop P to change over as has been described with reference to the period of time 1. Since a positively directed edge given by the signal J.sub.3 = e13 occurs in the signal J, at the instant t.sub.10 + 1t.sub.Q, the next negatively directed edge in the signal T = d11 causes the flip-flop P to change over at t.sub.12. In this manner an equalizing pulse is generated in the signal Q.sub.1 = p in each of the periods of time 3.....8, which equalizing pulse is denoted by s.sub.EP. The equalizing pulses s.sub.EP last from t.sub.9 + 2t.sub.Q to t.sub.12 + 1t.sub.Q (Figure 17), that is to say, 3 .times. 0.0125 T.sub.H - 0.001 T.sub.H = 0.0365 T.sub.H. Thus the calculation given in Table 7 under item 9 is satisfied by the six generated equalizing pulses s.sub.EP.

During the periods of time 9.....14 the signal J.sub.1 = z with the logic 0 passes on this logic 0 to the signal J. For the condition K = O and J = O none of the negatively directed edges in the signal T = d11 can be active as a trigger edge. The flip-flop P changes over at the instant t.sub.9 under the influence of the signal S.sub.2 = i1' . During the remaining part of each of the periods of time 9.....14 the signal Q.sub.1 = p maintains the logic O. At the instant t.sub.3 in a next period of time, for example, period of time 10 relative to period of time 9, the negatively directed edge of the pulse with the logic O occurs in the signal S.sub.1 = i1 so that the Q1 output of P must convey the logic 1. The subsequent pulse with the logic O in the signal S.sub.2 = i1' at the instant t.sub. 9 causes the flip-flop P to convey the logic O again at the Q.sub.1 output. The result is that the signals S.sub.1 = i1' provide the raster serrations s.sub.VS in the signal Q.sub.1 = p from t.sub.3 + 2t.sub.Q to t.sub.9 + 2t.sub.Q (FIG. 17) so that six field synchronizing pulses denoted by s.sub.Vp appear in the field synchronizing period of 3T.sub.H. The raster serrations s.sub.VS have a duration of six clock pulse periods, that is to say, they are 6 .times. 0.0125 T.sub.H = 0.0075 T.sub.H.

When generating the raster serrations s.sub.VS and the field synchronizing pulses s.sub.Vp use was made of the property already mentioned that at the instant t.sub.9 the positively directed edge in the signal S.sub.1 = i1 at an earlier instant (approximately 20 ns) than the negatively directed edge in the signal S.sub.2 = i1' so that at this instant t.sub.9 there is no uncertainty about the state of the flip-flop P. To this end the flip-flop I1 is formed as an FCJ 121 having different propagation delay times from the pulse edges to the inverse outputs.

During the periods of time 15.....20 six equalizing pulses are generated in the signal Q.sub.1 = p in an analogous manner as described with reference to the periods of time 3.....8. The following applies for the transition between the periods of time 14 and 15. The signal J.sub.1 = z maintains the logic O until the instant t.sub.1 in the period of time 15. However, it is required for the logic O in the signal J to be maintained until shortly after the instant t.sub.9. Due to the choice of the signal J.sub.3 = e13 with the logic O from t.sub.39 + 1t.sub.Q in the period of time 14 to t.sub.10 + 1t.sub.Q in the period of time 15 it is ensured that this requirement is satisfied.

The periods of time 21 and 22 correspond to the periods of time 1 and 2. For the period of time 21 in particular there applies that the short pulse of 2t.sub.Q described with reference to FIG. 19, occurs in the signal J.sub.1 = z after the instant t.sub.1. It is found that this impulse has no influence on the signal J.

In FIG. 18 it is indicated that relative to FIG. 4, the field time scale is one clock pulse period of the signal a later (0.795 .mu.s). It is found that this does not make any difference for the generated pulses of line frequency and double line frequency, and the difference is negligibly small relative to the pulses occurring at the field frequency.

It is found that the pulse generator according to FIGS. 14 and 15 in the RTMA position generates some of the signals shown in FIGS. 16 and 17 and in Table 7, the front porch following from the time difference between the leading edges of the pulses s.sub.HW (t.sub.7 + 2t.sub.Q) and s.sub.HP (t.sub.9 + 2t.sub.Q).

For generating the said NTSC chrominance subcarrier gating signal (burst gate) s.sub.CR, FIG. 24 shows in detail a generator which can be connected to the pulse generator according to FIGS. 14 and 15, which generator includes in principle one flip-flop FF.sub.16. The other flip-flops shown in FIG. 24 are required for generating a PAL-chrominance subcarrier gating signal s.sub.CC. FIG. 15 shows the signals associated with the flip-flop FF.sub.16.

In FIG. 24 the flip-flop FF.sub.16 receives the signal a at the T input, the signal d12 at the K input and the signal y at the S.sub.2 input. The J input is connected to the collector electrode of an npn-transistor T.sub.6 which is connected through a resistor R.sub.23 to a terminal of potential U. The emitter electrode of transistor T.sub.6 is connected to ground and the base electrode is connected through a resistor R.sub.24 to the potential U and through a capacitor C.sub.16 to a terminal to which the synchronizing signal p is applied. The transistor T.sub.6 is normally conducting with J = O applying for the flip-flop FF.sub.16. A positively directed edge in the signal p does not influence the transistor T.sub.6, a negatively directed edge of a pulse renders the transistor T.sub.6 instantaneously non-conducting for a duration which is determined by the time constant of the resistor R.sub.24 and the capacitor C.sub.16 which act as a differentiating circuit.

FIG. 25 shows a signal p derived from FIG. 23 which provides the possibly occurring pulses over one line period T.sub.H. Solid lines denote a line synchronizing pulse s.sub.HP, fat broken lines denote two equalizing pulses s.sub.EP and thin broken lines partially show two field synchronizing pulses s.sub.VP. Negatively directed edges in the signal p applied to transistor T.sub.6, which edges correspond to positively directed edges in signal p provide a pulse having the logic 1 in the signal J = p' to the J input of FF.sub.16. Starting from the fact that the flip-flop FF.sub.16 was in its stable state at the instant t.sub.o in case of the condition J = O and k = 1 or O, the Q.sub.1 output conveys the logic O as is shown in the signal Q.sub.1 = s.sub.CR. Since no gating signals must be generated during the equalizing and field synchronizing period of 9 T.sub.H with y = O, the signal y is applied to the input S.sub.2 (FF.sub.16). In FIG. 25 the signal S.sub.2 = y is denoted by a solid (1) and a broken line (0) and it follows that for y = O the predominant S.sub.2 input maintains the output Q.sub.1 at the logic O irrespective of what occurs at the T, J and K inputs.

Outside the equalizing and field synchronizing period, a flip-flop FF.sub.6 may be changed over, because a pulse caused by the trailing edge of the pulse s.sub.HP appears with the logic 1 at the instant t.sub.15 + 1 t.sub.Q in the signal J = p' while a negatively directed edge in the signal T = a occurs at the instant t.sub.16 - 1t.sub.Q. In this case K may be 0 or 1. The signal Q.sub.1 = s.sub.CR has the logic 1 at the instant t.sub.16.

In the signal K = d12 the reference K.sub.R denotes the signal which occurs in case of the RTMA standard. At the instants t.sub.17 - 1t.sub.Q and t.sub.18 - 1t.sub.Q having negatively directed edges in the signal T = a, K = O so that for J = 1 or O the Q.sub.1 output maintains the logic 1. At the instant t.sub.18 K.sub.R in the signal K = d12 obtains the logic 1 so that the edge in the signal T = a at the instant t.sub.19 - 1t.sub.Q may be active as a trigger edge for the condition K = 1, J = 1 or 0. At the instant t.sub.19 the logic 0 has appeared in signal Q.sub.1 = s.sub.CR. After the instant t.sub.19 the logic 0 is to occur in the signal J = p' in order that the flip-flop FF.sub.16 does not change over again.

It is found that the flip-flop FF.sub.16 generates the chrominance subcarrier gate signal (burst gate) s.sub.CR already shown in FIGS. 16 and 17 from the instant t.sub.16 to t.sub.19, that is to say, at a duration of three clock pulse periods of the signal a, being 3 .times. 0.0125 T.sub.H = 0.0375 T.sub.H. This corresponds to 455/2 0.0375 = 8.5 periods of the chrominance subcarrier.

The times given in Table 7 and shown in FIG. 16 are self-evident.

So far the switchable pulse generator shown in FIGS. 14 and 15 has only been described as one acting for the RTMA standard. To achieve that the switchable generator according to FIGS. 14 and 15 can also be active for the CCIR standard, three switching operations are carried out as follows:

1. The flip-flop D11 in FIG. 15 receives a logic 1 at the S.sub.2 input because an input of the NAND gate N.sub.4 is connected to ground with the logic o; the gate N.sub.4 is blocked. Subsequently the signal e14' is applied to the reset input S.sub.2 of the flip-flop D12 because Q.sub.1 (E14) is connected through a capacitor C.sub.17 and a resistor R.sub.25 to ground to an input of a NAND gate N.sub.10 another input of which is free and conveys a logic 1 due to internal couplings while the output is connected to S.sub.2 (D12).

2. The flip-flops L13 and L14 receive the logic 1 at the S.sub.2 input through the NAND gate N.sub.5 with an input connected to ground with the logic 0. The signal l13' is applied to the reset input S.sub.2 of the flip-flop L11 because Q.sub.1 (L13) is connected through a capacitor C.sub.18 and a resistor R.sub.26 to ground to an input of a NAND gate N.sub.11 another input of which is free and the output of which is connected to S.sub.2 (L11).

3. The T and j inputs of the flip-flop X are switched over. To this end an input of the gates N.sub.6 and N.sub.7 is connected through a change-over switch to ground with the logic O, position C, so that two other NAND gates N.sub.12 and N.sub.13 are released. Gate N.sub.12 having an input connected to Q.sub.1 (L16) has its output connected to T(X) and gate N.sub.13 having an input connected to Q.sub.2 (Y) has its output connected to J(X).

Although the output of the gate N.sub.11 is connected to both S.sub.2 (L11) and S.sub.2 (L12), the flip-flop L11 only is influenced by the feedback. The reason for the interconnection of S.sub.2 (L11) and S2(L12) is that the flip-flops L11 and L12 can in practice be formed as one twofold flip-flop FCJ 121 having one interconnected input S.sub.2.

To explain the simple switchability of the pulse generator according to FIG. 15 and to illustrate a few important signal differences occurring between the R and C positions, a few signals are partially plotted in FIG. 26, which signals are associated with the frequency dividers D, E F11 and L, and in FIG. 27 associated with the generators ZZ, Y, Z and X. FIGS. 26 and 27 correspond for the position C to FIGS. 17, 18 and 19 for the position R.

The clock pulse period of the signal a of the 80 -fold line frequency .nu..sub.H is 800 ns in FIG. 26. Until the instant t.sub.19 when the feedback is effected with the signal el3' in FIG. 17 for the position R, the signals d11, d12, e11, e12 , e13, e14 and f11 in FIG. 26 are identical to those in FIG. 17. In this case the difference in the clock pulse period (795 relative to 800 ns) has been left out of consideration as well as in the calculated time scale t.sub.0.....t.sub.40..... t.sub.80 = t.sub.0. In the position C the feedback with the signal e14' in FIG. 26 is effected at the instant t.sub.22 + 2t.sub.Q. In the signal d12 a pulse having a duration of 3t.sub.Q occurs. The result is that the dividers D and E now count two successive pulses more or skip them so that the original 42-to-1 divider becomes a 40-to-1 divider. It is of importance that in the signal e11 which may perform a trigger action on the flip-flop W for supplying the line blanking signal (T(W) = Q.sub.1 (E11) according to FIG. 15) a negatively directed edge active as a trigger edge occurs at the instant t.sub.22 + 1 t.sub.Q. This is in contrast with the trigger edge in the signal T + e11 at the instant t.sub.21 + 1 t.sub.Q in FIG. 22 for the position R. As is evident from FIG. 3, a line blanking pulse in the signal s.sub.HW is to be generated for the CCIR standard from t.sub.7 + 2t.sub.Q to t.sub.22 + 2t.sub.Q at a duration of fifteen clock pulse periods, while for both standards the line synchronizing pulse in the signals s.sub.HP, the equalizing pulse in the signal s.sub.EP and the raster serration in the signal s.sub.VS have the same number of clock pulse period at the same relative instants.

The signal e14 with trigger edges at the instants t.sub.1 and t.sub.41 determines the signal l11....l 16 of which the signal i13' provides the feedback to the flip-flop L11. The field frequency time scale calculated thereon is plotted for the signal l15 in which, as in FIG. 18, the instant of commencement is t.sub.100 ' and in which t.sub.101 ' is one fourth line period T.sub.H later etc. until t.sub.1350 ' = t.sub.100 '.

Analogous to FIG. 19, the result of the flip-flops ZZ, Y, X and the NAND gate Z is given in FIG. 27. Starting from the signals 115 and l16 and the signal m15 of the divider M (FIG. 18) shown in FIG. 26 in which at the instant t.sub.110 ' a negatively directed edge occurs, there simply follow the signals Q.sub.2 = zz, Q.sub.1 = y and z having a pulse duration of 2.5 T.sub.H, 7.5 T.sub.H and 2.5 T.sub.H, respectively.

For the flip-flop X with K = O FIG. 27 shows the signals T = l16, J = y, S.sub.2 = zz' and Q.sub.1 = x. The negatively directed pulse in the signal S.sub.2 = zz' at the instant t.sub.120 ' causes the flip-flop X which is in the stable state with Q.sub.1 = 1 at the condition K = O, J = O or 1, to change over so that at the instant t.sub.120 ' + 2t.sub.Q the logic O appears in the signal Q.sub.1 = x. The next negatively directed edge in the signal T = l16 occurs at the instant t.sub.150 ' = 1t.sub.Q in which for K = 0 and the logic O in the signal J = y the flip-flop X is not changed over. At the instant t.sub.150 '= 2t.sub.Q, the logic 1 occurs in the signal J = y so that the next negatively directed edge in the signal T = l16 at the instant t.sub.200 ' + 1t.sub.Q causes flip-flop X to change over to its stable state with Q.sub.1 = 1 for K = O and J = 1.

In the CCIR standard the signal i as described in FIG. 20 with reference to the RTMA standard is generated in substantially the same manner. In fact, until the instant t.sub.19 the signals d11, e14', f11 and e12 are identical in shape for both standards except for the difference incclock pulse period. Beyond the equalizing and field synchronizing period auxiliary pulses of line frequency and of double line frequency occurring therewithin during the 7.5 T.sub.H period with y = O are generated in the signal Q.sub.1 = i1.

The flip-flop W active as a blanking signal generator operates in the same manner for both standards, the only considerable difference being that a trigger edge occurs in the signal T = e11 at the instant t.sub.22 for the CCIR standard instead of at t.sub.21 for the RTMA standard.

Apart from the different number of various pulses in the line synchronizing signal Q.sub.1 = p generated by the flip-flop P, this operates in the same manner for both standards for generating the pulses s.sub.HP, s.sub.EP, s.sub.VP and s.sub.VS.

It is found in the pulse generator according to FIGS. 14 and 15 that there is only little to switch for use with the RTMA or CCIR standard. The switching of the dividend of the circuit of frequency dividers L, M, dividing to the field frequency is evident. The choice of the clock pulse frequency of the generator A being the same number of times the line frequency in both positions, with the example of 80 .nu..sub.H, obviates a switching of the dividend of the circuit of dividers D, E, F11 dividing to the line frequency. A pulse dipsplacement by switching in the divider D,E is found to be necessary so as to generate the line blanking pulses s.sub.HW of relatively different duration (14 relative to 15 clock pulses). A very simple pulse edge displacement is realized by forming the divider D, E, not as a 40-to-1 divider which is adaptable by means of switching, but in principle as a 42-to-1 divider the dividend of which is reduced to 40 by means of a switchable feedback while the desired pulse edge displacement is effected at the same time.

FIG. 17 shows the NTSC chrominance subcarrier gating signal s.sub.CR for the RTMA standard whose generation is described with reference to FIGS. 24 and 25. For a corresponding PAL chrominance subcarrier gating signal s.sub.CC for the CCIR standard, two differences are of importance. In the first place, the instant of commencement and the pulse duration are different, namely for the CCIR standard 5.6 .mu. after the leading edge of the line synchronizing pulse s.sub.HP and a duration of 10 periods of the chrominance subcarrier signal at a frequency of 4433618.75 Hz being 2.26 .mu.s. In the line time scale this corresponds to an instant of commencement of t.sub.9 + 2t.sub.Q (leading edge s.sub.HP ) plus 5.6/0.8 = 7 clock pulse periods, that is to say, up to t.sub.16 + 2t.sub.Q. At a final instant t.sub.19 the duration is (t.sub.19 -t.sub.16)- 2t.sub.Q = 3.times.0.8 .mu.s-.times. 2.times.70 ns = 2.26 .mu.s is required.

In the second place it is not sufficient, as in the RTMA standard, to discontinue the generation of the gating signal in the equalizing and field synchronizing period, but according to the PAL system a phase-shifted suppression of nine line periods is to be effected in a cycle of four fields. All this has already been described with reference to FIGS. 10......13.

For the explanation of the operation of the generator shown in FIG. 24 for generating the PAL chrominance subcarrier gating signal s.sub.CC reference is made to FIGS. 11, 12 and 13. As regards their operation the flip-flops FF.sub.12, FF.sub.13 and FF.sub.14 shown in FIG. 24 correspond to the flip-flops FF.sub.2, FF.sub.3 and FF.sub.4, respectively, of FIG. 10. The flip-flop FF.sub.16 shown in FIG. 24 and described with reference to generating the NTSC gating signal s.sub.CR will be used when generating the PAL gating signal s.sub.CC. To this end the input T of a flip-flop FF.sub.17 is connected to Q.sub.2 (FF.sub.16). The input J (FF.sub.17) is connected to Q.sub.1 (FF.sub.13). The flip-flops FF.sub.13 and FF.sub.14 are active as a blocking signal generator for generating a blocking pulse of nine line periods in the signal s.sub.C occuring phaseshifted in a cycle of four lines, while beyond this period there applies that Q.sub.1 (FF.sub.13) = s.sub.C = 1. The signal d12 of FIG. 26 is applied to the input S.sub.2 (FF.sub.17). The output Q.sub.2 (FF.sub.17) is connected to S.sub.2 (FF.sub.12). For the flip-flop FF.sub.12, J = 1, K = O and T (FF.sub.12) receives the signal e of FIG. 26. In the position C of the pulse generator according to FIGS. 14 and 15, the output Q.sub.1 (FF.sub.12) conveys the PAL chrominance subcarrier gating signal s.sub.CC.

For the stable state of the flip-flop FF.sub.17 with S.sub.2 = d12 = 0 or 1, there applies that Q.sub.2 = 1. For the stable state of the flip-flop FF.sub.12 in which J = 1, K = 0 and S.sub.2 = Q.sub.2 (FF.sub.17) = 1 while T = a there applies that Q.sub.1 = s.sub.Cc = 1.

In the position C of the pulse generator according to FIGS. 14 and 15 there apply the signals shown in FIG. 25 for the flip-flop FF.sub.16 in which for K = d12 the signal K.sub.C occurs. Since the signals, K.sub.R and K.sub.C are more or less identical in shape up to the instantt t.sub.20, the flip-flop FF.sub.16 generates a signal at the Q.sub.2 output which signal is the inverse of the shown signal Q.sub.1 = s.sub.CR. During each line period outside the equalizing and field synchronisation of 7.5 line period T.sub.H a negatively directed edge occurs once at the input T (FF.sub.17) at the instant t.sub.16. At the instant t.sub.16, S.sub.2 = d12 = 1 and J = K = 1 so that the flip-flop FF.sub.17 is changed over so that at t.sub.16 + 1t.sub.Q the logic O appears at the output Q.sub.2 (FF.sub.17) with the result that the flip-flop FF.sub.12 is also changed over through the connection S.sub.2 (FF.sub.12) = Q.sub.2 (FF.sub.17). in the signal S.sub.CC at the output q.sub.1 (FF.sub.12 1 the logic 0 has appeared at the instant t.sub.16 + 2t.sub.Q. A pulse having the logic 0 begins at the input S.sub.2 (FF.sub.17) in the signal d12 at the instant t.sub.18 so that flip-flop FF.sub.17 is changed back and conveys the logic 1 again at the Q.sub.2 output after the instant t.sub.18 + 1 t.sub.Q. The next negatively directed edge active as a trigger edge at the input T (FF.sub.12) at the instant t.sub.19 - 1t.sub.Q will cause the flip-flop FF.sub.12 to change over to the stable state associated with the condition J = 1, K = 0. At the, instant t.sub.19 the logic 1 has appeared at the output Q.sub.1 (FF.sub.12). The signal s.sub.CC has a gate pulse from t.sub.16 + 2t.sub.Q to t.sub.19 as is required.

If a pulse with the logic 0 is generated in the signal s.sub.C by the flip-flops FF.sub.13 and FF.sub.14 and if this pulse is supplied to the input J (FF.sub.17), the negatively directed edge will not cause the flip-flop FF.sub.17 to change over at the instant t.sub.16 at the T input. For the condition that J = 0, K = 1 and S.sub.2 = 0 or 1, the logic 1 is associated with the output Q.sub.2 (FF.sub.17) in the stable state.

In the flip-flop FF.sub.14 the signal i1 is applied to the T input and the signal f11 is applied to the interconnected J and K inputs. The operation of the flip-flop FF.sub.14 is analogous to that of the flip-flop FF.sub.4 of FIG. 10, the signals being given in FIG. 12. The flip-flop FF.sub.14 generates a square-wave signal ff.sub.14 and ff.sub.14 at the outputs Q.sub.1 and Q.sub.2 at half the line frequency, in which dependent on the field the edges are located near the instant t.sub.9 or t.sub.49 under the influence of the trailing edge of the pulses in the signal i1.

The application of the signals at the inputs of the flip-flop FF.sub.13 is as follows: J.sub.1 signal y, J.sub.2 signal ff.sub.14, J.sub.3 signal l14, K.sub.1 signal l13, K.sub.2 signal ff.sub.14 and K.sub.3 signal zz. The signals ff.sub.14 and ff.sub.14 may be interchanged as has been done in FIG. 10 which is changed for the sake of a simpler drawing.

In FIG. 13 the signals are given for the flip-flop FF.sub.3 which with small modifications also applies to the flip-flop FF.sub.13 of FIG. 24. A survey of the modifications is as follows: FF.sub.3 FF.sub.13 K.sub.1 = ff.sub.4 K.sub.2 = ff.sub.14 (or ff.sub.14) Edges at t.sub.13 and t.sub.53 Edges at t.sub.9 and t.sub.49 K.sub.2 = ff.sub.5 K.sub.3 = zz Pulse t.sub.110 to t.sub.130 Pulse t.sub.110 ' to t.sub.120 ' K.sub.3 = 12 K.sub.1 = 113 Edges at t.sub.8 and t.sub.40 Edges at t.sub.1 and t.sub.41 K K Pulses to t.sub.130 No pulses after t.sub.120 ' J.sub.2 = ff.sub.4 J.sub.2 = ff.sub.14 (or ff.sub.14) See K.sub.1 See K.sub.2 J.sub.3 = ff.sub.5 J.sub.3 = 114 Pulse t.sub.110 to t.sub.130 Pulse t.sub.110 ' to t.sub.140 ' J.sub.1 = y J.sub.1 = y Pulse t.sub.120 to t.sub.150 Pulse t.sub.120 ' to t.sub.150 ' Q.sub.1 = s.sub.C 3 Fields one 9T.sub.H -pulse from t.sub.13 or t.sub.53 t.sub.9 or t.sub.49 4th Field a longer pulse from t.sub.8 to t.sub.13 t.sub.1 to t.sub.9 13 8 9T.sub.H + T.sub.H = 9.16T.sub.H 9T.sub.H + T.sub.H = 9.1T.sub.H 80 80

The slightly longer duration of the pulse in the blocking signal s.sub.C in the fourth field is allowed.

The pulse generator shown in FIG. 24 or FIG. 10 is easily connectable to a known PAL coder. This coder is provided with a so-called PAL switch so as to achieve that the polarity of the (R-Y) vector is changed every other line. It follows from the PAL standard that the position of the PAL switch must be such that the phase of the first formed burst of the chrominance subcarriers after the PAL gating signal s.sub.C of 9 T.sub.H is 135.degree. relative to the +(B-Y) vector. To this end the switch must be driven at half the line frequency. Since in the signal s.sub.C the gating pulse of 9T.sub.H is determined by the signals ff.sub.14 and ff.sub.14 of half the line frequency, a uniform relationship between these signals is guaranteed. The signals ff.sub.14 and ff.sub.14 may be used with this guarantee for switching the PAL switch in a coder.