US 3,932,863 AGrant
Digital-to-Analog Converters
Issue Date:1976-01-13
•2 Claims
•2 Drawing Sheets
Abstract
A digital-to-analog converter utilizing a set of high-speed current switches each comprising a buffer transistor and a switching transistor interconnected with a common resistor in such a fashion that the buffer transistor in the normal "off" state supplies the common resistor with a current of predetermined magnitude to bias the switching transistor to cut-off; a control pulse coupled through an input diode cuts off the buffer transistor, the bias at the switching transistor is thereby eliminated, and the switching transistor immediately conducts. The magnitude of current supplied to a summing point by each switching transistor is fixed in accordance with a weighted relationship determined by the order of the binary bit represented by the respective transistor; for one group of switching transistors, the current levels are determined by current-dividing networks individual to each transistor; in a second group, the current levels are determined by a ladder network interconnecting the transistors to the summing point; in a third group, each transistor is arranged to conduct the correct amount of current by appropriate loading of its output circuit. Special means are provided for assuring smooth transitions between positive and negative outputs, and to compensate for the effects of ambient temperature variations.
Metadata
Assignee
- Analog Devices, Inc.
Inventor
- James J. Pastoriza
Application Information
Application Number:US 4862201
Filing Date:1974-07-05
Priority Date:1969-03-24
Art Unit:236
Classifications
IPC:
H03K 1304
Field of Search:
340347 DA
Patent Drawings (2 sheets)
Description
This invention relates to digital-to-analog converters. More particularly, this invention relates to such converters which are capable of high-speed conversion with stability and freedom from transient effects.
A wide variety of digital-to-analog converters have been provided for many purposes heretofore. Initially such converters used vacuum tubes, but as with most electronic devices, vacuum tubes have been replaced with later developed solid-state elements. Since the design criteria of solid-state elements are significantly different from vacuum tubes, this replacement process has presented a number of special problems. In addition, with the increasing speeds attainable by computers and other digital devices, there has been a corresponding demand for increased speed from digital-to-analog converters.
Accordingly, it is a principal object of the present invention to provide solid-state digital-to-analog converters with improved operating characteristics, particularly high-speed conversion capabilities together with reliable, accurate performance.
Other objects, aspects and advantages of the invention will in part be pointed out in, and in part apparent from, the following description considered together with the accompanying drawing in which FIGS. 1A and 1B together show a circuit diagram of one presently preferred embodiment of the invention.
Referring now to the upper portions of FIG. 1B, there is shown a conventional storage register 10 having a series of separate binary stages 12 (12A, etc.). Input leads 14 (14A, etc.) supply to the stages 12 the individual binary elements of a digital number to be converted to a corresponding analog signal level. These input leads may be connected to any digital source (not shown), such as a high-speed data processor.
The binary signals stored in the stages 12 are gated out essentially simultaneously by a strobe circuit 16 energized by conventional gate-generating means (not shown) producing periodic pulses of suitably high frequency. When the stages 12 are thus gated open, the stored binary signals are directed through respective coupling circuits comprising individual diodes 18 (18A, etc.). That is, each stage containing a stored binary bit produces a control pulse which passes through the corresponding coupling diode. This control pulse is of negative polarity, and is applied to the emitter 20 (20A, etc.) of a corresponding PNP buffer transistor 22 (22A, etc.) arranged so as normally to conduct current.
The bases 24 (24A, etc.) of all of the buffer transistors 22 are connected together to a power supply lead 26 providing a regulated bias voltage somewhat more positive than -15 volts. The emitters 20 of all of the buffer transistors are connected through respective resistors 28 (28A, etc.) to a second power supply lead 30 having a regulated voltage of about +15 volts. The collectors 32 (32A, etc.) of the buffer transistors are connected to corresponding NPN switching transistors 34 (34A, etc.) so as to control the output thereof in a manner to be described hereinbelow in detail.
The collector 32 of each buffer transistor 22 is connected to one end of a corresponding load resistor 36 (36A, etc.) forming part of the output circuit of the associated switching transistor 34. The remote ends of those load resistors are connected in common to a power supply lead 38 maintained at about -60 volts. When any buffer transistor is on, its output current flows through the associated load resistor 36, and the resulting voltage drop across this resistor causes the emitter 40 (40A, etc.) of the corresponding switching transistor to be biased to cut-off. Thus, no current will flow through a switching transistor while the associated buffer transistor is on.
When any buffer transistor 22 is cut off by a negative control pulse coupled through its input diode 18, the cut-off bias at the emitter 40 of the corresponding switching transistor 34 disappears, and that transistor therefore immediately conducts. The load circuit of each switching transistor is so arranged that when the transistor is turned on, the magnitude of its output current will be virtually equal to that of the current previously passing through the series resistor 36 from the associated buffer transistor 22. Thus, the operating conditions of the switching transistor will be changed but very little during the switching transition, e.g. the voltage of the emitter 40 may change by only a little more than 0.7 volts, the normal voltage drop across a conducting transistor. This small change in operating voltages tends to assure smooth and rapid switching.
The buffer transistors 22 serve the important function of substantially isolating the switching transistors 34 from the transient effects of the gating strobe control pulse. That is, such a control pulse, if applied directly to the switching transistor, would introduce relatively large momentary signal variations in the output circuit of the transistor, as a result, for example, of leakage capacitance coupling of the leading edge of the control pulse. Such transient effects introduce errors in the conversion operation, particularly as the conversion speed is increased to the point where there is insufficient time for the transient effects to settle out. The transient effects of a switching pulse are somewhat erratic, and are difficult to eliminate by conventional circuit arrangements.
The individual buffer transistors 22 significantly minimize the transient effects of capacitive coupling feed-through to the switch output. The result is a considerable improvement in accuracy of the conversion, especially at high speeds. In addition, the use of the buffer transistors makes it readily possible to strobe the converter with negative-going gate pulses, preferred in such logic circuitry.
The output currents of all of the first eight switching transistors 34A-34H are pre-adjusted to be of exactly the same magnitude (approximately 1 mil), by selection of the appropriate value for the associated load resistors 36A-36H. A portion of the output current of each conducting transistor is coupled through a lead 42 to the summing input terminal 44 (FIG. 1A) of an operational amplifier 46. The magnitude of this portion of current is fixed in accordance with a 2:1 weighting relationship to correspond to the order of the binary bit represented by the respective switching transistor. Specifically, the current contribution of the second transistor 34B is arranged to be one-half that of the first transistor 34A, the current contribution of the third transistor 34C is one-half that of the second 34B, and so forth.
The output of the first switching transistor 34 is connected directly to the summing terminal 44 of the operational amplifier 46, and thus this transistor contributes its entire output. The next three switching transistors 34B, 34C, and 34D are connected to the summing terminal by individual weighting networks comprising current dividers 48, 50, and 52. The preferred form of divider consists of two series-connected resistors the common junction of which is connected to the collector electrode 54 of the associated switching transistor, and the remote terminals of which are connected respectively to ground and the summing input terminal 44 of the operational amplifier 46. Thus, the amount of current contributed by any one of these latter three switching transistors 34B, 34C and 34D is determined by the ratio of the two resistors in the corresponding current-divider network 48, 50 or 52, in such a manner as to provide the required 2:1 ratio from one to the next.
The next four output transistors 34E-34H form a second discrete set, all coupled to the summing input terminal 44 of the operational amplifier 46 by means of a two-to-one ladder network 56 consisting of a series of four cascaded identical stages 58, 60, 62 and 64. The intersection points 66, 68, 70 between the separate stages are connected respectively to the transistor collector electrodes 54E, 54F and 54G, and the right-hand end terminal 72 (serving as the input terminal for the ladder network) is connected to collector electrode 54H. In this ladder network, the ohmic resistance of each series resistance 74 is one-half that of the associated shunt resistance 76. Thus, visualizing the signal flow as proceeding from right to left, each stage of the ladder network provides a 2:1 attenuation of any current supplied thereto, either from the associated switching transistor 34, or from the preceding (right-hand) stage of the ladder network.
Although this ladder network 50 does introduce some distributed capacitance effects, and permits some interaction between the functioning of the associated switching transistors 34, these effects produce relatively small consequences in the overall conversion accuracy because the bits of data involved are several orders down from the most significant bit of the complete digital number. Moreover, such adverse effects are compensated for, at least to some extent, by arranging the switching transistors to produce the same magnitude of current output. This equal-current arrangement tends to minimize instability and other error effects.
The load resistors 36I-36M of the last set of five switching transistors 34I-34M are so proportioned relative to one another as to provide the desired two-to-one ratio in current flow through the respective transistors. The load resistors 28I-28M of the corresponding buffer transistors 22I-22M are similarly proportioned. That is, each resistor in the sequence has a total ohmic resistance of approximately twice that of the preceding resistor of the sequence. Thus, the magnitude of the current supplied by each switching transistor 34I-34M is one-half that of the preceding transistor, e.i. the transistor to the left, as seen in the drawing.
The collector electrodes (54I-54M) of all five of this third set of switching transistors 34I-34M are connected together to the input terminal 72 of the ladder network 56. Any one of the transistors which is gated on will thus supply a corresponding weighted current contribution through the ladder network to the summing input terminal 41 of the amplifier 46. Although the use of currents of different magnitude in each of the switching transistors 34I-34M introduces some asymmetries in the conversion operation, these asymmetries do not have any important effect on the final result because the five transistors of this third set provide digital bits corresponding to the lowest orders of the digital number, i.e. the five least significant bits of the group. The direct connection of this third set provides desirable economies of construction without important performance limitations.
For some applications, it is necessary to provide a sign-change capability, i.e. so as to develop either positive or negative analog outputs corresponding to positive or negative digital inputs. Referring to the lower portion of FIG. 1A, such a capability can be provided by coupling the output of the amplifier 46 to an inverting amplifier 80, and by employing a selector switch 82 having two sections 82A, 82B to select either the direct output or the inverted output. The switch 82 is operated by a conventional switch driver 84 controlled by an input lead 86 to which is directed a sign bit, i.e. a binary bit indicating whether the number to be converted is positive or negative. The sign bit is gated by a strobe circuit (not shown) synchronized with the converter strobe. When so gated, the driver 84 opens either switch section 82A or switch section 82B, but not both at the same time. The selected analog signal is coupled to an output amplifier 66 which provides the final analog output signal of the converter.
Since it is not readily possible to assure exact synchronism between the operation of the switch 82 and the strobing of the storage register 10, transient errors may be developed in the converter output during the transition between negative and positive outputs. The problem cannot be solved simply by arranging the circuit so that the sign switch 82 is always actuated slightly before or slightly after strobing of the storage register, because a momentary error effect such as an overshoot can result under either circumstance, depending upon the beginning and ending voltages of the analog output. In accordance with a further aspect of the present invention, this problem has been solved by a special arrangement for insuring that the analog output signal, whenever a sign change is to be made, will first be brought to zero potential. Since every sign change requires the analog voltage to pass through zero, automatically shifting the voltage to zero whenever a sign change is to take place insures that the output will not vary in the wrong direction at the outset of a change. Holding the output on zero until all of the switching has been completed prevents overshooting of the final voltage.
In more detail, the converter includes (referring now to the upper left-hand corner of FIG. 1A) a sign change detector 90 which in the present embodiment includes a conventional flip-flop 92 arranged to receive the sign bit as the controlling input. The set and reset contours of the flip-flop are coupled through respective derivative circuits 96, 98 and isolating diodes 100, 102 to a common load resistor 104. Thus, whenever there is a change of sign (where the sign bit changes from "zero" to "one" or vice-versa), a sharp positive spike will be developed at the load resistor 104. This spike momentarily turns on a transistor switch 106 which, in turn, momentarily disables a transistor 108 serving to establish the bias voltage for the power supply lead 26.
Power supply lead 26 thereupon goes negative and holds the buffer transistors 22 on, producing a flow of current through all of the resistors 36 for a brief period. This current flow causes all of the switching transistors 34 to be turned off momentarily, thereby making the output voltage of amplifiers 46 and 80 to be held momentarily at zero. Thus, even though the sign-change switch 82 is not exactly synchronized with the gating of the register 10, the converter output will momentarily be shifted to zero during a sign change.
After the spike has subsided at the input to transistor 106, the buffer transistors 22 all are returned to normal operating conditions, and the strobed control pulses fed to these transistors from register 10 will activate the switching transistors 34 in a pattern representing the stored digital number. Thus, the output of the amplifier 88 will be shifted to the proper level, and transient errors during the sign change transition avoided.
Another source of error is changes in ambient temperature, which alter the operating characteristics of the switching transistors 34, and tend to vary the magnitude of current produced thereby. In accordance with a still further aspect of the invention, means are provided to minimize such effects of ambient temperature. More specifically, all of the bases 110 (110A, etc.) of the switching transistors 34 are connected to a bias lead 112 the voltage of which is regulated so as to maintain the current through the switching transistors substantially constant with changes in temperature.
The voltage of the bias lead 112 is primarily determined by a transistor 114 in series with a resistor 116. Bias lead 112 also is connected to the base 120 of a control transistor 122 matched to the first switching transistor 34A, particularly in having a "beta" which tracks the corresponding parameter of transistor 34A with changes in temperature. The emitter 124 of control transistor 122 is connected through a load resistor 126 to the power supply lead 38, and the collector 128 of this transistor is connected through a resistive network 130 to a positive reference voltage terminal 132. The circuit elements are so selected so as to produce a predetermined flow of current through the resistive network 130 and the control transistor 122, and resulting in a zero potential at a control point 134 between the resistive network 130 and the control transistor. The magnitude of the current through transistor 122 is set to equal the flow of current through the switching transistor 34A when the latter has been turned on.
If there is a change in ambient temperature, the result typically will be a change in operating characteristics of the switching transistor 34A, so as to alter the normal current flow therethrough. By positioning the control transistor 122 physically adjacent the switching transistor 34A, the same temperature effect will be experienced by the control transistor. The change of current produced by a change in temperature is detected by an operational amplifier 136 having one input terminal connected to control point 134, and its other input terminal connected through a resistor 138 to ground. The output of this amplifier 136 is connected through a resistor 140 and an isolating diode 142 to power supply lead 38.
When there is a change in the current supplied to the amplifier 136 from control point 134, there will be a corresponding change in the amount of current drawn by this amplifier from the power supply lead 38. Since this power supply lead is connected through a resistor 150 to the power supply terminal 152, the change in current drawn by amplifier 134 will cause a corresponding change in the voltage of power supply lead 38. Thus, the amplifier 134 provides an amplified negative feedback action which automatically alters the voltage of lead 38 in such a way as to maintain constant the current flow through the control transistor 122. Since transistor 122 is matched to switching transistor 34A, the change in potential of power supply lead 38 will have a similar effect on the functioning of this switching transistor, i.e. it will compensate for the change in ambient temperature of transistor 34A, and assure that the current through that transistor is maintained effectively invariant with changes in temperature. Moreover, this result can be achieved with a power supply 152 of relatively modest complexity and cost, because the power supply need not be closely regulated internally.
The same controlling influence tends to maintain constant the current through the other switching transistors 34B, etc. However, as a practical matter these latter transistors need not be so identically matched in characteristics to the first transistor 34A, because they represent binary information of progressively less significance to the ultimate analog output voltage.
Typical values and types of elements used in a preferred embodiment of the invention as described above are as follows:
It will be apparent from the foregoing description that various changes can be made to the preferred embodiment without departing from the spirit of the invention. For example, the values of elements herein disclosed should not be construed as limiting. Other changes suited for particular applications will be apparent to those skilled in this art.
Claims
I claim:
1. A digital-to-analog converter comprising a first set of individually-activatable transistor current sources arranged to conduct currents of equal magnitude producing equal current densities in the transistors; said transistors each having collector, emitter and base electrodes; a plurality of equal current-setting resistors each connected between the emitter of a respective transistor and a common power supply line; means to maintain the bases of said transistors at a substantially constant potential, whereby when said transistors are activated they produce said equal current through the collector circuits of said transistors; a second set of individually-activatable transistor current sources for controlling said first set of current sources; said second set of transistors each having collector, emitter and base electrodes; means connecting the collectors of said second set of transistors respectively to the emitters of said first set of transistors to provide for controlling the flow of current through the corresponding current-setting resistor to control the activation of the associated one of said first set of transistor current sources; means connected to said second set of transistors to control the individual actuation thereof in accordance with an input binary number thereby to control the flow of current from each transistor collector through the corresponding one of said current setting resistors so as to control the activation of the associated one of said first set of transistor current sources; a current summing point to which a plurality of separate currents can be directed to produce a combined output current corresponding to the sum of the separate currents; a plurality of attenuation networks each having an input circuit and an output circuit and arranged, when supplied with an input current, to provide an output current the magnitude of which is a predetermined fraction of the input current; said attenuation networks having differing attenuations in accordance with a predetermined weighting pattern, such that if the same current is supplied to said input circuits, the corresponding output currents from said networks will differ in accordance with said weighting pattern; means connecting each of said input circuits directly to the collector circuit of a respective one of said first set of transistor current sources to provide equal input currents thereto from the activated current sources; said attenuation networks being arranged to present equal impedances to each of said collector circuits in said first set of transistor current sources; and means connecting all of said attenuation network output circuits together and to said current summing point, whereby to supply thereto currents of differing magnitudes in accordance with said predetermined weighting pattern.
2. A digital-to-analog converter comprising first and second sets of individually-activatable transistor current sources arranged to conduct currents of equal magnitude producing equal current densities in the transistors; said transistors each having collector, emitter and base electrodes; a plurality of equal current-setting resistors each connected between the emitter of a respective transistor and a common power supply line; means to maintain the bases of said transistors at a substantially constant potential, whereby to produce said equal currents from the collectors of said transistors effectively independently of the loads placed on the outputs of said transistors; an operational amplifier including a current summing point to which a plurality of separate currents can be directed to produce a combined output current corresponding to the sum of the separate currents; a plurality of attenuation networks each having an input circuit and an output circuit and arranged, when supplied with an input current, to provide an output current the magnitude of which is a predetermined fraction of the input current; said attenuation networks having differing attenuations in accordance with a predetermined weighting pattern, such that if the same current is supplied to all of said input circuits, the corresponding output current from said networks will differ in accordance with said weighting pattern; first circuit means connecting each of said input circuits directly to a respective current source of said first set to provide equal currents thereto from the activated current sources; second circuit means connecting all of said output circuits together and to said current summing point, whereby to supply thereto currents of differing magnitudes in accordance with said predetermined weighting pattern; a ladder network comprising a set of equal-resistance series-connected resistors and a set of equal-resistance shunt-resistors connected between the junctions of said series resistors and a common reference point, said series and shunt resistors having ohmic resistances of predetermined ratio; third circuit means connecting said ladder network junctions respectively to current sources of said second set to provide equal currents to said junctions from the activated current source; means connecting one end of said ladder network to said current summing point so that the currents contributed to said summing point by the separate current sources of said second set differe in accordance with the degree of attenuation developed between the respective junction and said one ladder network end; and means to selectively activate said current sources in response to a digital input signal.
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