Period Meter for Reactors

The reactor period, T, is the time required for the power level of a nuclear reactor to increase by a factor e (the base of natural logarithms). When the reactor period becomes too short, i.e. the power level is increasing too quickly, a reactor scram should be initiated. A log N amplifier type reactor period meter for measuring T includes an ionization chamber whose output current I is a measure of the neutron flux from the reactor and therefore the current I is proportional to the reactor power level. The output of the ionization chamber is applied to a logarithmic or log N amplifier whose output V(t) will be proportional to the log of the reactor power level, i.e.

Where V.sub.o is the log N amplifier output voltage at some reference time, A is the open loop gain of the amplifier, .gamma. is the voltage change across the logarithmic element or equivalent resistance of the log N amplifier due to each factor e increase in current through the logarithmic element, and I.sub.o is the ionization chamber output current at the reference time. The reactor period T can be obtained by differentiating equation (1) with respect to time,

Prior art period meters have applied the V(t) signal to a conventional analog differentiator element to obtain a dV( t)/dt signal representative of reactor period. When the dV( t)/dt signal exceeds a particular value, indicating a low T, a scram signal is generated by a scram generator. It is characteristic of this system to tend to be more vulnerable to electrical and statistical noise when the V( t) signal is small, which corresponds to low reactor power levels. This noise can be of such amplitude as to induce the scram generator to develop a spurious scram signal, causing unnecessary reactor shutdown.

It is therefore an object of this invention to provide an improved reactor period meter.

Another object of this invention is to provide a reactor period meter with reduced probability of spurious reactor scrams.

An improved log N type nuclear reactor period meter is provided. With the reactor at low power, a sampling circuit which measures finite changes in the V(t) signal over predetermined time intervals is provided, giving .DELTA. V/.DELTA. t, an arithmetic approximation of the slope of the V(t) signal, which is used to determine the reactor period. With the reactor at high power, conventional analog differentiation of the V(t) signal from a log N amplifier provides the dV(t)/dt reactor period output. With either of the reactor period signals, dV(t)/dt or .DELTA. V/.DELTA. t, above a predetermined value, a scram signal generator develops a reactor scram signal.

The drawing is a block diagram of the improved reactor period meter.

Referring to the drawing, there is shown an improved reactor period meter. An ionization chamber 10, such as a neutron sensitive ionization chamber used in the current mode, positioned in the reactor (not shown) develops an output signal I which is proportional to the neutron flux density of the reactor and which is therefore nominally proportional to the reactor power level. The output signal I is fed to a logarithmic amplifier 12 whose output V(t) is of the form of equation (1) as previously described.

To obtain a signal representative of reactor period, it is possible to differentiate V(t) with respect to time, i.e. as shown by equation (2) above. It has been observed that the reactor period output signal developed by applying the V(t) signal to a conventional analog differentiator is very noisy with I at a relatively low value, even though the V(t) signal is well behaved at both high and low signal levels. Thus, the conventional analog differentiator decreases the signal-to-noise ratio at low reactor power levels. Utilization of the well behaved V(t) signal to generate period information at low power will tend to reduce noise-induced scrams.

When the reactor power level is rising on an asymptotic period, the V(t) signal of equation (1) is linear so the reactor period can be obtained by determining the linear slope between any two points along the V(t) signal line on either side of the particular point. This may be done by periodically establishing initial conditions, i.e. V(0) and t = 0 and subsequently monitoring the finite changes in the V(t) signal over a predetermined time interval. A period scram level can be established by selecting an allowable increase .DELTA. V of V(t) over some prescribed time interval t = .delta.. Since the change in V(t) is the significant parameter because it is related to the increase in reactor power level which will occur before scram action is initiated, the change of its value .DELTA. V with reference to V(0) is selected first. The value of .delta. is then chosen to achieve a scram when the reactor period decreases to some prescribed value T.sub.i.

In particular, referring to the drawing there is shown a circuit in which the conventional analog differentiator scram signal is developed by dV/dt scram circuit 13 which is limited to developing scram signals at high power levels and in which low power scram signals are developed by .DELTA.V/dt circuit 20 which monitors finite changes in the V(t) signal over a predetermined time interval. The high power level scram signal generation is developed by dV/dt scram circuit 13. The V(t) signal developed by amplifier 12 is fed to a conventional differentiator 14 where it is differentiated with respect to time to produce the dV/dt reactor period signal to be utilized at high power. The output of differentiator 14 is applied to comparator circuit 15. A comparator circuit is a logic device which compares the value of a first input signal to that of a second input signal. If it is a "greater than" comparator circuit, it generates a positive logical output signal with the value of the first signal greater than the value of the second and if it is a "lesser than" comparator circuit, it generates a positive logical output signal with the value of the first signal less than the value of the second. In all other cases the output of the circuit is zero. Comparator 15 is a "greater than" circuit intended to determine if the reactor period T is below a predetermined value. Since according to equation (2), T is inversely proportional to dV/dt, comparator 15 generates an output having a positive logical state with the dV/dt signal greater than the value of the output of period trip setting 16 which is also applied to comparator circuit 15. A setting circuit, such as period trip setting circuit 16 is an element whose output signal has a predetermined programmable or settable value. The programmed value of period trip setting circuit 16 is the predetermined value of dV/dt at which a scram signal should be generated. Note that while the disclosure herein deal with positive logic circuitry, of course, to those skilled in the art, negative or other types of logic circuitry are equally applicable.

As the positive signal developed by comparator 15 is developed with undesirable frequency at low reactor power due to the noise in the dV/dt signal, means are provided to limit the high reactor power level scramming of the reactor in response to the positive state of comparator 15. The V(t) signal from amplifier 12 is also fed to a "greater than" comparator 17 which compares the value of V(t), which is proportional to reactor power level, to the output of reference power level setting 18. The value of the output of power level setting 18 is programmed to a particular value of V(t) corresponding to a particular power level so that comparator circuit 17 generates an output of positive logical state only when the particular reactor power level is exceeded. The output signals from comparator circuits 15 and 17 are applied to AND circuit 19 which will develop a positive logical output only when both inputs are in a positive logical state simultaneously. Thus, AND circuit 19 will allow the scram signal developed by comparator circuit 15 to be passed on only when comparator circuit 17 is simultaneously indicating that the reactor power level is above a particular value. The particular value of the reactor power level programmed into power level setting 18 is determined by the noise condition of the dV/dt signal from differentiator 14. It has been observed that the range of programmed values for power level setting 18 corresponds with the value of the I signal from ionization chamber 20 typically being between 10.sup.-.sup.7 amps and 10.sup.-.sup.4 amps. Best results were obtained with the programmed value of the reactor power level setting 18 corresponding to a value of the I signal of 10.sup.-.sup.5 amps.

Generation of a reactor scram with reduced noise induced scram is provided by .DELTA.V/.DELTA.t circuit 20, which utilizes the V(t) signal, less noisy at low power levels than the dV/dt signal, to monitor changes in the V(t) signal over a predetermined time interval. Low power scram signal detection, i.e. below the reactor power level trip setting of reference power level setting 18 is developed by .DELTA. V/.DELTA. t circuit 20. Circuit 20 includes two separate sampling circuits to monitor the finite changes, .DELTA. V, in the value of V(t) over continuously repeated predetermined time intervals of t = .delta.. The repeated time intervals covered by the two circuits are made to overlap each other so that one sampling circuit is monitoring V(t) for a time period which ends in the middle of the time period monitored by the other circuit. This is done so that there is no dead time while the sampling circuits rezero themselves at the end of each predetermined time period. In all other aspects these two circuits are identical. They each include gate circuits 22 and 32 to which the V(t) signal is fed. Gate circuits 22 and 32 are parts of sample and hold circuits which apply the value of V(t) to analog memories 24 and 34, respectively, whenever they receive a gate pulse from gate pulse sources 23 and 33, respectively. Gate pulse sources 23 and 33 are devices which continuously generate pulses at predetermined programmable time intervals of .delta. and are coupled together so that the timing of their outputs may be synchronized. Thus, every time interval .delta., gate circuit 22 is opened and the existing value of V(t) at the instant is stored in analog memory 24 as an updated value of V(0). The same procedure follows for gate circuit 32 and analog memory 34 over an overlapping time interval. Low power period trip settings 25 and 35 develop a programmed output whose value is .gamma..delta./T.sub.1, where .gamma. is the constant associated with the logarithmic element of log N amplifier 12 as described in equation (1), T.sub.1 is the reactor period at which a scram should be generated and .delta. is the time interval associated with the reactor period T.sub.1 for a given finite change .DELTA.V in V(t). The output of period trip settings 25 and 35 and of analog memories 24 and 35 are constantly applied to adding amplifiers 27 and 28, respectively, whose outputs will therefore be V(0) + .gamma..delta./T.sub.1 with V(0) in each sampling circuit being continually updated each time interval .delta.. The V(t) signal is applied to comparators 29 and 39, both being "greater than" comparators. Comparators 29 and 39 constantly compare the value of V(t) with the output of adding amplifiers 27 and 37, respectively, and each generates a positive logic state of scram signal with V(t) greater than V(0) + .gamma..delta./T.sub.1. Note that the value of the outputs of adding amplifiers 27 and 37 is constantly changed each time interval .delta..

The value of .delta. is arbitrary being defined by .delta.V for a given T.sub.1 and vice versa. Of course, the longer .delta., the greater the finite change in V(t) from V(0) and the shorter .delta. selected the smaller the finite change. For T.sub.1 .apprxeq. 10 sec, typical values for .delta. for acceptable results are within the range of 1-20 sec.

The outputs of comparator circuits 29 and 39 which have low noise induced positive states at low power, and AND circuit 26 19, which is limited to being in the positive state only at high power, all of which are either in a scram or no scram condition are applied to OR circuit 40. If any of comparator circuits 29 and 39 or AND circuit 19 indicate a scram condition, then OR circuit 40 develops an output indicating scram condition and the reactor is scrammed by scram generator 42.

Note that the .DELTA.V/.DELTA.t circuit 20 is used over the entire spectrum of reactor power levels while the dV/dt circuit 13 is used only at high power levels. This is done to provide the safety factor of redundancy and increases response time since in certain rare instances at high power the .DELTA.V/t circuit detects a scram faster than the dV/dt circuit.

Further, it is important to note that the frequency response of the .DELTA.V(t)/.DELTA.t system can be significantly improved over the conventional dV/dt system because the signal-to-noise ratio associated with the .DELTA.V(t)/.DELTA.t signal is considerably greater than that associated with the dV/dt signal developed by a conventional differentiator. Also, the power level increase factor as well as the transient response may be adjusted to minimize the effects of noise or to otherwise optimize the V(t) circuit performance. This is an additional parameter to govern the performance of the circuit not otherwise available in the conventional analog differentiator circuit.