3D CHIP PACKAGE BASED ON THROUGH-SILICON-VIA INTERCONNECTION ELEVATOR

[0001] This application is a continuation of application Ser. No. 18/129,840, filed Sep. 24, 2022, now pending, which claims priority benefits from Ser. No. 17/026,186, filed Sep. 19, 2020, now U.S. Pat. No. 11,637,056, which claims priority benefits from U.S. provisional application No. 62/903,655, filed on Sep. 20, 2019 and entitled “3D CHIP PACKAGE BASED ON THROUGH-SILICON-VIA INTERCONNECTION ELEVATOR”, U.S. provisional application No. 62/964,627, filed on Jan. 22, 2020 and entitled “3D chiplet system-in-a-package using vertical-through-via connector”, U.S. provisional application No. 62/983,634, filed on Feb. 29, 2020 and entitled “A Non-volatile Programmable Logic Device Based On Multichip Package”, U.S. provisional application No. 63/012,072, filed on Apr. 17, 2020 and entitled “VERTICAL INTERCONNECT ELEVATOR BASED ON THROUGH SILICON VIAS” and U.S. provisional application No. 63/023,235, filed on May 11, 2020 and entitled “3D Chip Package based on Through-Silicon-Via Interconnection Elevator”. The present application incorporates the foregoing disclosures herein by reference.

[0002] The present invention relates to a 3D IC chip packaging technology, and more specifically relates to a 3D single-chip or multi-chip package based on a vertical interconnect elevator (VIE) chip or component including through-silicon-via interconnect elevators (TSVIE), through-glass-via interconnect elevators (TGVIE) or through-polymer-via interconnect elevators (TPVIE).

[0003] One aspect of the disclosure provides a Vertical Interconnect Elevator (VIE) chip or component including a Through-Silicon-Via Interconnect Elevator (TSVIE), Through-Glass-Via Interconnect Elevator (TGVIE) or Through-Polymer-Via Interconnect Elevator (TPVIE). The VIE chip or component is for use in a chip package, wherein the chip package may be (i) a single-chip package (comprising only one semiconductor IC chip), (ii) single-COC package (chip-on-chip components or packages) or (iii) a multichip package (comprising a plurality of semiconductor IC chips or a plurality of COCs). The formation and structures of the COCs package will be described and specified below. The chip package may comprise one or a plurality of semiconductor IC chips (or COCs) and one or a plurality of VIE chips or components, wherein one or the plurality of semiconductor IC chips (or COCs) and one or the plurality of VIE chips or components are disposed on a same horizontal plane. The chip package comprising the VIE chips or components provides vertical interconnection for connecting the circuits at the bottom side (frontside) of the chip package to the top side (backside) of the chip package, wherein the through vias in the VIE chips or components are used for signal, clock, power and/or ground interconnection. The one or the plurality of semiconductor IC chips may not comprise any TSV. Alternatively, the one or the plurality of semiconductor IC chips may comprise TSVs, used for signal, clock, power supply (Vcc) and/or ground reference (Vss) interconnection. The VIE chip or component may comprise only passive elements and no active devices (for example, transistors). The standard wafer for the VIE chips is diced or sawed to form the separated VIE chips. The VIE chip or component may be manufactured by the packaging manufacturing companies or facilities without front-end of line (for fabrication of circuits including transistors) manufacturing capability. The chip package comprises contact copper pads or pillars, or solder bumps at the frontside (i.e., the side of the semiconductor IC chip or chips with transistors is facing) of the chip package and contact copper or nickel pads, copper pillars or solder bumps at the backside side (i.e., the side of the semiconductor IC chip or chips without transistors is facing) of the chip package. The contact copper pads or pillars, or solder bumps at the frontside of the chip package may be coupled or connected to the contact copper or nickel pads, copper pillars or solder bumps at the backside side of the chip package through the through vias of the VIE chips or components, wherein the through vias of the VIE chips or components are used for signal, clock, power and/or ground interconnection. The transistors or circuits of the semiconductor IC chip or chips may be coupled or connected to the external circuits outside of the frontside and/or the backside of the chip package. The transistors or circuits of the semiconductor IC chip or chips may be coupled or connected to the external circuits outside of the backside of the chip package, through vias of the VIE chips or components and the contact copper or nickel pads, copper pillars or solder bumps at the backside side of the chip package, wherein the through vias of the VIE chips or components are used for signal, clock, power supply (Vcc) and/or ground reference (Vss) interconnection. The locations or layout in a horizontal plane of contact copper pads or pillars, or solder bumps at the frontside of the chip package may be the same as that of the contact copper or nickel pads, copper pillars or solder bumps at the backside side of the chip package. In this case, the chip package is a chiplet or package in a standard format. The standard format of the chiplets or packages provides capability for stacking them vertically in a stacked 3D chip package. A second chip package may be stacked on the top of a first chip package using Package-On-Package (POP) assembly methods to form the 3D stacked chip package, wherein the first and second chip packages may be the chip packages as described and specified above.

[0004] Another aspect of the disclosure provides a standard common wafer for the VIE chips or components, as described and specified above. The VIE chip or component is for use in the chip package comprising (i) a single-chip package (comprising only one semiconductor IC chip), (ii) single-COC package or (iii) a multichip package (comprising a plurality of semiconductor IC chips or a plurality of COCs), as described above and to be described and specified below. The standard common wafers for the VIE chips or components may have a fixed pattern of design and layout for locations of the TSVs, and may be diced or separated into VIE chips or components each with different dimensions or shapes and different numbers of TSVs. In some applications, the aspect ratio of length to width for a diced or separated VIE chip or component may be between 2 and 10, between 4 and 10 or between 2 and 40. Assume that the width of a scribe line is W_sb, the space or separation between the scribe line and the TSV at the edge or boundary of the VIE chip or component is W_sbt, and the space or separation between two neighboring TSVs is W_sptsv. W_sptsv is smaller than 50, 40 or 30 micrometers. In a case, if W_sptsv is greater than W_sb+2W_sbt, the standard common wafer is designed and layout with TSVs populated regularly in the whole wafer with a fixed pitch and separation (space W_sptsv) between two neighboring TSVs in x-direction and y-direction, respectively. The standard common VIE wafer may be cut or diced, through the space between two neighboring TSVs, to form separated or diced VIE chips or components each in a square or rectangular shape and with any dimension, and the separated or diced VIE chip or component may comprise any number of TSVs. In this case, in each separated or diced VIE chip or component, W_sbt is smaller than W_sptsv. For example, a standard common VIE wafer with a given TSV layout may be cut or diced into separated or diced VIE chips or components each with an array of M1 by N1 (M1×N1) TSVs, M1 and N1 are positive integers, and wherein N1<M1, 1<=N1<=15, and 50<=M1<=500; or N1<M1, 1<=N1<=10, and 30<=M1<=200. For example, a separated or diced VIE chip or component may comprise an array of 100 by 5, 200 by 5, or 300 by 10 TSVs. In another case, if W_sptsv is equal to or smaller than W_sb+2W_sbt, the standard common wafer is designed and layout with two alternatives: (1) with islands or regions of TSV arrays populated regularly in the whole wafer with reserved scribe lines. Each of the reserved scribe line has a fixed space or separation W_spild between two neighboring islands or regions of TSV arrays (that is between two neighboring TSVs across the reserved scribe line) in x-direction and y-direction, respectively, that is, there are two different separation spaces, W_spild and W_sptsv, between two neighboring TSVs in a separated or diced VIE chip or component. W_spild is greater than W_sptsv. As an example, W_spild is greater than 50, 40 or 30 micrometers, and W_sptsv is smaller than 50, 40 or 30 micrometers. The reserved scribe line between two neighboring islands or regions of TSV arrays may be used as a scribe line for dicing and cutting. The standard common VIE wafer may be cut or diced, through the reserved scribe lines, to form separated or diced VIE chips or components in square or rectangular shape and with various dimensions. In this case, the separated or diced chip or component comprises M×N islands or regions of TSV arrays (wherein M and N are positive integers, wherein N<=M, 1<=N<=10, and 1<=M<=20) with the fixed space or separation W_spild between two neighboring islands or regions of TSV arrays, wherein, for example, W_spild is greater than 50, 40 or 30 micrometers, and W_sptsv is smaller than 50, 40 or 30 micrometers. As example, the standard common VIE wafer with a given design and layout of islands or regions of TSV arrays may be cut or diced into a plurality of VIE chips or components, wherein each separated or diced VIE chip or component comprises one or a plurality of islands or regions of TSV arrays, for example, 3 by 1, 6 by 1, 4 by 2, 8 by 2, or 10 by 3 islands or regions of TSV arrays. If the separated or diced VIE chip or component comprises a plurality of (more than one) islands or regions of TSV arrays, there is the reserved scribe line between two neighboring islands or regions of TSV arrays therein. The diced or separated VIE chip or component may comprise repetitive islands or regions of TSV arrays with each island or region of TSV arrays comprising M2 by N2 TSVs, M2 and N2 are positive integers, and wherein N2<M2, 1<=N2<=15, and 25<=M2<=250; or N2<M2, 1<=N2<=10, and 15<=M2<=100. For example, a separated or diced VIE chip or component comprises repetitive islands or regions of TSV arrays with each island or region of TSV arrays comprising an array of 50 by 5, 150 by 5, 150 by 10, or 250 by 10 TSVs; (2) with TSVs populated regularly in the whole wafer with a fixed pitch and separation (space W_sptsv) between two neighboring TSVs in x-direction and y-direction, respectively. The standard common VIE wafer may be cut or diced through the TSVs to form separated or diced VIE chips or components in a square or rectangular shape and with any dimension, and the separated or diced VIE chip or component may comprise any number of TSVs. In this case, for each separated or diced VIE chip or component, W_sbt may be equal to or greater than zero and is smaller than W_sptsv, and W_sptsv is smaller than 50, 40 or 30 micrometers.

[0005] The above specifications for TSVs in the silicon substrate of the VIE chip or component (TSVIE) are applied to the specifications for TGVs in the glass substrate of the VIE chip or component (TGVIE).

[0006] Another aspect of the disclosure provides a standard common wafer for the VIE chips or components. The VIE chip or component is for use in the chip package comprising (i) a single-chip package (comprising only one semiconductor IC chip), (ii) single-COC package or (iii) a multichip package (comprising a plurality of semiconductor IC chips or a plurality of COCs), as described above and to be described and specified below. The standard common wafers for the VIE chips or components may have a fixed pattern of design and layout for locations of the micro metal pads or bumps on the TSVs, and may be diced or separated into VIE chips or components each with different dimensions or shapes and different numbers of the micro metal pads or bumps on the TSVs. In some applications, the aspect ratio of length to width for a deiced or separated VIE chip or component may be between 2 and 10, between 4 and 10 or between 2 and 40. Assume that the width of a scribe line is W_sb, the space or separation between the scribe line and the micro metal pad or bump on the TSV at the edge or boundary of the VIE chip is WB_sbt, and the space or separation between two neighboring micro metal pads or bumps on the TSVs is WB_sptsv. WB_sptsv is smaller than 50, 40 or 30 micrometers. In a case, if WB_sptsv is greater than W_sb+2WB_sbt, the standard common wafer is designed and layout with micro metal pads or bumps on the TSVs populated regularly in the whole wafer with a fixed pitch and separation (space WB_sptsv) between two neighboring micro metal pads or bumps on the TSVs in x-direction and y-direction, respectively. The standard common VIE wafer may be cut or diced, through the space between two neighboring micro metal pads or bumps on the TSVs, to form a separated or diced VIE chip or component in a square or rectangular shape and with any dimension, and the separated or diced VIE chip may comprise any number of micro metal pads or bumps on the TSVs. In this case, in each separated or diced VIE chip or component, the distance between the edge of the diced VIE chip or component to the nearest micro metal pad or bump on the TSV (WB_sbt) is smaller than WB_sptsv. For example, a standard common VIE wafer with a layout of given micro metal pads or bumps on the TSVs may be cut or diced into separated or diced VIE chips or components each with an array of M2 by N2 (M2×N2) micro metal pads or bumps on the TSVs, M2 and N2 are positive integers, and wherein N2<M2, 1<=N2<=15, and 25<=M2<=250; or N2<M2, 1<=N2<=10, and 15<=M2<=100. For example, a separated or diced VIE chip or component may comprise an array of 50 by 5, 150 by 5, 150 by 10, or 250 by 10 micro metal pads or bumps on the TSVs. In another case, if WB_sptsv is equal to or smaller than W_sb+2WB_sbt, the standard common wafer is designed and layout with two alternatives: (1) with islands or regions of arrays of micro metal pads or bumps on the TSVs populated regularly in the whole wafer with reserved scribe lines. Each of the reserved scribe line has a fixed space or separation WB_spild (equal to W_sb+2WB_sbt,) between two neighboring islands or regions of arrays of micro metal pads or bumps on the TSVs (that is between two neighboring micro metal pads or bumps on the TSVs across the reserved scribe line) in x-direction and y-direction, respectively, that is, there are two different separation spaces, WB_spild and WB_sptsv, between two neighboring micro metal pads or bumps on the TSVs in a separated or diced VIE chip or component. WB_spild is greater than WB_sptsv. As an example, WB_spild is greater than 50, 40 or 30 micrometers, and WB_sptsv is smaller than 50, 40 or 30 micrometers. The reserved scribe line between two neighboring islands or regions of arrays of micro metal pads or bumps on the TSVs may be used as a scribe line for dicing and cutting. The standard common VIE wafer may be cut or diced, through the reserved scribe lines, to form separated or diced VIE chips or components in square or rectangular shape and with various dimensions. In this case, the separated or diced chip or component comprises M×N islands or regions of arrays of micro metal pads or bumps on the TSVs (wherein M and N are positive integers, wherein N<M, 1<=N<=10, and 2<=M<=20) with the fixed space or separation WB_spild between two neighboring islands or regions of arrays of micro metal pads or bumps on the TSVs, wherein, for example, WB_spild is greater than 50, 40 or 30 micrometers, and WB_sptsv is smaller than 50, 40 or 30 micrometer. As an example, the standard common VIE wafer with a given design and layout of islands or regions of arrays of micro metal pads or bumps on the TSVs may be cut or diced into a plurality of VIE chips or components, wherein each separated or diced VIE chip or component comprises one or a plurality of islands or regions of arrays of micro metal pads or bumps on the TSVs, for example, 3 by 1 islands or regions of arrays of micro metal pads or bumps on the TSVs, 6 by 1 islands or regions of arrays of micro metal pads or bumps on the TSVs, 4 by 2 islands or regions of arrays of micro metal pads or bumps on the TSVs, 8 by 2 islands or regions of arrays of micro metal pads or bumps on the TSVs, or 10 by 3 islands or regions of arrays of micro metal pads or bumps on the TSVs. If the separated or diced VIE chip or component comprises a plurality of (more than one) islands or regions of arrays of micro metal pads or bumps on the TSVs, there is the reserved scribe line between two neighboring islands or regions of arrays of micro metal pads or bumps on the TSVs therein. The diced or separated VIE chip or component may comprise repetitive islands or regions of arrays of micro metal pads or bumps on the TSVs with each island or region of arrays of micro metal pads or bumps on the TSVs comprising an array of 30 by 2 micro metal pads or bumps on the TSVs, an array of 60 by 2 micro metal pads or bumps on the TSVs, an array of 50 by 5 micro metal pads or bumps on the TSVs, or an array of 100 by 5 micro metal pads or bumps on the TSVs; (2) with micro metal pads or bumps on the TSVs populated regularly in the whole wafer with a fixed pitch and separation (space WB_sptsv) between two neighboring micro metal pads or bumps on the TSVs in x-direction and y-direction, respectively. The standard common VIE wafer may be cut or diced through the micro metal pads or bumps on the TSVs to form separated or diced VIE chips or components in a square or rectangular shape and with any dimension, and the separated or diced VIE chip or component may comprise any number of micro metal pads or bumps on the TSVs. In this case, for each separated or diced VIE chip or component, WB_sbt may be equal to or greater than zero, and is smaller than WB_sptsv, and WB_sptsv is smaller than 50, 40 or 30 micrometers.

[0007] The above specifications for TSVs in the silicon substrate of the VIE chip or component (TSVIE) are applied to the specifications for TGVs in the glass substrate of the VIE chip or component (TGVIE).

[0008] Another aspect of the disclosure provides a standard common wafer for the VIE chips or components. The VIE chip or component is for use in the chip package comprising (i) a single-chip package (comprising only one semiconductor IC chip), or (ii) a multichip package (comprising a plurality of semiconductor IC chips, single-COC package, or a plurality of COC (chip-on-chip components or packages)), as described above and to be described and specified below. The standard common wafers for the VIE chips or components may have a fixed pattern of design and layout for locations of the micro metal pads or bumps on the TSVs, and may be diced or separated into VIE chips or components each with different dimensions or shapes and different numbers of the micro metal pads or bumps on the TSVs. In some applications, the aspect ratio of length to width for a deiced or separated VIE chip or component may be between 2 and 10, between 4 and 10 or between 2 and 40. Assume that the width of a scribe line is W_sb, the space or separation between the scribe line and the micro metal pad or bump on the TSV at the edge or boundary of the VIE chip is WB_sbt, and the space or separation between two neighboring micro metal pads or bumps on the TSVs is WB_sptsv. WB_sptsv is smaller than 50, 40 or 30 micrometers. In a case, if WB_sptsv is greater than W_sb+2WB_sbt, the standard common wafer is designed and layout with micro metal pads or bumps on the TSVs populated regularly in the whole wafer with a fixed pitch and separation (space WB_sptsv) between two neighboring micro metal pads or bumps on the TSVs in x-direction and y-direction, respectively. The standard common VIE wafer may be cut or diced, through the space between two neighboring micro metal pads or bumps on the TSVs, to form a separated or diced VIE chip or component in a square or rectangular shape and with any dimension, and the separated or diced VIE chip may comprise any number of micro metal pads or bumps on the TSVs. In this case, in each separated or diced VIE chip or component, the distance between the edge of the diced VIE chip or component to the nearest micro metal pad or bump on the TSV (WB_sbt) is smaller than WB_sptsv. For example, a standard common VIE wafer with a layout of given micro metal pads or bumps on the TSVs may be cut or diced into separated or diced VIE chips or components each with an array of M2 by N2 (M2×N2) micro metal pads or bumps on the TSVs, M2 and N2 are positive integers, and wherein N2<M2, 1<=N2<=15, and 25<=M2<=250; or N2<M2, 1<=N2<=10, and 15<=M2<=100. For example, a separated or diced VIE chip or component may comprise an array of 50 by 5, 150 by 5, 150 by 10, or 250 by 10 micro metal pads or bumps on the TSVs. In another case, if WB_sptsv is equal to or smaller than W_sb+2 WB_sbt, the standard common wafer is designed and layout with two alternatives: (1) with islands or regions of arrays of micro metal pads or bumps on the TSVs populated regularly in the whole wafer with reserved scribe lines. Each of the reserved scribe line has a fixed space or separation WB_spild (equal to W_sb+2WB_sbt,) between two neighboring islands or regions of arrays of micro metal pads or bumps on the TSVs (that is between two neighboring micro metal pads or bumps on the TSVs across the reserved scribe line) in x-direction and y-direction, respectively, that is, there are two different separation spaces, WB_spild and WB_sptsv, between two neighboring micro metal pads or bumps on the TSVs in a separated or diced VIE chip or component. WB_spild is greater than WB_sptsv. As an example, WB_spild is greater than 50, 40 or 30 micrometers, and WB_sptsv is smaller than 50, 40 or 30 micrometers. The reserved scribe line between two neighboring islands or regions of arrays of micro metal pads or bumps on the TSVs may be used as a scribe line for dicing and cutting. The standard common VIE wafer may be cut or diced, through the reserved scribe lines, to form separated or diced VIE chips or components in square or rectangular shape and with various dimensions. In this case, the separated or diced chip or component comprises M×N islands or regions of arrays of micro metal pads or bumps on the TSVs (wherein M and N are positive integers, wherein N<M, 1<=N<=10, and 2<=M<=20) with the fixed space or separation WB_spild between two neighboring islands or regions of arrays of micro metal pads or bumps on the TSVs, wherein, for example, WB_spild is greater than 50, 40 or 30 micrometers, and WB_sptsv is smaller than 50, 40 or 30 micrometer. As an example, the standard common VIE wafer with a given design and layout of islands or regions of arrays of micro metal pads or bumps on the TSVs may be cut or diced into a plurality of VIE chips or components, wherein each separated or diced VIE chip or component comprises one or a plurality of islands or regions of arrays of micro metal pads or bumps on the TSVs, for example, 3 by 1 islands or regions of arrays of micro metal pads or bumps on the TSVs, 6 by 1 islands or regions of arrays of micro metal pads or bumps on the TSVs, 4 by 2 islands or regions of arrays of micro metal pads or bumps on the TSVs, 8 by 2 islands or regions of arrays of micro metal pads or bumps on the TSVs, or 10 by 3 islands or regions of arrays of micro metal pads or bumps on the TSVs. If the separated or diced VIE chip or component comprises a plurality of (more than one) islands or regions of arrays of micro metal pads or bumps on the TSVs, there is the reserved scribe line between two neighboring islands or regions of arrays of micro metal pads or bumps on the TSVs therein. The diced or separated VIE chip or component may comprise repetitive islands or regions of arrays of micro metal pads or bumps on the TSVs with each island or region of arrays of micro metal pads or bumps on the TSVs comprising an array of 30 by 2 micro metal pads or bumps on the TSVs, an array of 60 by 2 micro metal pads or bumps on the TSVs, an array of 50 by 5 micro metal pads or bumps on the TSVs, or an array of 100 by 5 micro metal pads or bumps on the TSVs; (2) with micro metal pads or bumps on the TSVs populated regularly in the whole wafer with a fixed pitch and separation (space WB_sptsv) between two neighboring micro metal pads or bumps on the TSVs in x-direction and y-direction, respectively. The standard common VIE wafer may be cut or diced through the micro metal pads or bumps on the TSVs to form separated or diced VIE chips or components in a square or rectangular shape and with any dimension, and the separated or diced VIE chip or component may comprise any number of micro metal pads or bumps on the TSVs. In this case, for each separated or diced VIE chip or component, WB_sbt may be equal to or greater than zero, and is smaller than WB_sptsv, and WB_sptsv is smaller than 50, 40 or 30 micrometers.

[0009] The above specifications for micro metal pads or bumps on TSVs in the silicon substrate of the VIE chip or component (TSVIE) are applied to the specifications for that of TGVs in the glass substrate of the VIE chip or component (TGVIE).

[0010] Another aspect of the disclosure provides a chip-on-chip component or package (COC) configured in a format like the one or the plurality of semiconductor IC chips in the chip package, for packaging in the chip package as described above, or to be described and specified below. The COC has micro metal pads, pillars or bumps exposed at a surface thereof, like micro metal pads, pillars or bumps at the surface of the semiconductor IC chips. The micro metal pads, pillars or bumps exposed at the surface of the (COC) are configured for the chip package as described above, or to be described and specified below.

[0011] A first type COC comprises a first semiconductor IC chip with the frontside (with transistors) facing up, and a second semiconductor IC chip with the frontside (with transistors) facing down, wherein the second semiconductor IC chip is on or over and bonded to the first semiconductor IC chip, wherein the area of the second semiconductor IC chip is smaller than that of the first semiconductor IC chip, and the boundary (four edges) of the second semiconductor IC chip is within the boundary (four edges) of the first semiconductor IC chip. The first semiconductor IC chip comprises through silicon vias (TSVs) in its silicon substrate, and micro metal pads, pillars or bumps at the bottom of the TSVs, same as the micro metal pads, pillars or bumps at the frontside of the one or the plurality of second semiconductor IC chips in the chip packages described above or to be described and specified below. The first and second semiconductor IC chips may comprise (i) the standard commodity FPGA chip, (ii) an auxiliary or supporting (AS) IC chip, wherein the AS IC chip comprises a cryptography or security IC chip, I/O or control IC chip, power management IC chip, and/or Innovated ASIC or COT (abbreviated as IAC below) IC chip (the AS IC chips to be described and specified below), (iii) processing and/or computing IC chip, for example CPU, GPU, DSP, TPU, APU or ASIC chip, and/or (iv) memory IC chip, for a first example, the non-volatile NAND and/or NOR flash chip, and/or High Bandwidth DRAM or SRAM Memory (HBM) chip. For a first example, a first type COC may comprise (a) the first semiconductor chip comprising the standard commodity FPGA chip, or the processing and/or computing IC chip, for example CPU, GPU, DSP, TPU, APU or ASIC chip, and (b) the second semiconductor IC chip comprising the AS IC chip comprising the cryptography or security IC chip, I/O or control IC chip, power management IC chip, and/or Innovated ASIC or COT (abbreviated as IAC below) IC chip, or the memory IC chip, for example, the non-volatile NAND and/or NOR flash chip, and/or High Bandwidth DRAM or SRAM Memory (HBM) chip. In the first example, the COC may be a (i) FPGA/AS COC or logic/AS COC, or (ii) a FPGA/HBM COC or logic/HBM COC. The functions and purposes of the AS chip or the memory chip (the second semiconductor IC chip), and its relationship to the standard commodity FPGA chip, or the processing and/or computing IC chip (the first semiconductor IC chip) in the same first type COC will be described and specified below. For a second example, a first type chip-on-chip component or package may comprise (a) the first semiconductor chip comprising the AS IC chip comprising the cryptography or security IC chip, I/O or control IC chip, power management IC chip, or Innovated ASIC or COT (abbreviated as IAC below) IC chip, or the memory IC chip, for example, the non-volatile NAND and/or NOR flash chip, and/or High Bandwidth DRAM or SRAM Memory (HBM) chip, and (b) the second semiconductor IC chip comprising the standard commodity FPGA chip, or the processing and/or computing IC chip, for example CPU, GPU, DSP, TPU, APU or ASIC chip. In the second example, the COC may be a (i) FPGA/AS COC or logic/AS COC, or (ii) a FPGA/HBM COC or logic/HBM COC. In the second example, the COC may be a (i) FPGA/AS COC or logic/AS COC, or (ii) a FPGA/HBM COC or logic/HBM COC. In the second example, the functions and purposes of the AS chip or the memory chip (the first chip), and its relationship to the standard commodity FPGA chip, or the processing and/or computing IC chip (the second chip) in the same first type COC will be described and specified below.

[0012] The key process steps of forming the first type COC are: (i) flip-chip bonding the separated or diced second semiconductor IC chip on a wafer comprising the first semiconductor IC chips by flip-chip solder reflow bonding, thermal compression bonding, or oxide-to-oxide metal-to-metal direct bonding, wherein the first semiconductor IC chip with the frontside (with transistors) facing up, and the second semiconductor IC chip with the frontside (with transistors) facing down. The pitch between two micro metal bonds (based on the pitch of the micro metal pads, pillars or bumps at the frontside of the first and second semiconductor IC chips) formed by the thermal compression bonding may be between 5 and 30 micrometers or between 10 and 25 micrometers. The pitch between two micro metal bonds (based on the pitch of the micro metal pads, pillars or bumps at the frontside of the first and second semiconductor IC chips) formed by the oxide-to-oxide metal-to-metal direct bonding may be between 3 and 10 micrometers or 4 and 7 micrometers; (ii) applying a material, resin, or compound (a) on or over the wafer comprising the first semiconductor IC chips, and (b) between the second semiconductor IC chips. The polymer material includes, for example, polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer, or silicone. The polymer may be, for example, photosensitive polyimide/PBO PIMEL™ supplied by Asahi Kasei Corporation, Japan; or epoxy-based molding compounds, resins or sealants provided by Nagase ChemteX Corporation, Japan; (iii) polishing, grinding or CMP to planarize the top surface of the applied material, resin, or compound. The backside of the second semiconductor IC chip (at the top) may be exposed after the polishing, grinding or CMP process; (iv) polishing, grinding or CMP the surface at the backside of the wafer until the bottom surface of TSVs in the substrate of the wafer is exposed; (v) forming micro metal pads, pillars or bumps at the bottom of the TSVs; (iv) the wafer is then separated or diced to from the separated first type COC.

[0013] A second type COC comprises a first semiconductor IC chip with the frontside (with transistors) facing up, a second semiconductor IC chip with the frontside (with transistors) facing down, and a VIE chip or component; wherein the first semiconductor IC chip and the VIE chip or component are disposed on a same horizontal plane, and the second semiconductor IC chip is on or over the first semiconductor IC chip and the VIE chip or component, wherein the second semiconductor IC chip has a portion extending from at least an edge of the first semiconductor IC chip in a horizontal direction, and the VIE chip or component is vertically under the portion. The first semiconductor IC chip and the VIE chip or component may comprise through silicon vias (TSVs) in their silicon substrates, and micro metal pads, pillars or bumps at the bottom of the TSVs, same as the micro metal pads, pillars or bumps at the frontside of the one or the plurality of second semiconductor IC chips in the chip packages described above or to be described and specified below. The signal, clock, power supply (Vcc) or ground reference (Vss) for the second semiconductor IC chip may be through the TSVs of VIE chip or component. The second type COC is to be used in the chip package to be described and specified in the chip packages below. As a first example, a second type COC may comprise (a) the first semiconductor chip comprising the standard commodity FPGA chip, or the processing and/or computing IC chip, for example CPU, GPU, DSP, TPU, or APU chip, and (b) the second semiconductor IC chip comprising the AS IC chip comprising the cryptography or security IC chip, I/O or control IC chip, power management IC chip, and/or Innovated ASIC or COT (abbreviated as IAC below) IC chip, or the memory IC chip, for example, the non-volatile NAND and/or NOR flash chip, and/or High Bandwidth DRAM or SRAM Memory (HBM) chip. In the first example, the COC may be a (i) FPGA/AS COC or logic/AS COC, or (ii) FPGA/HBM COC or logic/HBM COC. In the first example, the functions and purposes of the AS chip or the memory chip (the second semiconductor IC chip), and its relationship to the standard commodity FPGA chip, or the processing and/or computing IC chip (the first semiconductor IC chip) in the same second type COC will be described and specified below. For a second example, a second type COC may comprise (a) the first semiconductor chip comprising the AS IC chip comprising the cryptography or security IC chip, I/O or control IC chip, power management IC chip, or Innovated ASIC or COT (abbreviated as IAC below) IC chip, or the memory IC chip, for example, the non-volatile NAND and/or NOR flash chip, and/or High Bandwidth DRAM or SRAM Memory (HBM) chip, and (b) the second semiconductor IC chip comprising the standard commodity FPGA chip, or the processing and/or computing IC chip, for example CPU, GPU, DSP, TPU, or APU chip. In the second example, the COC may be a (i) FPGA/AS COC or logic/AS COC, or (ii) a FPGA/HBM COC or logic/HBM COC. In the second example, the COC may be a (i) FPGA/AS COC or logic/AS COC, or (ii) FPGA/HBM COC or logic/HBM COC. In the second example, the functions and purposes of the AS chip or the memory chip (the first semiconductor IC chip), and its relationship to the standard commodity FPGA chip, or the processing and/or computing IC chip (the second semiconductor IC chip) in the same second type COC will be described and specified below.

[0014] The key process steps of forming the second type COC are: (i) flip-chip bonding the separated or diced first semiconductor IC chip and the separated or diced VIE chips or components on a wafer comprising the second semiconductor IC chips by flip-chip solder reflow bonding, thermal compression bonding, or oxide-to-oxide metal-to-metal direct bonding. The pitch between two micro metal bonds (based on the pitch of the micro metal pads, pillars or bumps at the frontside of the first and second semiconductor IC chips, and at the surface of the VIE chips or components) formed by the thermal compression bonding may be between 5 and 30 micrometers or 10 and 25 micrometers. The pitch between two micro metal bonds (based on the pitch of the micro metal pads, pillars or bumps at the frontside of the first and second semiconductor IC chips, and at the surface of the VIE chips or components) formed by the oxide-to-oxide metal-to-metal direct bonding may be between 3 and 10 micrometers or 4 and 7 micrometers; (ii) applying a material, resin, or compound (a) on or over the wafer comprising the second semiconductor IC chips, and (b) between the first semiconductor IC chips and the VIE chips or components. The polymer material includes, for example, polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer, or silicone. The polymer may be, for example, photosensitive polyimide/PBO PIMEL™ supplied by Asahi Kasei Corporation, Japan; or epoxy-based molding compounds, resins or sealants provided by Nagase ChemteX Corporation, Japan; (iii) polishing, grinding or CMP to planarize the top surface of the applied material, resin, or compound until the surface of TSVs in the silicon substrates of the first semiconductor IC chips and the VIE chips or components is exposed; (iii) formed micro metal pads, pillars or bumps at the exposed surface of the TSVs of the first semiconductor IC chips and the VIE chips or components; (iv) the wafer is then separated or diced, and then turn the separated or diced units upside down to obtain the separated or diced second type COC, as described and specified above. The second type COCs are to be used in the chip package to be described and specified in the chip packages below.

[0015] Another aspect of the disclosure provides methods for forming a chip package (including single-chip package or multichip package) using the VIE chips or components (including TSVIEs, TGVIEs or TPVIEs). The chip package including a Fan-Out Interconnection Technology (FOIT) package, a Chip-On-Interposer (COIP) package, or a Chip-On-an-Interconnection-Substrate (COIS) package. The chip package comprises one or a plurality of semiconductor IC chips, one or a plurality of the first type chip-on-chip components or packages (COCs), and/or one or a plurality of the second type chip-on-chip components or packages (COCs). The methods of forming FOIT, COIP and COIS packages will be described and specified below.

[0016] Another aspect of the disclosure provides a method of thermal compression bump bonding for bonding the semiconductor IC chip or chips (and/or the first type COC or the second type COC) and the VIE chips or components to a substrate (for example, an interposer in a Chip-On-Interposer (COIP) package, or a temporary substrate with Fan-Out redistribution layer in the Fan-Out Interconnection Technology (FOIT) package), both are to be described below.

[0017] Another aspect of the disclosure provides a method of oxide-to-oxide/metal-to-metal direct bonding for bonding the semiconductor IC chip or chips (and/or the first type COC or the second type COC) and the VIE chips or components to a substrate. (for example, an interposer in a Chip-On-Interposer (COIP) package with First Interconnection Scheme of the InterPoser (FISIP)), to be described below.

[0018] Another aspect of the disclosure provides a Fan-Out Interconnection Technology (FOIT) with Frontside Interconnection Scheme of logic Drive or device (abbreviated as FISD) and Backside metal Interconnection Scheme at the backside of the multichip-packaged logic drive or device (abbreviated as BISD) for making or fabricating a multi-chip package using the VIE chips or components. The multichip package may be used for a logic drive comprising one or a plurality of standard commodity Field Programmable Gate Array (FPGA) IC chips. The multichip package is formed by the following process steps:

• • [0019] (1) Providing a chip carrier, holder, molder or substrate, semiconductor IC chips and VIE chips or components, or COCs and VIE chips or components; wherein the semiconductor IC chips may comprise TSVs; alternatively, the semiconductor IC chips may not comprise TSVs; and the COCs comprise the first type COC or the second type COC. The semiconductor IC chip or COC will be abbreviated as SIC/COC. The semiconductor IC chip, and the first type COC or the second type COC have the same format with micro metal pads, pillars or bumps at their frontside surface (for the semiconductor IC chip, the frontside is the side with transistors; for the first type COC or the second type COC, the frontside is the backside of the first semiconductor IC chip (with TSVs) in the COC). Then placing, fixing or attaching the SIC/COCs and VIE chips or components to and on the carrier, holder, molder or substrate. The carrier, holder, molder or substrate may be in a wafer format (with 8″, 12″ or 18″ in diameter), or, in a panel format in the square or rectangle format (with a width or a length greater than or equal to 20 cm, 30 cm, 50 cm, 75 cm, 100 cm, 150 cm, 200 cm or 300 cm). The material of the chip carrier, holder, molder or substrate may be silicon, metal, ceramics, glass, steel, plastics, polymer, epoxy-based polymer, or epoxy-based compound. The SIC/COCs and the VIE chips or components are placed, fixed or attached (with the backside of the SIC/COCs and the VIE chips or components without micro metal pads, pillars or bumps facing down) to the carrier, holder, molder or substrate. The VIE chips or components and the SIC/COCs are on a same horizontal plane (coplanar). Each of the VIE chips or components is located in a space between two neighboring SIC/COCs. The semiconductor IC chips comprise (i) the standard commodity FPGA chip, (ii) an auxiliary or supporting (AS) IC chip, wherein the auxiliary or supporting IC chip comprises a cryptography or security IC chip, I/O or control IC chip, power management IC chip, and/or Innovated ASIC or COT (abbreviated as IAC below) IC chip, The AS IC chips will be described or specified below, (iii) processing and/or computing IC chip, for example CPU, GPU, DSP, TPU, APU or ASIC chip, and/or (iv) memory IC chip, for example, the non-volatile NAND and/or NOR flash chip, and/or High Bandwidth DRAM or SRAM Memory (HBM) chip. The COCs are as described and specified above. All the SIC/COCs and the VIE chips or components packaged in the multichip package comprise micro metal pads, pillars or bumps, (for example, copper pads or pillars, or solder bumps) on their surfaces (the front sides); wherein the frontside of the one or the plurality of the semiconductor IC chips have transistors, and the frontside of the one or the plurality of the first type COC or the second type COC is the backside (without transistors) of the first semiconductor IC chips at the bottom of the chip-on-chip units or components. The frontside of the SIC/COCs (the side or surface with micro metal pads, pillars or bumps) is facing up, and the backside of the SIC/COCs (the side or surface without micro metal pads, pillars or bumps) is placed, fixed, held or attached on or to the carrier, holder, molder or substrate.
  • [0020] (2) Applying a material, resin, or compound to fill the gaps or spaces between the SIC/COCs, between the VIE chips or components, and between the SIC/COCs and the VIE chips or components, up to a level sufficiently at a horizontal level as the top-most frontside surfaces of the SIC/COCs and the VIE chips or components by methods, for example, spin-on coating, screen-printing, dispensing or molding in the wafer or panel format. The molding method includes the compress molding (using top and bottom pieces of molds) or the casting molding (using a dispenser). The material, resin, or compound used may be a polymer material includes, for example, polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer, or silicone. The polymer may be, for example, photosensitive polyimide/PBO PIMEL™ supplied by Asahi Kasei Corporation, Japan; or epoxy-based molding compounds, resins or sealants provided by Nagase Chemte X Corporation, Japan. The material, resin or compound is applied (by coating, printing, dispensing or molding) on or over the carrier, holder, molder or substrate to a level to: (i) fill gaps or spaces between SIC/COCs and VIE chips or components, (ii) sufficiently at a horizontal level as the top-most frontside surface of the SIC/COCs and VIE chips or components. Applying a CMP, polishing or grinding process to planarize the surface of the applied material, resin or compound, and until a level where the micro metal pads, pillars or bumps of the SIC/COCs and VIE chips or components are fully exposed.
  • [0021] (3) Depositing by a wafer or panel processing a first insulating dielectric layer (for example, a polymer layer) on or over (i) the front side (the side with micro metal pads, pillars or bumps) of the SIC/COCs and the VIE chips or components, (ii) exposed micro copper pads or pillars, or solder bumps at the front side of the SIC/COCs and the VIE chips or components, and (iii) the material, resin or compound in the spaces or gaps between the SIC/COCs, between the VIE chips or components, and between the SIC/COCs and the VIE chips or components. Then forming openings in the first insulating dielectric layer to expose the micro copper pads or pillars, or solder bumps at the front side of the SIC/COCs and the VIE chips or components. The first insulating dielectric layer comprises a polymer material includes, for example, polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer, or silicone.
  • [0022] (4) Forming a Frontside Interconnection Scheme in, on or of the logic Drive or Device (FISD) on or over (i) the first insulating dielectric layer deposited as described above, (ii) exposed the micro copper pads or pillars, or solder bumps at the front side of the SIC/COCs and the VIE chips or components by a wafer or panel processing. The FISD comprises one or a plurality of interconnection metal layers, (for example, 1 to 5 or 1 to 8 interconnection metal layers) with inter-metal dielectric layers between two neighboring layers of the plurality of interconnection metal layers. The metal lines or traces of the interconnection metal layers of the FISD are over the SIC/COCs and the VIE chips or components and extend horizontally across the edges of the SIC/COCs or the VIE chips or components. The metal lines or traces of the interconnection metal layers of the FISD are formed using embossing copper electroplating processes. The interconnection metal lines or traces of FISD have an adhesion layer (Ti or TiN, for example) and the copper seed layer at the bottom of the metal lines or traces, but not at a sidewall of metal lines or traces of the interconnection metal layers of the FISD. The inter-metal dielectric layers may comprise polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer, or silicone. The polymer may be, for example, photosensitive polyimide/PBO PIMEL™ supplied by Asahi Kasei Corporation, Japan; or epoxy-based molding compounds, resins or sealants provided by Nagase ChemteX Corporation, Japan.

[0023] The thickness of the metal lines or traces of the FISD is between, for example, 0.3 μm and 30 μm, 0.5 μm and 20 μm, 1 μm and 10 μm, or 0.5 μm to 5 μm, or thicker than or equal to 0.3 μm, 0.5 μm, 0.7 μm, 1 μm, 1.5 μm, 2 μm, 3 μm or 5 μm. The width of the metal lines or traces of the FISD is between, for example, 0.3 μm and 30 μm, 0.5 μm and 20 μm, 1 μm and 10 μm, or 0.5 μm to 5 μm, or wider than or equal to 0.3 μm, 0.5 μm, 0.7 μm, 1 μm, 1.5 μm, 2 μm, 3 μm or 5 μm. The thickness of the inter-metal dielectric layer of the FISD is between, for example, 0.3 μm and 30 μm, 0.5 μm and 20 μm, 1 μm and 10 μm, or 0.5 μm and 5 μm, or thicker than or equal to 0.3 μm, 0.5 μm, 0.7 μm, 1 μm, 1.5 μm, 2 μm, 3 μm or 5 μm.

• • [0024] (5) Applying a CMP, polishing or grinding process at the backside of the SIC/COCs and VIE chips or components to expose the surfaces of the TSVs, TGVs or TPVs in the SIC/COCs and VIE chips or components;
  • [0025] (6) (now turning the whole structure upside down) Depositing a second insulating dielectric layer (for example a polymer layer) on the top side (the opposite side of the side with FISD) of the multichip package; that is, on or over (i) the exposed backside of the semiconductor IC chips (or COCs), (ii) the exposed backside of the VIE chips or components and (iii) the spaces or gaps between the semiconductor IC chips (or COCs), between the VIE chips or components, and between the semiconductor IC chips (or COCs) and the VIE chips or components. Forming openings in the second insulating dielectric layer to expose the surfaces of the TSVs, TGVs or TPVs in the VIE chips or components;
  • [0026] (7) Forming a Backside metal Interconnection Scheme at the backside of the multichip-packaged logic drive or device (abbreviated as BISD in below) on or over the second insulating dielectric layer, and the exposed surfaces (of the TSVs, TGVs or TPVs in the VIE chips or components) in the openings in the second insulating dielectric layer. The BISD is over (i) the exposed backside of the semiconductor IC chips (or COCs), (ii) the exposed backside of the VIE chips or components and (iii) the spaces or gaps between the semiconductor IC chips (or COCs), between the VIE chips or components, and between the semiconductor IC chips (or COCs) and the VIE chips or components. The BISD may comprise metal lines, traces, or planes in one or a plurality of interconnection metal layers (for example, 1 to 6 or 1 to 4 interconnection metal layers), and is formed on or over the backsides of the semiconductor IC chips and the VIE chips or components, or, on or over the backsides of the COC and the VIE chips or components. The metal lines or traces of the interconnection metal layers of the BISD are over the SIC/COCs and the VIE chips or components and extend horizontally across the edges of the SIC/COCs or the VIE chips or components. The BISD may be formed using the same or similar process steps and materials as in forming the FISD as described above. The BISD provides additional interconnection metal layer or layers at the top or the backside of the multichip package.

[0027] The thickness of the metal lines, traces or planes of the BISD is between, for example, 0.3 μm and 40 μm, 0.5 μm and 30 μm, 1 μm and 20 μm, 1 μm and 15 μm, 1 μm and 10 μm, or 0.5 μm to 5 μm, or thicker than or equal to 0.3 μm, 0.7 μm, 1 μm, 2 μm, 3 μm, 5 μm, 7 μm or 10 μm. The width of the metal lines or traces of the BISD is between, for example, 0.3 μm and 40 μm, 0.5 μm and 30 μm, 1 μm and 20 μm, 1 μm and 15 μm, 1 μm and 10 μm, or 0.5 μm to 5 μm, or wider than or equal to 0.3 μm, 0.7 μm, 1 μm, 2 μm, 3 μm, 5 μm, 7 μm or 10 μm. The thickness of the inter-metal dielectric layer of the BISD is between, for example, 0.3 μm and 50 μm, 0.3 μm and 30 μm, 0.5 μm and 20 μm, 1 μm and 10 μm, or 0.5 μm and 5 μm, or thicker than or equal to 0.3 μm, 0.5 μm, 0.7 μm, 1 μm, 1.5 μm, 2 μm, 3 μm or 5 μm. The planes in a metal layer of interconnection metal layers of the BISD may be used for the power, ground planes of a power supply, and/or used as heat dissipaters or spreaders for the heat dissipation or spreading; wherein the metal thickness may be thicker, for example, between 5 μm and 50 μm, 5 μm and 30 μm, 5 μm and 20 μm, or 5 μm and 15 μm; or thicker than or equal to 5 μm, 10 μm, 20 μm, or 30 μm. The power, ground plane, and/or heat dissipater or spreader may be layout as interlaced or interleaved shaped structures in a plane of an interconnection metal layer of the BISD; or may be layout in a fork shape.

• • [0028] (8) Forming copper or nickel pads, copper pillars, or solder bumps on or over exposed surfaces of the top-most metal interconnection layer (of the BISD) at the bottom of openings in the top-most insulting dielectric layer of the BISD. The copper or nickel pads, copper pillars, or solder bumps in an area array at the top of the multichip package including at locations vertically over the backside of the SIC/COCs of the multichip package. The copper or nickel pads, copper pillars, or solder bumps are formed by performing an embossing electroplating copper process.
  • [0029] (9) (now turning the whole structure upside down) Forming copper pads or pillars, or solder bumps (for example, copper pads, pillars or bumps, solder bumps, or gold bumps) on or over the top-most insulating dielectric layer of the FISD, and the exposed top surfaces of the top-most interconnection metal layer of the FISD in openings of the top-most insulating dielectric layer of the FISD, by performing an embossing electroplating copper process.
  • [0030] (10) Separating, cutting or dicing the finished wafer or panel, including separating, cutting or dicing through materials or structures between two neighboring multichip packages. The material (for example, polymer) filling gaps or spaces between chips or components of two neighboring multichip packages is separated, cut or diced to form individual unit of the multichip package.

[0031] In the separated, cut or diced individual unit of the multichip package, the copper or nickel pads, copper pillars, or solder bumps in an area array at the top (the opposite side of FISD side, that is, the backside side of SIC/COCs having micro metal pads, pillars or bumps are facing down) are connected or coupled to a transistor of the SIC/COCs through the TSVs, TGVs or TPVs of the VIE chips or components. The TSVs, TGVs or TPVs of the VIE chips or components are used for connecting or coupling circuits or components (for example, the FISD) at the frontside of the multichip to that (for example, the BISD) at the backside of the multichip package. A copper pad or pillar, or solder bump of the copper pads or pillars, or solder bumps in an area array at the bottom (the FISD side, that is, the front sides of SIC/COCs having micro metal pads, pillars or bumps are facing down) of the separated or diced multichip package may be vertically under a SIC/COCs of the SIC/COCs, and couple or connect (for signal, clock, power supply Vcc, or ground reference Vss) to a copper or nickel pad, copper pillar, or solder bump of the copper or nickel pads, copper pillars, or solder bumps vertically over the SIC/COC through a metal interconnect of the FISD, the TSV, TGV or TPV of the VIE chip or component and a metal interconnect of the BISD, wherein the copper pad or pillar, or solder bump at the bottom of the separated or diced multichip package may couple to a transistor of the SIC/COC. Each separated or diced multichip package may comprise a plurality of SIC/COCs and one or a plurality of VIE chips or components.

[0032] Another aspect of the disclosure provides a Fan-Out Interconnection Technology (FOIT) with FISD and BISD for making or fabricating a single-chip package or single-COC package using the VIE chips or components. The single-chip or single-COC package may comprise only one semiconductor IC chip and at least one of the VIE chips or components; or, only one first type chip-on-chip component or package and at least one of the VIE chips or components; or, only one second type chip-on-chip component or package and at least one of the VIE chips or components. The single-chip or single-COC package is formed using the same or similar process steps as forming the multichip package with FISD and BISD as described and specified above, except:

• • [0033] (A) In Step (1), the SIC/COCs placed, fixed or attached to the carrier, holder, molder or substrate for a process batch may be of the same product or device of the semiconductor IC chip, of the same product or device of the first type chip-on-chip component or package, or, of the same product or device of the second type chip-on-chip component or package. For example, the semiconductor IC chips used in one wafer or panel process batch may be of only one of following products or devices: (i) the standard commodity FPGA chip, (ii) an auxiliary or supporting (AS) IC chip, wherein the auxiliary or supporting IC chip comprises a cryptography or security IC chip, I/O or control IC chip, power management IC chip, and/or Innovated ASIC or COT (abbreviated as IAC below) IC chip, The AS IC chips will be described or specified below, (iii) processing or computing IC chip, for example, the CPU, GPU, DSP, TPU, or APU chip, or (iv) the memory IC chip, for example, the non-volatile NAND or NOR flash chip, or High Bandwidth DRAM or SRAM Memory (HBM) chip.
  • [0034] (B) In Step (10), separating, cutting or dicing the finished wafer or panel, to form a separated single-chip or single-COC package, wherein the single-chip or single-COC package may comprise only one semiconductor IC chip and one or a plurality of VIE chips or components; wherein the single-COC package may comprise only one first type chip-on-chip component or package and one or a plurality of VIE chips or components, or, only one second type chip-on-chip component or package and one or a plurality of VIE chips or components. The single-chip or single-COC package has the copper pads or pillars, or solder bumps in an area array at the bottom (the side which the frontside having micro metal pads, pillars or bumps of SIC/COC is facing), and the copper or nickel pads, copper pillars, or solder bumps also in an area array at the top (the side which the backside of SIC/COC without micro metal pads, pillars or bumps is facing). The copper or nickel pads, copper pillars, or solder bumps may be at locations vertically over or under the SIC/COC and may be connecting or coupling to the transistors of the SIC/COC. A copper pad or pillar, or solder bump of the copper pads or pillars, or solder bumps at the bottom (the FISD side, that is, the frontside of the SIC/COC with micro metal pads, pillars or bumps are facing down) of the separated or diced single-chip or single-COC package may be vertically under the SIC/COC, and couple or connect (for signal, clock, power supply Vcc, or ground reference Vss) to a copper or nickel pad, copper pillar, or solder bump of the copper or nickel pads, copper pillars, or solder bumps vertically over the SIC/COC through a metal interconnect of the FISD, the TSV, TGV or TPV of one of the VIE chips or components and a metal interconnect of the BISD, wherein the copper pad or pillar, or solder bump at the bottom of the separated or diced single-chip or single-COC package may couple to a transistor of the SIC/COC.

[0035] Another aspect of the disclosure provides a Fan-Out Interconnection Technology (FOIT) with a Fan-Out Interconnection Scheme of the logic Drive or Device (FOISD) and the BISD (as described and specified above) for making or fabricating a multi-chip package using the VIE chips or components. The multichip package may be used for a logic drive comprising one or a plurality of standard commodity Field Programmable Gate Array (FPGA) IC chips. The multichip package is formed by providing a Temporary Substrate (T-Sub) with a Fan-Out Interconnection Scheme of the logic Drive or Device (FOISD) on it. The FOISD comprises fan-out interconnection metal lines or traces and micro copper pads or pillars, or solder bumps on or over the T-Sub. The semiconductor IC chips or the COCs (SIC/COCs), and the VIE chips or components are flip-chip packaged on the T-Sub using the micro copper pads or pillars, or solder bumps on the FOISD. The T-Sub may be in a wafer format (with 8″, 12″ or 18″ in diameter), or, in a panel format in the square or rectangle format (with a width or a length greater than or equal to 20 cm, 30 cm, 50 cm, 75 cm, 100 cm, 150 cm, 200 cm or 300 cm). The T-Sub is served as a temporary support for the wafer-level or panel-level processes. The T-Sub will be removed or released after the processes. The IC chips, packages or components to be flip-chip assembled, bonded or packaged, to the substrate (T-Sub) include the semiconductor IC chips or the COCs (SIC/COCs), and the VIE chips or components. The FOISD comprises one or multiple interconnection metal layers, with an inter-metal dielectric layer between two neighboring interconnection metal layers. The metal lines or traces and the metal vias are formed by the embossing electroplating copper processes. The inter-metal dielectric layer may comprise polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer, or silicone. The polymer may be, for example, photosensitive polyimide/PBO PIMEL™ supplied by Asahi Kasei Corporation, Japan; or epoxy-based molding compounds, resins or sealants provided by Nagase ChemteX Corporation, Japan. The FOISD may comprise 1 to 8 layers, or 1 to 5 layers of interconnection metal layers. Micro copper pads or pillars, or solder bumps are formed on or over the top most interconnection metal layer of the FOISD.

[0036] The thickness of the metal lines or traces of FOISD is between, for example, 0.3 μm and 20 μm, 0.5 μm and 10 μm, 1 μm and 5 μm, 1 μm and 10 μm, or 2 μm and 10 μm; or thicker than or equal to 0.3 μm, 0.5 μm, 0.7 μm, 1 μm, 1.5 μm, 2 μm or 3 μm. The width of the metal lines or traces of FOISD is between, for example, 0.3 μm and 20 μm, 0.5 μm and 10 μm, 1 μm and 5 μm, 1 μm and 10 μm, or 2 μm and 10 μm; or wider than or equal to 0.3 μm, 0.5 μm, 0.7 μm, 1 μm, 1.5 μm, 2 μm or 3 μm. The thickness of the inter-metal dielectric layer has a thickness between, for example, 0.3 μm and 20 μm, 0.5 μm and 10 μm, 1 μm and 5 μm, or 1 μm and 10 μm; or thicker than or equal to 0.3 μm, 0.5 μm, 0.7 μm, 1 μm, 1.5 μm, 2 μm or 3 μm.

[0037] The process steps for forming the FOIT multi-chip package with the FOISD are described as below:

• • [0038] (1) Performing flip-chip assembling, bonding or packaging: (a) First providing the substrate with FOISD, semiconductor IC chips (or COCs) and the VIE chips or components. The substrate (T-Sub) with FOISD is formed as described and specified above; (b) The micro metal pads, pillars or bumps of the semiconductor IC chips (or COCs) and the VIE chips or components are then flip-chip assembled, bonded or packaged on or to corresponding micro copper pads or pillars, or solder bumps of the FOISD on or over the substrate with the side or surface of the semiconductor IC chips with transistors faced down, or with the side of the COCs having micro metal pads, pillars or bumps faced down. The backside of the semiconductor IC chips (the side or surface without transistors) is facing up, or the backside of the COCs (the side or surface without micro metal pads, pillars or bumps) is facing up. All the semiconductor IC chips (or COCs) and the VIE chips or components to be flip-chip packaged in the multichip package comprise micro metal pads, pillars or bumps. The semiconductor IC chips comprise (i) the standard commodity FPGA chip, (ii) an auxiliary or supporting (AS) IC chip, wherein the auxiliary or supporting IC chip comprises a cryptography or security IC chip, I/O or control IC chip, power management IC chip, and/or Innovated ASIC or COT (abbreviated as IAC below) IC chip, The AS IC chips will be described or specified below, (iii) processing and/or computing IC chip, for example CPU, GPU, DSP, TPU, APU or ASIC chip, and/or (iv) memory IC chip, for example, the non-volatile NAND and/or NOR flash chip, and/or High Bandwidth DRAM or SRAM Memory (HBM) chip. The COCs are as described and specified above.
  • [0039] (2) Applying a material, resin, or compound to fill the gaps or spaces between the semiconductor IC chips (or COCs), the gaps or spaces between the VIE chips or components, and the gaps or spaces between the semiconductor IC chips (or COCs) and the VIE chips or components, covering the backside surfaces of semiconductor IC chips (or COCs) and the VIE chips or components by methods, for example, spin-on coating, screen-printing, dispensing or molding in the wafer or panel format. The molding method includes the compress molding (using top and bottom pieces of molds) or the casting molding (using a dispenser). The material, resin, or compound used may be a polymer material includes, for example, polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer, or silicone. The polymer may be, for example, photosensitive polyimide/PBO PIMEL™ supplied by Asahi Kasei Corporation, Japan; or epoxy-based molding compounds, resins or sealants provided by Nagase ChemteX Corporation, Japan. The material, resin or compound is applied (by coating, printing, dispensing or molding) on or over the substrate and on or over the backside of the semiconductor IC chips (or COCs) to a level to: (i) fill gaps or spaces between semiconductor IC chips (or COCs) and VIE chips or components, (ii) cover the top-most backside surface of the semiconductor IC chips (or COCs) and VIE chips or components. Applying a CMP, polishing or grinding process to planarize the surface of the applied material, resin or compound, and until a level where the backside surfaces of TSVs, TGVs or TPVs of the VIE chips or components are fully exposed.
  • [0040] (3) Depositing an insulating dielectric layer (for example a polymer layer) on the top side (the opposite side of the side with FOISD) of the multichip package, that is, on or over (i) the exposed backside of the semiconductor IC chips (or COCs), (ii) the exposed backside of the VIE chips or components and (iii) the material, resin, or compound in the spaces or gaps between the semiconductor IC chips (or COCs), between the VIE chips or components, and between the semiconductor IC chips (or COCs) and the VIE chips or components. Forming openings in the insulating dielectric layer, exposing the top (backside) surfaces of the TSVs, TGVs or TPVs in the VIE chips or components.
  • [0041] (4) Forming a Backside metal Interconnection Scheme at the backside of the multichip-packaged logic drive or device (abbreviated as BISD in below) on or over the second insulating dielectric layer, and the exposed surfaces (of the TSVs, TGVs or TPVs in the VIE chips or components) in the openings in the second insulating dielectric layer. The BISD may comprise metal lines, traces, or planes in one or a plurality of interconnection metal layers, and is formed on or over the backsides of the semiconductor IC chips and the VIE chips or components, or, on or over the backsides of the COC and the VIE chips or components. The metal lines or traces of the interconnection metal layers of the BISD are over the SIC/COCs and the VIE chips or components and extend horizontally across the edges of the SIC/COCs or the VIE chips or components. The BISD may be formed using the same or similar process steps, materials and specification as in forming the BISD in the FOIT multichip package (with the FISD) described above. The BISD provides additional interconnection metal layer or layers at the top or the backside of the multichip package.
  • [0042] (5) Forming copper or nickel pads, copper pillars, or solder bumps on or over exposed surfaces of the top-most metal interconnection layer (of the BISD) at the bottom of openings in the top-most insulting dielectric layer of the BISD. The copper or nickel pads, copper pillars, or solder bumps in an area array at the top of the multichip package including at locations vertically over the backside of the SIC/COCs of the multichip package. The copper or nickel pads, copper pillars, or solder bumps are formed by performing an embossing electroplating copper process.
  • [0043] (6) Removing or releasing the temporary substrate (the T-Sub only, not including FOISD) from the structures on or over it. The bottom surfaces of the metal via contacts in the openings in the bottom-most dielectric insulating layer of the FOISD are then exposed (the side of the semiconductor IC chips with transistors are facing down, or the side of the micro metal pads, pillars or bumps of COCs are facing down).
  • [0044] (7) (now turning the whole structure upside down) Forming copper pads or pillars, or solder bumps on or over the exposed top surfaces of the metal via contacts of the FOISD, (here side of the semiconductor IC chips with transistors are facing up, or the side of the micro metal pads, pillars or bumps of COCs are facing up) by performing an embossing electroplating copper process.
  • [0045] (8) Separating, cutting or dicing the molding material, including separating, cutting or dicing through materials or structures between two neighboring multichip packaged logic drives. The material (for example, polymer) filling gaps between chips of two neighboring multichip packages is separated, cut or diced to from an individual unit of multichip package.

[0046] The BISD provides additional interconnection metal layer or layers at the top or the backside of the multichip package, and provides the copper or nickel pads, copper pillars, or solder bumps in an area array at the top of the multichip package including at locations vertically over the backside of the SIC/COCs of the multichip package, wherein the copper or nickel pads, copper pillars, or solder bumps are connected or coupled to a transistor of the SIC/COCs through the TSVs, TGVs or TPVs of the VIE chips or components. The TSVs, TGVs or TPVs of the VIE chips or components are used for connecting or coupling circuits or components (for example, the FOISD) at the frontside of the multichip to that (for example, the BISD) at the backside of the multichip package. A copper pad or pillar, or solder bump of the copper pads or pillars, or solder bumps at the bottom (the FOISD side, that is, the front sides of SIC/COCs having micro metal pads, pillars or bumps are facing down) of the separated or diced multichip package may be vertically under a SIC/COCs of the SIC/COCs, and couple or connect (for signal, clock, power supply Vcc, or ground reference Vss) to a copper or nickel pad, copper pillar, or solder bump of the copper or nickel pads, copper pillars, or solder bumps vertically over the SIC/COC through a metal interconnect of the FOISD, the TSV, TGV or TPV of the VIE chip or component and a metal interconnect of the BISD, wherein the copper pad or pillar, or solder bump at the bottom of the separated or diced multichip package may couple to a transistor of the SIC/COC. Each separated or diced multichip package may comprise (a) a plurality of semiconductor IC chips and one or a plurality of VIE chips or components; (b) a plurality of COCs and one or a plurality of VIE chips or components: or, (c) one or a plurality of semiconductor IC chips, one or a plurality of COCs, and one or a plurality of VIE chips or components.

[0047] Another aspect of the disclosure provides a Fan-Out Interconnection Technology (FOIT) with FOISD and BISD for making or fabricating a single-chip package or single-COC package using the VIE chips or components. The single-chip package or single-COC package comprises the FOISD and BISD. The single-chip or single-COC package may comprise only one semiconductor IC chip and at least one of the VIE chips or components; or, only one first type chip-on-chip component or package and at least one of the VIE chips or components; or, only one second type chip-on-chip component or package and at least one of the VIE chips or components. The single-chip package or single-COC package is formed using the same or similar process steps as forming the multichip package with the FOISD and BISD as described and specified above, except:

• • [0048] (A) In Step (1), the semiconductor IC chips flip chip bonded or assembled to the FOISD on the temporary substrate for a process batch may be of the same product or device of the semiconductor IC chips (or CIOCs). For example, the semiconductor IC chips (or COCs) used in one wafer or panel process batch may be of only one of following products or devices: (i) the standard commodity FPGA chip, (ii) an auxiliary or supporting (AS) IC chip, wherein the auxiliary or supporting IC chip comprises a cryptography or security IC chip, I/O or control IC chip, power management IC chip, and/or Innovated ASIC or COT (abbreviated as IAC below) IC chip, The AS IC chips will be described or specified below, (iii) the processing or computing IC chip, for example CPU, GPU, DSP, TPU, APU or ASIC chip, or (iv) the memory IC chip, for example, the non-volatile NAND or NOR flash chip, or High Bandwidth DRAM or SRAM Memory (HBM) chip.
  • [0049] (B) In Step (8), separating, cutting or dicing the finished wafer or panel, to form a unit of single-chip package or single-COC package, wherein the unit of single-chip package or single-COC package may comprise only one semiconductor IC chip and one or a plurality of VIE chips or components; or, only one COC and one or a plurality of VIE chips or components. The single-chip or single-COC package (SIC/COC) has copper pads or pillars, or solder bumps in an area array at the bottom (the side which the frontside of the SIC/COC with micro metal pads, pillars or bumps is facing), wherein the copper pads or pillars, or solder bumps connecting or coupling to the SIC/COC may be vertically under the SIC/COC. The single-chip or single-COC package has copper or nickel pads, copper pillars, or solder bumps in the area array at the top (the backside of the SIC/COC without micro metal pads, pillars or bumps). For an example, a copper pad or pillar, or solder bump of the copper pads or pillars, or solder bumps at the bottom (the FOISD side, that is, the frontside of the SIC/COC with micro metal pads, pillars or bumps is facing down) of the separated or diced single-chip or single-COC package may couple or connect to a copper or nickel pad, copper pillar, or solder bump of the copper or nickel pads, copper pillars, or solder bumps on or over the exposed top surfaces of the TSVs, TGVs or TPVs of the VIE chips or components through a metal interconnect of the FOISD and a TSV, TGV or TPV of one of the VIE chips or components (for signal, clock, power supply Vcc and/or ground reference Vss), wherein the copper pad or pillar, or solder bump at the bottom of the separated or diced single-chip or single-COC package may be vertically under the SIC/COC, and couple to a transistor of the SIC/COC. For another example, a copper or nickel pad, copper pillar, or solder bump of the copper or nickel pads, copper pillars, or solder bumps on or over the exposed top surfaces of the TSVs, TGVs or TPVs of the VIE chips or components may couple or connect (for signal, clock, power supply Vcc and/or ground reference Vss) to the transistors of the SIC/COC through one of the TSVs, TGVs or TPVs in one of the VIE chips or components and a metal interconnect of the FOISD, for signal, clock, power supply Vcc and/or ground reference Vss.

[0050] Another aspect of the disclosure provides an interposer for flip-chip assembly or packaging in forming the multichip package comprising the semiconductor IC chips or COCs (SIC/COCs) and the VIE chips or components. The multichip package may comprise one or a plurality of standard commodity FPGA chips and be used for the logic drive. The multi-chip package is based on multiple-Chips-On-an-Interposer (COIP) flip-chip packaging method. The interposer or substrate in the COIP multi-chip package comprises: (1) high density interconnects for fan-out and interconnection between the semiconductor IC chips (or COCs), between the VIE chips or components and/or between the semiconductor IC chip (or COCs) and the VIE chip or component, wherein the semiconductor IC chips (or COICs) and the VIE chips or components are to be flip-chip-assembled, bonded or packaged on or over the interposer, (2) micro copper pads or pillars, or solder bumps on or over the high density interconnects, (3) deep metal vias or shallow metal vias in the interposer. The process steps for forming the interposer of multichip packages are as follows:

• • [0051] (1) Providing a substrate. The substrate may be in a wafer format (with 8″, 12″ or 18″ in diameter), or, in a panel format in the square or rectangle format (with a width or a length greater than or equal to 20 cm, 30 cm, 50 cm, 75 cm, 100 cm, 150 cm, 200 cm or 300 cm). The material of the substrate may be silicon, metal, ceramics, glass, steel, plastics, polymer, epoxy-based polymer, or epoxy-based compound. As an example, a silicon wafer may be used, in the following paragraphs, as a substrate in forming a silicon interposer.
  • [0052] (2) Forming metal vias in the substrate. Silicon wafer is used as an example in forming the metal vias in the substrate. The bottom surface of the metal vias in the silicon wafer are exposed in a latter process steps in forming the multichip package of the logic drive, therefore, the metal vias become through vias, and the through vias are the Trough-Silicon-Vias (TSVs).
  • [0053] (3) Forming a First Interconnection Scheme on or of the Interposer (FISIP). The metal lines or traces, and metal vias (between two neighboring metal layers) of the FISIP are formed by the single damascene copper processes or the double damascene copper processes. The FISIP may comprise 2 to 10 layers, or 3 to 6 layers of interconnection metal layers. The metal lines or traces of the interconnection metal layers of FISIP have the adhesion layer (Ti or TiN, for example) and the copper seed layer at both the bottom and the sidewalls of the metal lines or traces.

[0054] The metal lines or traces in the FISIP are coupled or connected to the micro copper bumps or pillars of the IC chips in or of the logic drive, and coupled or connected to the TSVs in the substrate of the interposer. The thickness of the metal lines or traces of the FISIP, either formed by the single-damascene process or by the double-damascene process, is, for example, between 3 nm and 500 nm, between 10 nm and 1,000 nm, or between 10 nm and 2,000 nm, or, thinner than or equal to 50 nm, 100 nm, 200 nm, 300 nm, 500 nm, 1,000 nm, 1,500 nm or 2,000 nm. The minimum width of the metal lines or traces of the FISIP is, for example, equal to or smaller than 50 nm, 100 nm, 150 nm, 200 nm, 300 nm, 500 nm, 1,000 nm, 1,500 nm or 2,000 nm. The minimum space between two neighboring metal lines or traces of the FISIP is, for example, equal to or smaller than 50 nm, 100 nm, 150 nm, 200 nm, 300 nm, 500 nm, 1,000 nm, 1,500 nm or 2,000 nm. The minimum pitch of the metal lines or traces of the FISIP is, for example, equal to or smaller than 100 nm, 200 nm, 300 nm, 400 nm, 600 nm, 1,000 nm, 3,000 nm or 4,000 nm. The thickness of the inter-metal dielectric layer has a thickness, for example, between 3 nm and 500 nm, between 10 nm and 1,000 nm, or between 10 nm and 2,000 nm, or, thinner than or equal to 50 nm, 100 nm, 200 nm, 300 nm, 500 nm, 1,000 nm or 2,000 nm. The metal lines or traces of the FISIP may be used as the programmable interconnection.

• • [0055] (4) Forming a Second Interconnection Scheme of the Interposer (SISIP) on or over the FISIP structure. The SISIP comprises multiple interconnection metal layers, with an inter-metal dielectric layer between two neighboring interconnection metal layers. The metal lines or traces, and the metal vias are formed by the embossing electroplating copper processes. The SISIP may comprise 1 to 5 layers, or 1 to 3 layers of interconnection metal layers. The metal lines or traces of the interconnection metal layers of SISIP have the adhesion layer (Ti or TiN, for example) and the copper seed layer at the bottoms of the metal lines or traces, but not at a sidewall of the metal lines or traces. Alternatively, the SISIP on or of the interposer may be omitted, and the COIP only has FISIP interconnection scheme on the substrate of the interposer. Alternatively, the FISIP on or of the interposer may be omitted, and the COIP only has SISIP interconnection scheme on the substrate of the interposer.

[0056] The thickness of the metal lines or traces of SISIP is between, for example, 0.3 μm and 20 μm, 0.5 μm and 10 μm, 1 μm and 5 μm, 1 μm and 10 μm, or 2 μm and 10 μm; or thicker than or equal to 0.3 μm, 0.5 μm, 0.7 μm, 1 μm, 1.5 μm, 2 μm or 3 μm. The width of the metal lines or traces of SISIP is between, for example, 0.3 μm and 20 μm, 0.5 μm and 10 μm, 1 μm and 5 μm, 1 μm and 10 μm, or 2 μm and 10 μm; or wider than or equal to 0.3 μm, 0.5 μm, 0.7 μm, 1 μm, 1.5 μm, 2 μm or 3 μm. The thickness of the inter-metal dielectric layer has a thickness between, for example, 0.3 μm and 20 μm, 0.5 μm and 10 μm, 1 μm and 5 μm, or 1 μm and 10 μm; or thicker than or equal to 0.3 μm, 0.5 μm, 0.7 μm, 1 μm, 1.5 μm, 2 μm or 3 μm. The metal lines or traces of SISIP may be used as the programmable interconnection.

• • [0057] (5) Forming micro copper pads, pillars or bumps: (i) on the top surface of the top-most interconnection metal layer of SISIP, exposed in openings in the topmost insulating dielectric layer of the SISIP, or (ii) on the top surface of the top-most interconnection metal layer of FISIP, exposed in openings in the topmost insulating dielectric layer of the FISIP in the case that the SISIP is omitted. An embossing electroplating copper process, as described and specified in above paragraphs, is performed to form the micro copper pillars or bumps on or over the interposer.

[0058] Another aspect of the disclosure provides a method for forming a COIP multi-chip package using an interposer comprising the FISIP, the SISIP, micro copper pads, bumps or pillars and TSVs based on a flip-chip assembled multi-chip packaging technology and process. The multichip package may comprise one or a plurality of standard commodity FPGA chips and be used for the logic drive. The process steps for forming the COIP multi-chip package with the BISD are described as below:

[0059] (1) Performing flip-chip assembling, bonding or packaging: (a) First providing the interposer comprising the FISIP, the SISIP, micro copper pads, bumps or pillars and TSVs, the semiconductor IC chips (or COCs), and the VIE chips or components; then flip-chip assembling, bonding or packaging the semiconductor IC chips (or COCs) and the VIE chips or components to and on the interposer. The interposer is formed as described and specified above. The semiconductor IC chips comprise (i) the standard commodity FPGA chip, (ii) an auxiliary or supporting (AS) IC chip, wherein the auxiliary or supporting IC chip comprises a cryptography or security IC chip, I/O or control IC chip, power management IC chip, and/or Innovated ASIC or COT (abbreviated as IAC below) IC chip, The AS IC chips will be described or specified below, (iii) processing and/or computing IC chip, for example CPU, GPU, DSP, TPU, APU or ASIC chip, and/or (iv) memory IC chip, for example, the non-volatile NAND and/or NOR flash chip, and/or High Bandwidth DRAM or SRAM Memory (HBM) chip. The COCs are as described and specified above. All the semiconductor IC chips (or COCs) and the VIE chips or components to be flip-chip packaged in the multichip package comprise micro metal pads, pillars or bumps on their surface; (b) The micro metal pads, pillars or bumps of the semiconductor IC chips (or COCs) and the VIE chips or components are flip-chip assembled, bonded or packaged on or to corresponding micro copper pads, bumps or pillar on or of the interposer with the side or surface of the chip with transistors of the semiconductor IC chips faced down, or the side or surface of the COC with micro metal pads, pillars or bumps faced down. The backside of the silicon substrate of the chips (the side or surface without transistors) or the COCs (the side or surface without micro metal pads, pillars or bumps) is faced up; (c) Filling the spaces or gaps between the interposer and the semiconductor IC chips or COCs (and between micro copper bumps or pillars of the semiconductor IC chips (or COCs) and the interposer), and between the interposer and the VIE chips or components (and between micro metal pads, pillars or bumps of the VIE chips or components and the interposer) with an underfill material by, for example, a dispensing method using a dispenser.

• • [0060] (2) Applying a material, resin, or compound to fill the spaces or gaps between the semiconductor IC chips (or COCs), between the VIE chips or components, and between the semiconductor IC chips (or COCs) and the VIE chips or components, to cover the backside surfaces of the semiconductor IC chips (or COCs) and the VIE chips or components by methods, for example, spin-on coating, screen-printing, dispensing or molding in the wafer or panel format. The molding method includes the compress molding (using top and bottom pieces of molds) or the casting molding (using a dispenser). The material, resin, or compound used may be a polymer material includes, for example, polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer, or silicone. The polymer may be, for example, photosensitive polyimide/PBO PIMEL™ supplied by Asahi Kasei Corporation, Japan; or epoxy-based molding compounds, resins or sealants provided by Nagase ChemteX Corporation, Japan. Applying a CMP, polishing or grinding process to planarize the surface of the applied material, resin or compound, until a level where the backside surfaces of all TSVs of the VIE chips or components are fully exposed.
  • [0061] (3) Depositing an insulating dielectric layer (for example a polymer layer) on the top side (the opposite side of the side with interposer) of the multichip package; that is, on or over (i) the exposed backside of the semiconductor IC chips (or COCs), (ii) the exposed backside of the VIE chips or components and (iii) the spaces or gaps between the semiconductor IC chips (or COCs), between the VIE chips or components, and between the semiconductor IC chips (or COCs) and the VIE chips or components. Forming openings in the insulating dielectric layer to expose the top surfaces of the TSVs, TGVs or TPVs in the VIE chips or components.
  • [0062] (4) Forming a Backside metal Interconnection Scheme at the backside of the multichip-packaged logic drive or device (abbreviated as BISD in below) on or over the second insulating dielectric layer, and the exposed surfaces (of the TSVs, TGVs or TPVs in the VIE chips or components) in the openings in the second insulating dielectric layer. The BISD may comprise metal lines, traces, or planes in one or a plurality of interconnection metal layers, and is formed on or over the backsides of the semiconductor IC chips and the VIE chips or components, or, on or over the backsides of the COC and the VIE chips or components. The metal lines or traces of the interconnection metal layers of the BISD are over the SIC/COCs and the VIE chips or components and extend horizontally across the edges of the SIC/COCs or the VIE chips or components. The BISD may be formed using the same or similar process steps, materials and specification as in forming the BISD in the FOIT multichip package (with the FISD) described above. The BISD provides additional interconnection metal layer or layers at the top or the backside of the multichip package.
  • [0063] (5) Forming copper or nickel pads, copper pillars, or solder bumps on or over exposed surfaces of the top-most metal interconnection layer (of the BISD) at the bottom of openings in the top-most insulting dielectric layer of the BISD. The copper or nickel pads, copper pillars, or solder bumps in an area array at the top of the multichip package including at locations vertically over the backside of the SIC/COCs of the multichip package. The copper or nickel pads, copper pillars, or solder bumps are formed by performing an embossing electroplating copper process.
  • [0064] (6) Thinning the interposer to expose the surfaces of the metal vias (in the silicon substrate) at the backside of the interposer. A wafer or panel thinning process, for example, a CMP process, a polishing process or a wafer backside grinding process, may be performed to remove portion of the wafer or panel to make the wafer or panel thinner, in a wafer or panel process, to expose the surfaces of the metal vias (in the silicon substrate) at the backside of the interposer; the metal vias in the silicon substrate are therefore become through silicon vias (TSVs).
  • [0065] (7) (now turning the whole structure upside down) Depositing an insulating dielectric layer (for example a polymer layer) on the top side (the side of the side with interposer) of the multichip package, forming openings in the insulating dielectric layer to expose the top surfaces of TSVs in the silicon substrate of the interposer. Forming copper pads or pillars, or solder bumps on or over the exposed top surfaces of the TSVs in the interposer. (the side of the semiconductor IC chips with transistors is facing up, or the side of the COCs with micro metal pads, pillars or bumps is facing up) by performing an embossing electroplating copper process.
  • [0066] (8) Separating, cutting or dicing the molding material, including separating, cutting or dicing through materials or structures between two neighboring multichip packages. The material (for example, polymer) filling gaps between chips of two neighboring multichip packages is separated, cut or diced to from an individual unit of multichip package.

[0067] The BISD provides additional interconnection metal layer or layers at the top or the backside of the multichip package, and provides the copper or nickel pads, copper pillars, or solder bumps in an area array at the top of the multichip package including at locations vertically over the backside of the SIC/COCs of the multichip package, wherein the copper or nickel pads, copper pillars, or solder bumps are connected or coupled to a transistor of the SIC/COCs through the TSVs, TGVs or TPVs of the VIE chips or components. The TSVs, TGVs or TPVs of the VIE chips or components are used for connecting or coupling circuits or components (for example, the FISIP and/or SISIP of the interposer) at the frontside of the multichip to that (for example, the BISD) at the backside of the multichip package. A copper pad or pillar, or solder bump of the copper pads or pillars, or solder bumps at the bottom (the interposer side, that is, the front sides of SIC/COCs having micro metal pads, pillars or bumps are facing down) of the separated or diced multichip package may be vertically under a SIC/COCs of the SIC/COCs, and couple or connect (for signal, clock, power supply Vcc, or ground reference Vss) to a copper or nickel pad, copper pillar, or solder bump of the copper or nickel pads, copper pillars, or solder bumps vertically over the SIC/COC through a metal interconnect of the FISIP and/or SISIP of the interposer, the TSV, TGV or TPV of the VIE chip or component and a metal interconnect of the BISD, wherein the copper pad or pillar, or solder bump at the bottom of the separated or diced multichip package may couple to a transistor of the SIC/COC. Each separated or diced multichip package may comprise (a) a plurality of semiconductor IC chips and one or a plurality of VIE chips or components; (b) a plurality of COCs and one or a plurality of VIE chips or components: or, (c) one or a plurality of semiconductor IC chips, one or a plurality of COCs, and one or a plurality of VIE chips or components.

[0068] Another aspect of the disclosure provides a Chip-On-Interposer (COIP) with the interposer and the BISD for making or fabricating a single-chip package or single-COC package using the VIE chips or components. The single-chip package or single-COC package comprises the interposer and the BISD. The single-chip package may comprise only one semiconductor IC chip and at least one of the VIE chips or components; the single-COC package may comprise only one COC and at least one of the VIE chips or components. The single-chip package or single-COC package is formed using the same or similar process steps as forming the COIP multichip package with BISD as described and specified above, except:

• • [0069] (A) In Step (1), the semiconductor IC chips (or COCs) flip chip assembled to the interposer for a process batch may be of the same product or device of the semiconductor IC chip (or COC). For example, the semiconductor IC chips used in one wafer or panel process batch may be of only one of following products or devices: (i) the standard commodity FPGA chip, (ii) an auxiliary or supporting (AS) IC chip, wherein the auxiliary or supporting IC chip comprises a cryptography or security IC chip, I/O or control IC chip, power management IC chip, and/or Innovated ASIC or COT (abbreviated as IAC below) IC chip, The AS IC chips will be described or specified below, (iii) the processing or computing IC chip, for example CPU, GPU, DSP, TPU, APU or ASIC chip, or (iv) the memory IC chip, for example, the non-volatile NAND or NOR flash chip, or High Bandwidth DRAM or SRAM Memory (HBM) chip.
  • [0070] (B) In Step (8), separating, cutting or dicing the finished wafer or panel, to form a unit of single-chip package or single-COC package, wherein the unit of single-chip package (or single-COC package) may comprise only one semiconductor IC chip (or COC) and one or a plurality of VIE chips or components. The single-chip or single-COC package (SIC/COC) has copper pads or pillars, or solder bumps in an area array at the bottom (the side which the frontside of the SIC/COC with micro metal pads, pillars or bumps is facing), wherein the copper pads or pillars, or solder bumps connecting or coupling to the SIC/COC may be vertically under the SIC/COC. The single-chip or single-COC package has copper or nickel pads, copper pillars, or solder bumps in the area array at the top (the backside of the SIC/COC without micro metal pads, pillars or bumps). For an example, a copper pad or pillar, or solder bump of the copper pads or pillars, or solder bumps at the bottom (the interposer side, that is, the frontside of the SIC/COC with micro metal pads, pillars or bumps is facing down) of the separated or diced single-chip or single-COC package may couple or connect to a copper or nickel pad, copper pillar, or solder bump of the copper or nickel pads, copper pillars, or solder bumps on or over the exposed top surfaces of the TSVs, TGVs or TPVs of the VIE chips or components through a metal interconnect of the FISIP and/or SISIP of the interposer and a TSV, TGV or TPV of one of the VIE chips or components (for signal, clock, power supply Vcc and/or ground reference Vss), wherein the copper pad or pillar, or solder bump at the bottom of the separated or diced single-chip or single-COC package may be vertically under the SIC/COC, and couple to a transistor of the SIC/COC. For another example, a copper or nickel pad, copper pillar, or solder bump of the copper or nickel pads, copper pillars, or solder bumps on or over the exposed top surfaces of the TSVs, TGVs or TPVs of the VIE chips or components may couple or connect (for signal, clock, power supply Vcc and/or ground reference Vss) to the transistors of the SIC/COC through one of the TSVs, TGVs or TPVs in one of the VIE chips or components and a metal interconnect of the FISIP and/or SISIP of the interposer, for signal, clock, power supply Vcc and/or ground reference Vss.

[0071] Another aspect of the disclosure provides an Interconnection Substrate (IS) for flip-chip assembly or packaging in forming the multi-chip package. The multi-chip package is based on multiple-Chips (or COCs)-On-an-Interconnection-Substrate (COIS) flip-chip packaging method. The multi-chip package comprising one or a plurality of standard commodity FPGA chips may be used as a logic drive. The Interconnection Substrate (IS) in the COIS multi-chip package comprises: (1) Fineline Interconnection Bridges (FIB) comprising a silicon substrate with high density interconnects, metal vias and fine pitch metal pads, on or over the silicon substrate, for fan-out and interconnection between the semiconductor IC chips (or COCs), between the semiconductor IC chips (or COCs) and the VIE chips, between a semiconductor IC chip and a VIE chip or component, wherein the semiconductor IC chips (or COCs) and the VIE chips or components are flip-chip-assembled, bonded or packaged on or over the IS, (2) The Printed Circuit Board, for example, Ball-Grid-Array substrates (BGA), with lower density interconnects, metal vias and coarse metal pads, wherein the FIBs are embedded in the PCBs or BGAs. The PCBs or BGAs comprise bismaleimide triazine (BT) and/or Ajinomoto Build-up Film (ABF). The semiconductor IC chips or COCs (SIC/COCs), and the VIE chips or components to be flip-chip assembled, bonded or packaged to the IS are mentioned, described and specified above. The semiconductor IC chips comprise (i) the standard commodity FPGA chip, (ii) the dedicated control chip, (iii) the dedicated I/O chip, (iv) the dedicated control and I/O chip, (v) the ASIC chip, (vi) the processing and/or computing IC chip, for example CPU, GPU, DSP, TPU, APU and/or ASIC chip, and/or (vii) the memory IC chip, for example, the non-volatile NAND and/or NOR flash chip, and/or High Bandwidth DRAM or SRAM Memory (HBM) chip. The Fineline Interconnection Bridge (FIB) embedded in PCBs or BGAs comprises: (1) a silicon substrate; (2) a First Interconnection Scheme on or of the Interconnection Bridge (FISIB) on or over the silicon substrate formed by the damascene copper electroplating process, same or similar to that of the FISIP of the interposer described and specified above; (3) a Second Interconnection Scheme of the Interconnection Bridge (SISIB) on or over the FISIB structure, formed by the embossing copper electroplating process, same or similar to that of the SISIP of the interposer described and specified above; (4) micro copper pads, pillars or bumps on or over the SISIB.

[0072] The Interconnect Substrate (IS) is a Printing Circuit Board, for example, a BGA, based on the process steps of forming printing circuit boards. One or a plurality of Fineline Interconnection Bridges (FIBs) specified and described above are embedded in an IS in processes of forming the IS. The IS comprises: (1) a base structure, for example, a 5-2-5 BGA, two metal layers of the hard core (comprising BT), and five build-up layers (comprising ABF) on each side of the hard core with openings, dips or holes therein; (2) the FIB embedded or housed in the openings, dips or holes in the base structure; (3) multiple metal interconnection layers on or over the base structure and the FIBs; (4) a plurality of copper pads, pillars or bumps on or over a top surface of the top-most interconnection metal layer of IS.

[0073] Another aspect of the disclosure provides a method for forming the multichip package in a COIS multi-chip package comprising the semiconductor IC chips (or COCs) and one or a plurality of the VIE chips or components. The multichip package comprising one or a plurality of standard commodity of the FPGA chips may be used as the logic drive. The COIS multi-chip package uses the IS comprising the FISIB, the SISIB, copper pads or pillars, or solder bumps based on a flip-chip assembled multi-chip packaging technology and process. The process steps for forming the COIS multi-chip package are described as below:

• • [0074] (1) Performing flip-chip assembling, bonding or packaging: (a) First providing the interconnection substrate (IS) comprising the FISIS, the SISIB, copper pads or pillars at the top, semiconductor IC chips or COCs (SIC/COCs), and the VIE chips or components; then flip-chip assembling, bonding or packaging the SIC/COC, and the VIE chips or components to the copper pads or pillars at the top of the IS. The IS is formed as described and specified above. The SIC/COCs and the VIE chips or components to be assembled, bonded or packaged to the IS include the semiconductor IC chips or COCs mentioned, described and specified above. The semiconductor IC chips comprise (i) the standard commodity FPGA chip, (ii) an auxiliary or supporting (AS) IC chip, wherein the auxiliary or supporting IC chip comprises a cryptography or security IC chip, I/O or control IC chip, power management IC chip, and/or Innovated ASIC or COT (abbreviated as IAC below) IC chip, The AS IC chips will be described or specified below, (iii) processing and/or computing IC chip, for example CPU, GPU, DSP, TPU, APU or ASIC chip, and/or (iv) memory IC chip, for example, the non-volatile NAND and/or NOR flash chip, and/or High Bandwidth DRAM or SRAM Memory (HBM) chip. The COCs are as described and specified above. All semiconductor IC chips (or COCs) and the VIE chips or components to be flip-chip packaged in the multichip package comprise micro metal pads, pillars or bumps; (b) The SIC/COC and the VIE chips or components are flip-chip assembled, bonded or packaged on or to corresponding copper pads or pillars on the top of the IS with the side or surface of the semiconductor chip with transistors faced down, and the side or surface of the COC with the micro metal pads, pillars or bumps faced down. That is, the high density, small size micro metal pads, pillars or bumps (HDB) on the IC chips (or COCs) and the VIE chips or components are flip-chip assembled to the corresponding high density, small size copper pads or pillars (HDP) on the top of the IS; and, the low density, large size micro metal pads, pillars or bumps (LDB) on the IC chips (or COCs) and the VIE chips or components are flip-chip assembled to the corresponding low density, large size copper pads or pillars (LDP) on the top of the IS. The backside of the silicon substrate of the semiconductor IC chips (the side or surface without transistors) is faced up, or the backside of the silicon substrate of the COCs (the side or surface without micro metal pads, pillars or bumps) is faced up; (c) Filling an underfill material in the gaps (i) between the IS and the IC chips (or COCs) (and between micro copper pillars or bumps of the IC chips (or COCs) on the IS) (ii) between the IS and the VIE chips or components (and between micro copper pillars or bumps of the VIE chips or components on the IS).
  • [0075] (2) Applying a material, resin, or compound to fill the gaps or spaces (i) between the semiconductor IC chips (or COCs), (ii) between the VIE chips or components and (iii) between the semiconductor IC chip (or COC) and the VIE chip or component, and cover the backside surfaces of semiconductor IC chips (or COCs) and the VIE chips or components by methods, for example, spin-on coating, screen-printing, dispensing or molding in the wafer or panel format. The material, resin, or compound used may be a polymer material includes, for example, polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer, or silicone. The polymer may be, for example, photosensitive polyimide/PBO PIMEL™ supplied by Asahi Kasei Corporation, Japan; or epoxy-based molding compounds, resins or sealants provided by Nagase ChemteX Corporation, Japan. Applying a CMP, polishing or grinding process to planarize the surface of the applied material, resin or compound. The CMP, or grinding process is performed until a level where the backside surfaces of all of the semiconductor IC chips (or COCs) and the VIE chips or components are fully exposed, and the backside surfaces of TSVs, TGVs or TPVs of the VIE chips or components are fully exposed.
  • [0076] (3) Depositing an insulating dielectric layer (for example a polymer layer) on the top side (the opposite side of the side with IS) of the multichip package, forming openings in the insulating dielectric layer, exposing the top (backside) surfaces of the TSVs, TGVs or TPVs in the VIE chips or components, and forming copper or nickel pads, copper pillars, or solder bumps on or over the exposed top surfaces of the TSVs, TGVs or TPVs in the VIE chips or components, by performing an embossing electroplating copper process.
  • [0077] (4) Forming a Backside metal Interconnection Scheme at the backside of the multichip-packaged logic drive or device (abbreviated as BISD in below) on or over the second insulating dielectric layer, and the exposed surfaces (of the TSVs, TGVs or TPVs in the VIE chips or components) in the openings in the second insulating dielectric layer. The BISD may comprise metal lines, traces, or planes in one or a plurality of interconnection metal layers, and is formed on or over the backsides of the semiconductor IC chips and the VIE chips or components, or, on or over the backsides of the COC and the VIE chips or components. The metal lines or traces of the interconnection metal layers of the BISD are over the SIC/COCs and the VIE chips or components and extend horizontally across the edges of the SIC/COCs or the VIE chips or components. The BISD may be formed using the same or similar process steps, materials and specification as in forming the BISD in the FOIT multichip package (with the FISD) described above. The BISD provides additional interconnection metal layer or layers at the top or the backside of the multichip package.
  • [0078] (5) Forming copper or nickel pads, copper pillars, or solder bumps on or over exposed surfaces of the top-most metal interconnection layer (of the BISD) at the bottom of openings in the top-most insulting dielectric layer of the BISD. The copper or nickel pads, copper pillars, or solder bumps in an area array at the top of the multichip package including at locations vertically over the backside of the SIC/COCs of the multichip package. The copper or nickel pads, copper pillars, or solder bumps are formed by performing an embossing electroplating copper process.
  • [0079] (6) (now turning the whole structure upside down) Forming copper pads or pillars, or solder bumps on or over the exposed top surfaces of the metal contacts of the IS, (here side of the semiconductor IC chips with transistors are facing up, or the side of the micro metal pads, pillars or bumps of COCs are facing up) by performing an embossing electroplating copper process.
  • [0080] (7) Separating, cutting or dicing the finished panel, including separating, cutting or dicing through materials or structures between two neighboring multichip packaged logic drives. The material (for example, polymer) filling gaps or spaces between two neighboring multichip packaged logic drives is separated, cut or diced to form individual unit of logic drives.

[0081] The BISD provides additional interconnection metal layer or layers at the top or the backside of the multichip package, and provides the copper or nickel pads, copper pillars, or solder bumps in an area array at the top of the multichip package including at locations vertically over the backside of the SIC/COCs of the multichip package, wherein the copper or nickel pads, copper pillars, or solder bumps are connected or coupled to a transistor of the SIC/COCs through the TSVs, TGVs or TPVs of the VIE chips or components. The TSVs, TGVs or TPVs of the VIE chips or components are used for connecting or coupling circuits or components (for example, the FISIB and/or SISIB of the IS) at the frontside of the multichip to that (for example, the BISD) at the backside of the multichip package. A copper pad or pillar, or solder bump of the copper pads or pillars, or solder bumps at the bottom (the IS side, that is, the front sides of SIC/COCs having micro metal pads, pillars or bumps are facing down) of the separated or diced multichip package may be vertically under a SIC/COCs of the SIC/COCs, and couple or connect (for signal, clock, power supply Vcc, or ground reference Vss) to a copper or nickel pad, copper pillar, or solder bump of the copper or nickel pads, copper pillars, or solder bumps vertically over the SIC/COC through a metal interconnect of the FISIB and/or SISIB of the IS, the TSV, TGV or TPV of the VIE chip or component and a metal interconnect of the BISD, wherein the copper pad or pillar, or solder bump at the bottom of the separated or diced multichip package may couple to a transistor of the SIC/COC. Each separated or diced multichip package may comprise (a) a plurality of semiconductor IC chips and one or a plurality of VIE chips or components; (b) a plurality of COCs and one or a plurality of VIE chips or components: or, (c) one or a plurality of semiconductor IC chips, one or a plurality of COCs, and one or a plurality of VIE chips or components.

[0082] Another aspect of the disclosure provides a Chip-On-Interconnection-Substrate Technology (COIS) with IS and BISD for making or fabricating a single-chip package or single-COC package using the VIE chips or components. The single-chip package comprises the IS and BISD. The single-chip package single-chip package is formed using the same or similar process steps as forming the multichip package with the IS and BISD as described and specified above, except:

[0083] (A) In Step (1), the semiconductor IC chips (or COC) flip chip bonded or assembled to the IS for a process batch may be of the same product or device of the semiconductor IC chip (or COC). For example, the semiconductor IC chips used in one wafer or panel process batch may be of only one of following products or devices: (i) the standard commodity FPGA chip, (ii) an auxiliary or supporting (AS) IC chip, wherein the auxiliary or supporting IC chip comprises a cryptography or security IC chip, I/O or control IC chip, power management IC chip, and/or Innovated ASIC or COT (abbreviated as IAC below) IC chip, The AS IC chips will be described or specified below, (iii) the processing or computing IC chip, for example CPU, GPU, DSP, TPU, APU or ASIC chip, or (iv) the memory IC chip, for example, the non-volatile NAND or NOR flash chip, or High Bandwidth DRAM or SRAM Memory (HBM) chip.

[0084] (B) In Step (7), separating, cutting or dicing the finished wafer or panel, to form a unit of single-chip package or single-COC package, wherein the unit of single-chip package may comprise only one semiconductor IC chip and one or a plurality of VIE chips or components, and single-chip package may comprise only one COC and one or a plurality of VIE chips or components. The single-chip or single-COC package (SIC/COC) has copper pads or pillars, or solder bumps in an area array at the bottom (the side which the frontside of the SIC/COC with micro metal pads, pillars or bumps is facing), wherein the copper pads or pillars, or solder bumps connecting or coupling to the SIC/COC may be vertically under the SIC/COC. The single-chip or single-COC package has copper or nickel pads, copper pillars, or solder bumps in the area array at the top (the backside of the SIC/COC without micro metal pads, pillars or bumps). For an example, a copper pad or pillar, or solder bump of the copper pads or pillars, or solder bumps at the bottom (the IS side, that is, the frontside of the SIC/COC with micro metal pads, pillars or bumps is facing down) of the separated or diced single-chip or single-COC package may couple or connect to a copper or nickel pad, copper pillar, or solder bump of the copper or nickel pads, copper pillars, or solder bumps on or over the exposed top surfaces of the TSVs, TGVs or TPVs of the VIE chips or components through a metal interconnect of the FISIB and/or SISIB of the IS and a TSV, TGV or TPV of one of the VIE chips or components (for signal, clock, power supply Vcc and/or ground reference Vss), wherein the copper pad or pillar, or solder bump at the bottom of the separated or diced single-chip or single-COC package may be vertically under the SIC/COC, and couple to a transistor of the SIC/COC. For another example, a copper or nickel pad, copper pillar, or solder bump of the copper or nickel pads, copper pillars, or solder bumps on or over the exposed top surfaces of the TSVs, TGVs or TPVs of the VIE chips or components may couple or connect (for signal, clock, power supply Vcc and/or ground reference Vss) to the transistors of the SIC/COC through one of the TSVs, TGVs or TPVs in one of the VIE chips or components and a metal interconnect of the FISIB and/or SISIB of the IS, for signal, clock, power supply Vcc and/or ground reference Vss.

[0085] Another aspect of the disclosure provides the multichip package with a plurality of the semiconductor IC chips (or COCs) and one or a plurality of the VIE chips or components for use in a 3D stacked chip package, wherein the multichip package may be in a standard format, layout or having a standard size. The standard multichip package is formed using one of the methods described and specified above: (i) the FOIT multichip package with the FISD and BISD, (ii) the FOIT multichip package with the FOISD and BISD, (iii) the COIP multichip package using the interposer and with the BISD, or (iv) the COIS multichip package using the IS (comprising FIBs) and with the BISD. The standard multichip package may be in a shape of square or rectangle, with a certain widths, lengths and thicknesses; and/or with a standard layout of the locations of the copper pads or pillars, or solder bumps at its bottom, and a standard layout of the locations of the copper or nickel pads, copper pillars, or solder bumps at its top. An industry standard may be set for the shape and dimensions of the standard multichip package. For example, the standard shape of the standard multichip package may be a square, with a width smaller than or equal to 4 mm, 7 mm, 10 mm, 12 mm, 15 mm, 20 mm, 25 mm, 30 mm, 35 mm or 40 mm, and having a thickness thinner than or equal to 0.03 mm, 0.05 mm, 0.1 mm, 0.3 mm, 0.5 mm, 1 mm, 2 mm, 3 mm, 4 mm, or 5 mm. Alternatively, the standard shape of the standard multichip package may be a rectangle, with a width smaller than or equal to 3 mm, 5 mm, 7 mm, 10 mm, 12 mm, 15 mm, 20 mm, 25 mm, 30 mm, 35 mm or 40 mm, and a length smaller than or equal to 5 mm, 7 mm, 10 mm, 12 mm, 15 mm, 20 mm, 25 mm, 30 mm, 35 mm, 40 mm, 45 mm or 50 mm; and having a thickness thinner than or equal to 0.03 mm, 0.05 mm, 0.1 mm, 0.3 mm, 0.5 mm, 1 mm, 2 mm, 3 mm, 4 mm, or 5 mm. The copper pads or pillars, or solder bumps at the bottom (the side the semiconductor IC chips with transistors is facing, or the side the COCs with micro metal pads, pillars or bumps is facing) may be in an area array with a standard layout, wherein the locations of the copper pads or pillars, or solder bumps are at standard coordinates in a horizontal plane. The copper or nickel pads, copper pillars, or solder bumps at the top (the side the semiconductor IC chips without transistors is facing, or the side the COCs without micro metal pads, pillars or bumps is facing) of the standard multichip package may be also in the area array with a standard layout, wherein the locations of the copper or nickel pads, copper pillars, or solder bumps are at standard coordinates in a horizontal plane, wherein the copper or nickel pads, copper pillars, or solder bumps may be at locations vertically over the semiconductor IC chips (or COCs) and may be connecting or coupling to the frontside of the semiconductor IC chips (or COCs). Each of all or more than 10, 20, 30, 50, or 100 copper pads or pillars, or solder bumps at the bottom of a standard multichip package has a copper or nickel pads, copper pillars, or solder bumps at the top of the standard multichip package vertically over it. The standard layout or locations of the copper pads or pillars, or solder bumps at the bottom of a standard multichip package are the same as the standard layout or locations of the copper or nickel pads, copper pillars, or solder bumps at the top of the standard multichip package; therefore the bottom of a standard multichip package may be stacked on the top of another standard multichip package.

[0086] Another aspect of the disclosure provides the standard single-chip package or single-COC package with a semiconductor IC chip (or COC) and one or a plurality of the VIE chips or components for use in the 3D stacked chip package, wherein the single-chip package or single-COC package may be in a standard format, layout or having a standard size. The standard single-chip package is formed using one of the methods described and specified above: (i) the FOIT single-chip package or single-COC package with the FISD and BISD, (ii) the FOIT single-chip package or single-COC package with the FOISD and BISD, (iii) the COIP single-chip package or single-COC package using the interposer and with the BISD, or (iv) the COIS single-chip package or single-COC package using the IS (comprising FIBs) and with the BISD. The standard single-chip package or single-COC package may be in a shape of square or rectangle, with a certain widths, lengths and thicknesses; and/or with a standard layout of the locations of the copper pads or pillars, or solder bumps at its bottom and with a standard layout of the locations of the copper or nickel pads, copper pillars, or solder bumps at its top. An industry standard may be set for the shape and dimensions of the standard single-chip package. For example, the standard shape of the standard single-chip package or single-COC package may be a square, with a width smaller than or equal to 3 mm, 4 mm, 7 mm, 10 mm, 12 mm, 15 mm, 20 mm, 25 mm, 30 mm, 35 mm or 40 mm, and having a thickness greater than or equal to 0.03 mm, 0.05 mm, 0.1 mm, 0.3 mm, 0.5 mm, 1 mm, 2 mm, 3 mm, 4 mm, or 5 mm. Alternatively, the standard shape of the standard single-chip package or single-COC package may be a rectangle, with a width smaller than or equal to 2 mm, 3 mm, 5 mm, 7 mm, 10 mm, 12 mm, 15 mm, 20 mm, 25 mm, 30 mm, 35 mm or 40 mm, and a length smaller than or equal to 4 mm, 5 mm, 7 mm, 10 mm, 12 mm, 15 mm, 20 mm, 25 mm, 30 mm, 35 mm, 40 mm, 45 mm or 50 mm; and having a thickness thinner than or equal to 0.03 mm, 0.05 mm, 0.1 mm, 0.3 mm, 0.5 mm, 1 mm, 2 mm, 3 mm, 4 mm, or 5 mm. The copper pads or pillars, or solder bumps at the bottom (the side the semiconductor IC chips with transistors is facing down, or the side the COCs with micro metal pads, pillars or bumps is facing down) may be in an area array with a standard layout, wherein the locations of the copper pads or pillars, or solder bumps are at standard coordinates in a horizontal plane. The copper or nickel pads or pillars, or solder bumps at the top (the side the semiconductor IC chips without transistors is facing up, or the side the COCs without micro metal pads, pillars or bumps is facing up) of the standard single chip package may be may be also in an area array with a standard layout, wherein the locations of the copper or nickel pads, copper pillars, or solder bumps are at standard coordinates in a horizontal plane, wherein the copper or nickel pads, copper pillars, or solder bumps may be at locations vertically over the semiconductor IC chip (or COC) and may be connecting or coupling to the frontside of the semiconductor IC chip (or COC). Each of all or more than 10, 20, 30, 50, or 100 copper pads or pillars, or solder bumps at the bottom of a standard multichip package has a copper or nickel pad, copper pillar, or solder bump at the top of the standard multichip package vertically over and aligned with it. The standard layout or locations of the copper pads or pillars, or solder bumps at the bottom of a standard multichip package are the same as the standard layout or locations of the copper or nickel pads, copper pillars, or solder bumps at the top of the standard multichip package; therefore the bottom of a standard multichip package may be stacked on the top of another standard multichip package.

[0087] Another aspect of the disclosure provides the standard single-chip package (or single-COC package) and multichip package for use in the 3D chip stacked package, wherein the standard single-chip package (or single-COC package) and the multichip package are as described and specified above. The standard layout or locations are the same for: (i) the copper pads or pillars, or solder bumps at the bottom of a standard multi-chip package; (ii) the copper pads or pillars, or solder bumps at the bottom of a standard single-chip package or single-COC package, (iii) the copper or nickel pads, copper pillars, or solder bumps at the bottom of the standard multi-chip package; and (iv) the copper or nickel pads, copper pillars, or solder bumps at the bottom of the standard single-chip package or single-COC package. Therefore, the bottom of a standard single-chip package or single-COC package may be stacked on the top of a standard multi-chip package to form the 3D stacked chip package. Alternatively, the bottom of a standard multi-chip package may be stacked on the top of a standard single-chip package or single-COC package to form the 3D stacked chip package.

[0088] Another aspect of the disclosure provides a multichip package comprising a plurality of semiconductor IC chips and one or more VIE chips or components disposed on a same horizontal plane, wherein the plurality of semiconductor IC chips deliver or achieve a specific function, task, operation or purpose collectively. The multichip package may be the FOIT multichip package based on the FISD interconnection scheme, the FOIT multichip package based on the FOISD interconnection scheme, the COIP multichip package based on the FISIP and/or SISIP interconnection schemes of the interposer, or the COIS multichip package based on the IS interconnection scheme (comprising the FIBs). The multichip package described and specified above may comprise a plurality of semiconductor IC chips, wherein the plurality of semiconductor IC chips may be of different types of products and designs. The different types of semiconductor IC chips in the multichip package provide, collectively, a certain function, operation or purpose for a certain application, innovation or task. For example, the multichip package may comprise: (i) two or more than two FPGA chips for enlargement of the number of logic blocks or cells; (ii) a FPGA chip and a CPU chip for flexibility (provided by the FPGA chip) and programmability (provided by the CPU chip); (iii) a FPGA chip and a GPU chip for flexibility (provided by the FPGA chip) and efficiency (provided by the GPU chip); (iv) a CPU chip and a GPU chip for programmability (provided by the CPU chip) and efficiency (provided by the GPU chip); or (v) a FPGA chip, a CPU chip and a GPU chip for flexibility (provided by the FPGA chip), programmability (provided by the CPU chip) and efficiency (provided by the GPU chip), wherein the multichip package may optionally comprise, in addition, a NAND and/or NOR flash non-volatile memory chip, a High-Bandwidth DRAM Memory (HBM) chip, a High-Bandwidth SRAM Memory (HBM) chip, a High-Bandwidth (HBM) Magnetoresistive Random Access Memory (MRAM) chip, and/or a High-Bandwidth (HBM) Resistive Random Access Memory (RRAM) chip. The multichip package may comprise the FPGA chip or the plurality of FPGA chips, and the NAND and/or NOR flash non-volatile memory chip, and/or, the MRAM or RRAM chip, wherein the NAND and/or NOR flash non-volatile memory chip, and/or, the MRAM or RRAM chip may be used for configuring functions of the FPGA chip or the plurality of FPGA chips, for example, configuring (i) the programmable logic functions or operations, or (ii) the programmable interconnection. For configuring the programmable logic functions or operations, a first data stored in a non-volatile memory cell of the NAND and/or NOR flash non-volatile memory chip, and/or, the MRAM or RRAM chip is used for configuring the FPGA chip to perform a logic operation, wherein the FPGA chip comprises a static-random-access-memory (SRAM) cell of a Look-Up-Table (LUT), configured to store a second data associated with the first data, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having a data associated with the second data, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation. For the programmable interconnection, a third data stored in a non-volatile memory cell of the NAND and/or NOR flash non-volatile memory chip, and/or, the MRAM or RRAM chip is used for configuring the FPGA chip to perform programmable interconnection, wherein the FPGA chip comprises a static-random-access-memory (SRAM) cell configured to store a fourth data associated with the third data, a switch having an input point for an input data associated with the fourth data, and first and second programmable interconnects coupling to the switch, wherein the switch is configured to control, in accordance with the input data, connection between the first and second programmable interconnects. In this case the 3D stacked chip package may be used as the logic drive.

[0089] Another aspect of the disclosure provides a 3D stacked chip package comprising first and second chip packages (each comprising a single-chip package or a multichip package), wherein the first and second chip packages each comprises one or a plurality of semiconductor IC chips and one or a plurality of VIE chips or components, wherein the plurality of semiconductor IC chips deliver or achieve a specific function, task, operation or purpose collectively. The second chip package may be stacked on the first chip package to form the 3D stacked chip package based on a package-on-package assembly method. Alternatively, the first chip package may be stacked on the second chip package to form the 3D stacked chip package. The first and second chip packages may be the FOIT chip package based on the FISD interconnection scheme, the FOIT chip package based on the FOISD interconnection scheme, the COIP chip package based on the FISIP and/or SISIP interconnection schemes of the interposer, or the COIS chip package based on the IS interconnection scheme (comprising the FIBs). The first and second chip packages described and specified above may comprise one or a plurality of semiconductor IC chips. The different types of semiconductor IC chips in the 3D stacked chip package provide, collectively, a certain function, operation or purpose for a certain application, innovation or task. For example, the first chip package may comprise one or more following logic products or devices: (i) the standard commodity FPGA chip, (ii) an auxiliary or supporting (AS) IC chip, wherein the auxiliary or supporting IC chip comprises a cryptography or security IC chip, I/O or control IC chip, power management IC chip, and/or Innovated ASIC or COT (abbreviated as IAC below) IC chip, The AS IC chips will be described or specified below, (iii) processing and/or computing IC chip, for example CPU, GPU, DSP, TPU, APU or ASIC chip. The second chip package may comprise one or more following memory products or devices: (i) a NAND and/or NOR flash non-volatile memory chip, (ii) a High-Bandwidth DRAM Memory (HBM) chip, (iii) a High-Bandwidth SRAM Memory (HBM) chip, (iv) a High-Bandwidth (HBM) Magnetoresistive Random Access Memory (MRAM) chip, and/or (v) a High-Bandwidth (HBM) Resistive Random Access Memory (RRAM) chip. The different types of semiconductor IC chips in the first and second chip packages of the 3D stacked chip package may provide, collectively, a certain function, operation or purpose for a certain application, innovation or task, through the through vias in the one or the plurality of VIE chips or components. The first chip package may comprise a FPGA chip and the second chip package may comprise a NAND and/or NOR flash non-volatile memory chip, a High-Bandwidth (HBM) Magnetoresistive Random Access Memory (MRAM) chip, and/or a High-Bandwidth (HBM) Resistive Random Access Memory (RRAM) chip, wherein the NAND and/or NOR flash non-volatile memory chip, and/or, the MRAM or RRAM chip in the second chip package may be used for configuring functions of the FPGA chip in the first chip package, for example, configuring (i) the programmable logic functions or operations, or (ii) the programmable interconnection, of the FPGA chip in the first chip package. For configuring the programmable logic functions or operations, a first data stored in a non-volatile memory cell of the NAND and/or NOR flash non-volatile memory chip, and/or, the MRAM or RRAM chip is used, through the through vias in the one or the plurality of VIE chips or components, for configuring the FPGA chip to perform a logic operation, wherein the FPGA chip comprises a static-random-access-memory (SRAM) cell of a Look-Up-Table (LUT), configured to store a second data associated with the first data (through the through vias in the one or the plurality of VIE chips or components), and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having a data associated with the second data, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation. For the programmable interconnection, a third data stored in a non-volatile memory cell of the NAND and/or NOR flash non-volatile memory chip, and/or, the MRAM or RRAM chip is used, through the through vias in the one or the plurality of VIE chips or components, for configuring the FPGA chip to perform programmable interconnection, wherein the FPGA chip comprises a static-random-access-memory (SRAM) cell configured to store a fourth data associated with the third data (through the through vias in the one or the plurality of VIE chips or components), a switch having an input point for an input data associated with the fourth data, and first and second programmable interconnects coupling to the switch, wherein the switch is configured to control, in accordance with the input data, connection between the first and second programmable interconnects. In this case the 3D stacked chip package may be used as the logic drive.

[0090] Another aspect of the disclosure provides a logic drive in a 3D stacked chip package comprising a standard commodity FPGA IC chip, an NVM (non-volatile memory) IC chip, and an auxiliary or supporting (AS) IC chip, wherein the auxiliary or supporting IC chip comprises a cryptography or security IC chip, I/O or control IC chip, power management IC chip, and/or Innovated ASIC or COT (abbreviated as IAC below) IC chip. The 3D stacked chip package is a FPGA/AS 3D stacked chip package based on the chip packages (single-chip packages or multi-chip packages using the FOIT, COIP or COIS technology) as described and specified above.

[0091] The 3D stacked chip package comprising first and second chip packages (comprising a single-chip packages or a multichip packages), wherein the first and second chip packages comprise one or a plurality of semiconductor IC chips and one or more VIE chips or components. The second chip package may be stacked on the first chip package to form the 3D stacked chip package based on a package-on-package assembly method. Alternatively, the first chip package may be stacked on the second chip package to form the 3D stacked chip package. The first and second chip packages may be the FOIT chip package based on the FISD interconnection scheme, the FOIT chip package based on the FOISD interconnection scheme, the COIP chip package based on the FISIP and/or SISIP interconnection schemes of the interposer, or the COIS chip package based on the IS interconnection scheme (comprising the FIBs). As an example, when the 3D stacked chip package comprises the first chip package and the second chip package on or over the first chip package, wherein the first chip package may comprise one or a plurality of FPGA IC chips and one or more VIE chips or components, and the second chip package may comprise one or a plurality of semiconductor IC chips of the AS IC chips. The one or the plurality of semiconductor IC chips of the AS IC chips couples to one or a plurality of FPGA IC chips through the through vias in the one or the plurality of VIE chips or components. Alternatively, the second chip package may be replaced by a bare-die chip or chips comprising one or a plurality of semiconductor IC chips of the AS IC chips, wherein the bare-die chip or chips are flip-chip assembled on the first chip package comprising one or a plurality of FPGA IC chips and one or more VIE chips or components; and wherein an underfill material may be filled in between the first chip package and the AS chip or chips. As another example, when the 3D stacked chip package comprises the first chip package and the second chip package, wherein the first chip package is on or over the second chip package, wherein the first chip package may comprise one or a plurality of FPGA IC chips, and the second chip package may comprise one or a plurality of semiconductor IC chips of the AS IC chips and one or more VIE chips or components. The one or the plurality of semiconductor IC chips of the AS IC chips couples to one or a plurality of FPGA IC chips through the through vias in the one or the plurality of VIE chips or components. Alternatively, the first chip package may be replaced by a bare-die chip or chips comprising one or a plurality of FPGA IC chips, wherein the bare-die chip or chips (FPGA IC chip or chips) are flip-chip assembled on the second chip package comprising one or a plurality of semiconductor IC chips of the AS IC chips; and wherein an underfill material may be filled in between the bare-die FPGA IC chip or chips and the second chip package comprising the AS chip or chips. The different types of the AS IC chips in the 3D stacked chip package provide a certain function, operation or purpose collectively with the one or the plurality of FPGA IC chips in the 3D stacked chip package for a certain application, innovation or task.

[0092] Another aspect of the disclosure provides a logic drive in a 3D stacked chip package comprising a standard commodity FPGA IC chip, an NVM (non-volatile memory) IC chip, and an auxiliary or supporting (AS) IC chip, wherein the auxiliary or supporting IC chip is a cryptography or security IC chip. The 3D stacked chip package is a FPGA/AS 3D stacked chip package based on the chip packages (single-chip packages or multi-chip packages using the FOIT, COIP or COIS technology) as described and specified above. The NVM IC chip is packaged using the same method as that of the AS IC chip. The FPGA IC chip may be configured to perform a logic function by configuring data or information in the memory cells thereof (for example, SRAM cells) of LUTs for logic operations, and/or of configurable cross-point switches for programmable interconnections in the FPGA IC chips, wherein the configuring data or information in the memory cells of the FPGA IC chip may be stored, saved and backup in the non-volatile memory cells of the NVM IC chip in the same 3D stacked chip package. When the power supply of the logic drive is turned on, the configuring data or information in the non-volatile memory cells of the NVM IC chip is passing or transferring to the SRAM memory cells of the FPGA IC chip through the TSVs, TGVs or TPVs of the VIE chip component in the 3D stacked chip package. The logic drive may comprise cryptography or security circuits (encryption/decryption circuits and cryptography key or password) for protection of the developed configuration data or information (related to the innovation, architecture, algorithm and/or applications) for the FPGA IC chip in the logic drive, wherein the encryption/decryption circuits is controlled and secured by the cryptography key or password. In some cases, the cryptography key or password is stored in non-volatile memory cells comprising the FGMOS (Floating-Gate MOS) NVM cells, MRAM cells, RRAM cells, FRAM cells, e-fuses or anti-fuses on the FPGA IC chip. While in this aspect of disclosure, the cryptography or security circuits are included in the auxiliary or supporting IC chip, that is the cryptography or security IC chip. The cryptography or security IC chip comprises non-volatile memory cells comprising the FGMOS NVM cells, MRAM cells, RRAM cells, FRAM cells, e-fuses or anti-fuses for saving or storing the cryptography key or password for security purpose. The cryptography or security IC chip couples to the FPGA IC chip through the TSVs, TGVs or TPVs of the VIE chip or component in the 3D stacked chip package. The auxiliary or supporting IC chip (the cryptography or security IC chip) may be designed and implemented using a technology node more mature or less advanced than the FPGA IC chip. For example, the FPGA IC chip may be designed and implemented using a technology node more advanced than 20 nm or 10 nm, while the cryptography or security IC chip may be designed and implemented using a technology node less advanced than 20 nm or 30 nm. The semiconductor technology node used to fabricate the FPGA IC chip is more advanced than that used to fabricate the cryptography or security IC chip. For example, the FPGA IC chip may be designed and implemented using FINFET or GAAFET (Gate-All-Around Field-Effect-Transistor) transistors, while the cryptography or security IC chip may be designed and implemented using conventional planar MOSFET transistors. The purposes, functions and specifications of the FPGA IC chip, NVM IC chip and the cryptography or security IC chip in the FPGA/AS 3D stacked chip package are as described above. The logic drive in the FPGA/AS 3D stacked chip package becomes a nonvolatile programmable device with security when comprising (i) the FPGA IC chip; (ii) the NVM IC chip to store, save and backup the configuration data for configuring the standard commodity FPGA IC chip; and (iii) the cryptography or security IC chip comprising the cryptography or security circuits (including the encryption/decryption circuit and the cryptography key or password).

[0093] Another aspect of the disclosure provides a logic drive in a 3D stacked chip package comprising a standard commodity FPGA IC chip, an NVM IC chip, and an auxiliary or supporting IC chip, wherein the auxiliary or supporting IC chip is an I/O or control IC chip. The I/O or control circuits on the FPGA IC chip (as described and specified above) may be separated from the FPGA IC chip to form the auxiliary or supporting IC chip, that is the I/O or control IC chip. The FPGA IC chip, NVM IC chip, and auxiliary or supporting IC chip (the I/O or control IC chip) may be packaged in a FPGA/AS 3D stacked chip package, as described and specified above. The 3D stacked chip package is a FPGA/AS 3D stacked chip package based on the chip packages (single-chip packages or multi-chip packages using the FOIT, COIP or COIS technology) as described and specified above. The NVM IC chip is packaged using the same method as that of the AS IC chip. The purposes, functions and specifications of the FPGA IC chip, NVM IC chip and the I/O or control IC chip in the multichip package are as described above.

[0094] When the I/O or control circuits on the FPGA IC chip (as described and specified above) are separated from the FPGA IC chip to form the auxiliary or supporting IC chip (the I/O or control IC chip), the FPGA IC chip may become a standard commodity product. None or minimal area of the standard commodity FPGA IC chip is used for the control or I/O circuits, for example, less than 15%, 10%, 5%, 2% or 1% area (not counting the seal ring of the scribe line and the dicing area of the chip; that means, only including area up to the inner boundary of the seal ring) is used for the control or IO circuits; or, none or minimal transistors of the standard commodity FPGA IC chip are used for the control or I/O circuits, for example, less than 15%, 10%, 5%, 2% or 1% of the total number of transistors are used for the control or I/O circuits. All or most area of the standard commodity FPGA IC chip is used for (i) logic blocks comprising logic gate arrays, computing units or operators, and/or Look-Up-Tables (LUTs) and multiplexers, and/or (ii) programmable interconnection. For example, greater than 85%, 90%, 95% or 99% area of the standard commodity FPGA IC chip (not counting the seal ring and the dicing area of the chip; that means, only including area up to the inner boundary of the seal ring) is used for logic blocks, and/or programmable interconnection; or, all or most transistors of the standard commodity FPGA IC chip are used for logic blocks or repetitive arrays, and/or programmable interconnection, for example, greater than 85%, 90%, 95% or 99% of the total number of transistors are used for logic blocks, and/or programmable interconnection.

[0095] The auxiliary or supporting chip (the I/O or control IC chip) is designed, implemented and fabricated using varieties of semiconductor technology nodes or generations, including old or matured technology nodes or generations, for example, a semiconductor node or generation less advanced than or equal to, or above or equal to 20 nm, 30 nm, 40 nm, 50 nm, 90 nm, 130 nm, 250 nm, 350 nm, or 500 nm. The semiconductor technology node or generation used in the I/O or control chip is 1, 2, 3, 4, 5 or greater than 5 nodes or generations older, more matured or less advanced than that used in the standard commodity FPGA IC chip packaged in the same logic drive. Transistors used in the I/O or control IC chip may be a Fully Depleted Silicon-on-insulator (FDSOI) MOSFET, a Partially Depleted Silicon-on-insulator (PDSOI) MOSFET or a conventional planar MOSFET. Transistors used in the I/O or control IC chip may be different from that used in the standard commodity FPGA IC chip packaged in the same logic drive; for example; the I/O or control IC chip may use the conventional planar MOSFET, while the standard commodity FPGA IC chip packaged in the same logic drive may use the FINFET or GAAFET. The power supply voltage (Vcc) used in the I/O or control IC chip may be greater than or equal to 1.5V, 2.0 V, 2.5V, 3 V, 3.3V, 4V, or 5V, while the power supply voltage (Vcc) used in the standard commodity FPGA IC chip packaged in the same logic drive may be smaller than or equal to 1.8V, 1.5V, or 1 V. The power supply voltage used in the I/O or control IC chip may be higher than that that used in the standard commodity FPGA IC chip packaged in the same logic drive; for example, the I/O or control IC chip may use a power supply of 3.3V, while the standard commodity FPGA IC chip packaged in the same logic drive may use a power supply voltage of 1V; or the I/O or control IC chip may use a power supply of 2.5V, while the standard commodity FPGA IC chip packaged in the same logic drive may use a power supply of 0.75V. The gate oxide (physical) thickness of the Field-Effect-Transistors (FETs) used in the I/O or control IC chip may be thicker than or equal to 5 nm, 6 nm, 7.5 nm, 10 nm, 12.5 nm, or 15 nm, while the gate oxide (physical) thickness of FETs used in the standard commodity FPGA IC chip packaged in the same logic drive may be thinner than 4.5 nm, 4 nm, 3 nm or 2 nm. The gate oxide (physical) thickness of FETs used in the I/O or control IC chip may be thicker than that used in the standard commodity FPGA IC chip packaged in the same logic drive; for example, the I/O or control IC chip may use a FET having a gate oxide with a (physical) thickness of 10 nm, while the standard commodity FPGA IC chip packaged in the same logic drive may use a FET having a gate oxide with a (physical) thickness of 3 nm; or the I/O or control IC chip may use a FET having a gate oxide with a (physical) thickness of 7.5 nm, while the standard commodity FPGA IC chip packaged in the same logic drive may use a FET having a gate oxide with a (physical) thickness of 2 nm. The I/O or control IC chip provides input and output circuits, and ESD protection circuits for the logic drive. The I/O or control IC chip provides (i) large drivers or receivers, or I/O circuits for connecting or coupling to external or outside (of the logic drive) circuits, and (ii) small drivers or receivers, or I/O circuits for connecting or coupling to IC chips in or of the logic drive. The large drivers or receivers, or I/O circuits for connecting or coupling to external or outside (of the logic drive) circuits have driving capability, loading, output capacitance or input capacitance lager or bigger than that of the small drivers or receivers, or I/O circuits for connecting or coupling to IC chips in or of the logic drive. The FPGA IC chip provides only the small drivers or receivers, or I/O circuits for connecting or coupling to the small drivers or receivers, or I/O circuits on the I/O or control IC chip and other IC chips in or of the logic drive. The driving capability, loading, output capacitance, or input capacitance of each of the large I/O drivers or receivers, or I/O circuits for connecting or coupling to external or outside (of the logic drive) circuits may be between 2 pF and 100 pF, 2 pF and 50 pF, 2 pF and 30 pF, 2 pF and 20 pF, 2 pF and 15 pF, 2 pF and 10 pF, or 2 pF and 5 pF; or larger than 2 pF, 5 pF, 10 pF, 15 pF or 20 pF. Each of the large input/output (I/O) circuits may have an I/O power efficiency greater than 3, 5 or 10 pico-Joules per bit, per switch or per voltage swing. The driving capability, loading, output capacitance, or input capacitance of each of the small I/O drivers or receivers, or I/O circuits for connecting or coupling to IC chips in or of the logic drive may be between 0.1 pF and 5 pF, 0.1 pF and 2 pF or 0.1 pF and 1 pF; or smaller than 10 pF, 5 pF, 3 pF, 2 pF or 1 pF. Each of the small input/output (I/O) circuits may have an I/O power efficiency smaller than 0.5 pico-Joules per bit, per switch or per voltage swing, or between 0.01 and 0.5 pico-Joules per bit, per switch or per voltage swing. The size of ESD protection device on the I/O or control IC chip is larger than that on the standard commodity FPGA IC chip in the same logic drive. The size of the ESD device in the large I/O circuits on the I/O or control IC chip may be between 0.5 pF and 20 pF, 0.5 pF and 15 pF, 0.5 pF and 10 pF, 0.5 pF and 5 pF or 0.5 pF and 2 pF; or larger than 0.5 pF, 1 pF, 2 pF, 3 pF, 5 pF or 10 pF. The size of the ESD device in the small I/O circuits on the I/O or control IC chip and the standard commodity FPGA IC chip may be between 0.1 pF and 2 pF, or 0.1 pF and 1 pF; or smaller than 0.5 pF, 1 pF, or 2 pF. For example, a bi-directional (or tri-state) I/O pad or circuit on the I/O or control IC chip may be used for the large I/O drivers or receivers, or I/O circuits for connecting or coupling to external or outside (of the logic drive) circuits, and may comprise an ESD circuit, a receiver, and a driver, and each may have an input capacitance, output capacitance or driving capability between 2 pF and 100 pF, 2 pF and 50 pF, 2 pF and 30 pF, 2 pF and 20 pF, 2 pF and 15 pF, 2 pF and 10 pF, or 2 pF and 5 pF; or larger than 2 pF, 5 pF, 10 pF, 15 pF or 20 pF. The bi-directional (or tri-state) I/O pad or circuit used for the large I/O drivers or receivers, or I/O circuits may have an I/O power efficiency greater than 3, 5 or 10 pico-Joules per bit, per switch or per voltage swing. For example, a bi-directional (or tri-state) I/O pad or circuit on the I/O or control IC chip and the standard commodity FPGA IC chip may be used for the small I/O drivers or receivers, or I/O circuits for connecting or coupling to IC chips in or of the logic drive, and may comprise an ESD circuit, a receiver, and a driver, and may have an input capacitance, output capacitance or driving capability between 0.1 pF and 2 pF or 0.1 pF and 2 pF; or smaller than 2 pF or 1 pF. The bi-directional (or tri-state) I/O pad or circuit used for the small I/O drivers or receivers, or I/O circuits may have an I/O power efficiency smaller than 0.5 pico-Joules per bit, per switch or per voltage swing, or between 0.01 and 0.5 pico-Joules per bit, per switch or per voltage swing.

[0096] The I/O or control IC chip in the multichip package of the standard commodity logic drive may comprise a buffer and/or driver circuits for (i) downloading the programing codes from the non-volatile memory cells on the non-volatile IC chip in the logic drive to the 5 T or 6 T SRAM cells of the programmable interconnection on the standard commodity FPGA IC chip through the TSVs, TGVs or TPVs of the VIE chip or component. The programming codes from the non-volatile IC chip in the logic drive may go through the buffer or driver in or of the I/O or control IC chip before getting into the 5 T or 6 T SRAM cells of the programmable interconnection on the standard commodity FPGA IC chips. The buffer in or of the I/O or control IC chip may latch the data from the non-volatile IC chip and increase the bit-width of the data. For example, the data bit-width (in a SATA standard) from the non-volatile IC chip is 1 bit, and the buffer may latch the 1 bit data in each of the plurality of SRAM cells in the buffer on the non-volatile IC chip, and output the data stored or latched in the plurality of SRAM cells (on the I/O or control IC chip) in parallel and simultaneously to increase the data bit-width; for example, equal to or greater than 4, 8, 16, 32, or 64 data bit-width. For another example, the data bit-width (in a PCIe standard) from the non-volatile IC chip is 32 bits, the buffer on the non-volatile IC chip may increase the data bit-width to equal to or greater than 64, 128, or 256 data bit-width. The driver in or of the I/O or control IC chip may further amplify the data signals from the non-volatile IC chip; (ii) downloading data from the non-volatile memory cells on the non-volatile IC chip in the logic drive to the 5 T or 6 T SRAM cells of the LUTs on the standard commodity FPGA IC chip through the TSVs, TGVs or TPVs of the VIE chip component. The data from the non-volatile IC chip in the logic drive may go through the buffer or driver in or of the I/O or control IC chip before getting into the 5 T or 6 T SRAM cells of LUTs on the standard commodity FPGA IC chip. The buffer in or of the I/O or control IC chip may latch the data from the non-volatile IC chip and increase the bit-width of the data. For example, the data bit-width (in a SATA standard) from the non-volatile IC chip is 1 bit, the buffer on the non-volatile IC chip may latch the 1 bit data in each of the plurality of SRAM cells in the buffer, and output the data stored or latched in the plurality of SRAM cells (on the I/O or control IC chip) in parallel and simultaneously to increase the data bit-width; for example, equal to or greater than 4, 8, 16, 32, or 64 data bit-width. For another example, the data bit-width (in a PCIe standard) from the non-volatile IC chip is 32 bits, the buffer may increase the data bit-width to equal to or greater than 64, 128, or 256 data bit-width. The driver in or of the I/O or control IC chip may further amplify the data signals from the non-volatile IC chip.

[0097] The I/O or control IC chip in the multichip package of the standard commodity logic drive may comprise I/O circuits or pads (and micro metal pads, pillars or bumps) for I/O ports comprising one or more than one (2, 3, 4, or more than 4) Universal Serial Bus (USB) ports, one or more than one wide-bit I/O ports, one or more than one SerDes ports, one or more than one thunderbolt ports, one or more than one Serial Advanced Technology Attachment (SATA) ports, one or more than one Peripheral Components Interconnect express (PCIe) ports, one or more IEEE 1394 ports, one or more Ethernet ports, one or more than one audio ports or serial ports, RS-232 or COM (communication) ports, wireless transceiver I/O ports, and/or Bluetooth transceiver I/O ports. The I/O or control IC chip may comprise I/O circuits or pads (or micro copper pillars or bumps) for connecting or coupling to Serial Advanced Technology Attachment (SATA) ports, Peripheral Components Interconnect express (PCIe) ports, wide-bit I/O ports for communicating, connecting or coupling with the memory storage drive.

[0098] Another aspect of the disclosure provides a logic drive in a 3D stacked chip package comprising a standard commodity FPGA IC chip, an NVM IC chip, and an auxiliary or supporting IC chip, wherein the auxiliary or supporting IC chip is a power management IC chip. The power management IC chip, comprising a voltage regulator, provides power supply voltages for the FPGA IC chip through the TSVs, TGVs or TPVs of the VIE chip component. The FPGA IC chip, NVM IC chip, and auxiliary or supporting IC chip may be packaged in a FPGA/AS 3D stacked chip package as described and specified above. The 3D stacked chip package is a FPGA/AS 3D stacked chip package based on the chip packages (single-chip packages or multi-chip packages using the FOIT, COIP or COIS technology) as described and specified above. The NVM IC chip is packaged using the same method as that of the AS IC chip. The auxiliary or supporting IC chip (the power management IC chip) may be designed and implemented using a technology node more mature or less advanced than the FPGA IC chip. For example, the FPGA IC chip may be designed and implemented using a technology node more advanced than 20 nm or 10 nm, while the power management IC chip may be designed and implemented using a technology node less advanced than 20 nm or 30 nm. The semiconductor technology node used to fabricate the FPGA IC chip is more advanced than that used to fabricate the power management IC chip. For example, the FPGA IC chip may be designed and implemented using FINFET or GAAFET transistors, while the power management IC chip may be designed and implemented using conventional planar MOSFET transistors. The purposes, functions and specifications of the FPGA IC chip, NVM IC chip and the power management IC chip in the 3D stacked chip package are as described above.

[0099] Another aspect of the disclosure provides a logic drive in a 3D stacked chip package comprising a standard commodity FPGA IC chip, an NVM IC chip, and an auxiliary or supporting IC chip, wherein the auxiliary or supporting IC chip is an Innovated ASIC or COT (abbreviated as IAC below) IC chip. The FPGA IC chip, NVM IC chip and IAC IC chip, may be packaged in a FPGA/AS 3D stacked chip package as described and specified above, wherein the IAC IC chip couples to the standard commodity FPGA IC chip through the TSVs, TGVs or TPVs in the VIE chip component. The 3D stacked chip package is a FPGA/AS 3D stacked chip package based on the chip packages (single-chip packages or multi-chip packages using the FOIT, COIP or COIS technology) are as described and specified above. The NVM IC chip is packaged using the same method as that of the AS IC chip. As described above, the innovators may implement their innovation using the standard commodity FPGA IC chip (fabricated in the advanced technology nodes more advanced than 20 nm or 10 nm). The IAC IC chip, in addition to the standard commodity FPGA IC chip, provides innovators further freedom to implement their innovation with further customized or personalized capability using less expensive technology nodes less advanced than 20 nm or 30 nm. The semiconductor technology node used to fabricate the FPGA IC chip is more advanced than that used to fabricate the IAC IC chip. For example, the IAC IC chip provides innovators an affordable expense for realizing or implementing their innovated Intellectual Property (IP) circuits, Application Specific circuits, analog circuits, mixed-mode signal circuits, Radio-Frequency (RF) circuits, and/or transmitter, receiver, transceiver circuits, etc. The purposes, functions and specifications of the FPGA IC chip, NVM IC chip and the IAC IC chip in the multichip package are as described above.

[0100] The IAC IC chip is designed, implemented and fabricated using varieties of semiconductor technology nodes or generations, including old or matured technology nodes or generations, for example, less advanced than or equal to, or more mature than 20 nm or 30 nm, and for example using the technology node of 22 nm, 28 nm, 40 nm, 90 nm, 130 nm, 180 nm, 250 nm, 350 nm or 500 nm. The semiconductor technology node or generation used in the IAC IC chip is 1, 2, 3, 4, 5 or greater than 5 nodes or generations older, more matured or less advanced than that used in the standard commodity FPGA IC chip packaged in the same logic drive. Transistors used in the IAC IC chip may be a FINFET, a Fully Depleted Silicon-on-insulator (FDSOI) MOSFET, a Partially Depleted Silicon-On-Insulator (PDSOI) MOSFET or a conventional planar MOSFET. Transistors used in the IAC IC chip may be different from that used in the standard commodity FPGA IC chip packaged in the same logic drive; for example, the IAC IC chip may use the conventional planar MOSFET, while the standard commodity FPGA IC chip packaged in the same logic drive may use the FINFET or GAAFET; or the IAC IC chip may use the Fully Depleted Silicon-on-insulator (FDSOI) MOSFET, while the standard commodity FPGA IC chips packaged in the same logic drive may use the FINFET. Since the IAC IC chip in this aspect of disclosure may be designed and fabricated using older or less advanced technology nodes or generations, its NRE cost is cheaper than or less than that of the current ASIC or COT IC chip designed and fabricated using an advanced IC technology node or generation. The NRE cost for designing a current ASIC or COT IC chip using an advanced IC technology node or generation, for example, more advanced than or below 20 nm or 10 nm, may be more than US $5M, US $10M, US $20M or even exceeding US $50M, or US $100M. The cost of a photo mask set for an ASIC or COT IC chip at the 16 nm technology node or generation is over US $2M, US $5M, or US $10M. Implementing the same or similar innovation and/or application using the logic drive including the IAC IC chip designed and fabricated using more matured or less advanced technology nodes or generations may reduce NRE cost down to less than US $10M, US $7M, US $5M, US $3M or US $1M. Compared to the implementation by developing the current logic ASIC or COT IC chip, the NRE cost of developing the IAC IC chip for use in the standard commodity logic drive to achieve the same or similar innovation and/or application may be reduced by a factor of 2, 5, 10, 20, or 30.

[0101] Another aspect of the disclosure provides a logic drive in a 3D stacked chip package comprising a standard commodity FPGA IC chip, a NVM IC chip, and one or a plurality of auxiliary or supporting IC chips, wherein the one or the plurality of auxiliary or supporting IC chips provide one or more than one of any combined functions provided by the cryptography or security IC chip, the I/O or control IC chip, the power management IC chip, and/or the IAC IC chip, as described and specified above. The functions of cryptography or security, I/O or control, the power management and the IAC may be combined in one auxiliary or supporting IC chip, or partitioned into two or three auxiliary or supporting IC chips, or separated in four auxiliary or supporting IC chips. Any of the functions of cryptography or security, I/O or control, the power management and the IAC not included in the one or the plurality of auxiliary or supporting IC chips may be included and kept in the standard commodity FPGA IC chip in the logic drive. The FPGA IC chip, NVM IC chip, and the one or the plurality of auxiliary or supporting IC chips may be packaged in a FPGA/AS 3D stacked chip package as described and specified above, wherein the one or the plurality of auxiliary or supporting IC chips couple to the FPGA IC chip through the TSVs, TGVs or TPVs in the VIE chip or component in the 3D stacked chip package. The purposes, functions and specifications of the FPGA IC chip, NVM IC chip and the one or a plurality auxiliary or supporting IC chips in the 3D stacked chip package are as described above.

[0102] Another aspect of the disclosure provides the FPGA/AS 3D stacked chip package, as described and specified above, for use as the logic drive. The logic drive may be in 3 types of the 3D stacked chip packages: (i) the first type of the 3D stacked chip package comprises a standard commodity FPGA IC chip and a NVM IC chip, wherein the standard commodity FPGA IC chip may comprise circuits providing functions of cryptography or security, I/O or control, power management and/or the IAC; (ii) the second type of the 3D stacked chip package comprises the standard commodity FPGA IC chip, the NVM IC chip and an auxiliary or supporting IC chip, wherein the auxiliary or supporting IC chip is one of the cryptography or security IC chip, the I/O or control IC chip, the power management IC chip, or the IAC IC chip, as described and specified above. For this second type, functions of cryptography or security, I/O or control, the power management and the IAC not included in the auxiliary or supporting IC chip may be included and kept in the standard commodity FPGA IC chip in the logic drive; or (iii) the third type of the 3D stacked chip package comprises the standard commodity FPGA IC chip, the NVM IC chip and a plurality of auxiliary or supporting IC chips, wherein the plurality of auxiliary or supporting IC chips provide one or more than one of any combined functions provided by the cryptography or security IC chip, the I/O or control IC chip, the power management IC chip, and/or the IAC IC chip, as described and specified above. For the third type, functions of cryptography or security, I/O or control, the power management and the IAC not included in the plurality of auxiliary or supporting IC chips may be included and kept in the standard commodity FPGA IC chip in the logic drive. The functions of cryptography or security, I/O or control, the power management and the IAC may be combined in one auxiliary or supporting IC chip, or partitioned into two or three auxiliary or supporting IC chips, or separated in four auxiliary or supporting IC chips.

[0103] Another aspect of the disclosure provides a standardized commodity logic drive in the chip package or 3D stacked chip package comprising (i) one or a plurality of the standard commodity FPGA chips, (ii) one or a plurality of auxiliary or supporting (AS) IC chips comprising a cryptography or security IC chip, I/O or control IC chip, power management IC chip, and/or Innovated ASIC or COT (abbreviated as IAC below) IC chip, (iii) one or a plurality of the processing or computing IC chips comprising a CPU, GPU, DSP, TPU, APU and/or ASIC chip, or (iv) one or a plurality of the memory IC chips or CSPs (Chip-Scale-Package) comprising a non-volatile NAND or NOR flash chip, or High Bandwidth DRAM or SRAM Memory (HBM) chip or HBM stacked CSP (SCSP). The standardized commodity logic drive is for use in different algorithms, architectures and/or applications requiring logic, computing and/or processing functions by field programming, wherein data stored in the one or the plurality of non-volatile memory IC chips are used for configuring the one or the plurality of FPGA IC chips in the same chip package. The chip package comprises the single-COC package or multichip package, as described and specified above. The 3D stacked chip package is as described or specified above. Uses of the standardized commodity logic drive is analogues to uses of a standardized commodity data storage device or drive, for example, solid-state disk (drive), data storage hard disk (drive), data storage floppy disk, Universal Serial Bus (USB) flash drive, USB drive, USB stick, flash-disk, or USB memory, and differs in that the latter has memory functions for data storage, while the former has logic functions for processing and/or computing.

[0104] Another aspect of the disclosure provides a method to reduce Non-Recurring Engineering (NRE) expenses for implementing (i) an innovation, (ii) an innovation process or application, and/or (iii) accelerating workload processing or application in semiconductor IC chips by using the standardized commodity logic drive, FIG. 51. The standardized commodity logic drive may comprise: (i) one or a plurality of the standard commodity FPGA chips, (ii) one or a plurality of auxiliary or supporting (AS) IC chips comprising a cryptography or security IC chip, I/O or control IC chip, power management IC chip, and/or Innovated ASIC or COT (abbreviated as IAC below) IC chip, (iii) one or a plurality of the processing or computing IC chips comprising a CPU, GPU, DSP, TPU, APU and/or ASIC chip, or (iv) one or a plurality of the memory IC chips or CSPs (Chip-Scale-Package) comprising a non-volatile NAND or NOR flash chip, or High Bandwidth DRAM or SRAM Memory (HBM) chip or HBM stacked CSP (SCSP). The standardized commodity logic drive may be packaged in a chip package or 3D stacked chip package, wherein the chip package comprises the single-COC package or multichip package, as described and specified above. The 3D stacked chip package is as described or specified above. A person, user, or developer with an innovation and/or an application concept or idea or an aim for accelerating workload processing may purchase the standardized commodity logic drive and develop or write software codes or programs to load into the standardized commodity logic drive to implement his/her innovation and/or application concept or idea; wherein said innovation and/or application (maybe abbreviated as innovation below) comprises (i) innovative algorithms and/or architectures of computing, processing, learning and/or inferencing, and/or (ii) innovative and/or specific applications. The developed software codes or programs related to the innovation are used for configuring the one or a plurality of FPGA IC chips in the chip package or 3D stacked chip package, and may be stored in the one or a plurality of non-volatile memory IC chips in the same chip package or 3D stacked chip package. With non-volatile memory cells in the one or a plurality of non-volatile memory IC chips in the chip package or 3D stacked chip package, the logic drive may be used as an alternative of the ASIC chip fabricated using advanced technology nodes. The standard commodity logic drive comprises one or a plurality of FPGA IC chips fabricated by using advanced technology nodes or generations more advanced than 20 nm or 10 nm. The innovation is implemented in the logic drive by configuring the hardware of FPGA IC chips by altering the data in the 5 T or 6 T SRAM cells of the programmable interconnection (configurable switches including pass/no-pass switching gates and multiplexers) and/or programmable logic circuits, cells or blocks (including LUTs and multiplexers) therein using the data stored in the non-volatile memory cells in the one or a plurality of non-volatile memory IC chips or the one or a plurality of FPGA IC chips in the chip package or 3D stacked chip package. Compared to the implementation by developing a logic ASIC or COT IC chip, implementing the same or similar innovation and/or application using the logic drive may reduce the NRE cost down to smaller than US $1M by developing a software and installing it in the purchased or rented standard commodity logic drive. The aspect of the disclosure inspires the innovation and lowers the barrier for implementing the innovation in IC chips designed and fabricated using an advanced IC technology node or generation, for example, a technology node or generation more advanced than or below 20 nm or 10 nm.

[0105] Another aspect of the disclosure provides a “public innovation platform” by using logic drives for innovators to easily and cheaply implement or realize their innovation (algorithms, architectures and/or applications) in semiconductor IC chips fabricated using advanced IC technology nodes more advanced than 20 nm or 10 nm, and for example, using a technology node of 16 nm, 10 nm, 7 nm, 5 nm or 3 nm, FIG. 51. In early days, 1990's, innovators could implement their innovation (algorithms, architectures and/or applications) by designing IC chips and fabricate their designed IC chips in a semiconductor foundry fab using technology nodes at 1 μm, 0.8 μm, 0.5 μm, 0.35 μm, 0.18 μm or 0.13 μm, at a cost of about several hundred thousands of US dollars. The IC foundry fab was then the “public innovation platform”. However, when IC technology nodes migrate to a technology node more advanced than 20 nm or 10 nm, and for example to the technology node of 16 nm, 10 nm, 7 nm, 5 nm or 3 nm, only a few giant system or IC design companies, not the public innovators, can afford to use the semiconductor IC foundry fab. It costs about or over 5 million US dollars to develop and implement an IC chip using these advanced technology nodes. The semiconductor IC foundry fab is now not “public innovation platform” anymore, it is “club innovation platform” for club innovators only. The concept of the disclosed logic drives, comprising standard commodity FPGA IC chips, provides public innovators “public innovation platform” back to semiconductor IC industry again; just as in 1990's. The innovators can implement or realize their innovation (algorithms, architectures and/or applications) by using logic drives (comprising FPGA IC chips fabricated using advanced than 20 nm or 10 nm technology nodes) and writing software programs in common programing languages, for example, C, Java, C++, C #, Scala, Swift, Matlab, Assembly Language, Pascal, Python, Visual Basic, PL/SQL or JavaScript languages, at a cost of less than 500K or 300K US dollars. The innovators can install their developed software using their own standard commodity logic drives or rented standard commodity logic drives in data centers or clouds through networks.

[0106] Another aspect of the disclosure provides a method to change the current logic ASIC or COT IC chip business into a commodity logic IC chip business, like the current commodity DRAM, or commodity NAND flash memory IC chip business, by using the standardized commodity logic drive. Since the performance, power consumption, and engineering and manufacturing costs of the standardized commodity logic drive may be better than that of the ASIC or COT IC chip for a same innovation (algorithms, architectures and/or applications) or an aim for accelerating workload processing, the standardized commodity logic drive may be used as an alternative for designing an ASIC or COT IC chip. The current logic ASIC or COT IC chip design, manufacturing and/or product companies (including fabless IC design and product companies, IC foundry or contracted manufactures (may be product-less), and/or vertically-integrated IC design, manufacturing and product companies) may become companies like the current commodity DRAM, or NAND flash memory IC chip design, manufacturing, and/or product companies; or like the current DRAM module design, manufacturing, and/or product companies; or like the current flash memory module, flash USB stick or drive, or flash solid-state drive or disk drive design, manufacturing, and/or product companies.

[0107] Another aspect of the disclosure provides the standardized commodity logic drive, wherein a person, user, customer, or software developer, or algorithm/architecture/application developer may purchase the standardized commodity logic drive and write software codes to program the logic drive for his/her desired algorithms, architectures and/or applications, for example, in algorithms, architectures and/or applications of Artificial Intelligence (AI), machine learning, deep learning, big data, Internet Of Things (IOT), Virtual Reality (VR), Augmented Reality (AR), car electronics, Graphic Processing (GP), Digital Signal Processing (DSP), Micro Controlling (MC), and/or Central Processing.

[0193] While certain embodiments are depicted in the drawings, one skilled in the art will appreciate that the embodiments depicted are illustrative and that variations of those shown, as well as other embodiments described herein, may be envisioned and practiced within the scope of the present application.

[0194] Illustrative embodiments are now described. Other embodiments may be used in addition or instead. Details that may be apparent or unnecessary may be omitted to save space or for a more effective presentation. Conversely, some embodiments may be practiced without all of the details that are disclosed.

[0195] A vertical-through-via (VTV) connector is provided with multiple vertical through vias (VTVs) for vertical connection to transmit signals or clocks or deliver power or ground in a vertical direction. The vertical-through-via (VTV) connector may be of a first or second type mentioned as below:

[0196] FIGS. 1A and 1B are schematically cross-sectional views showing first and second types of vertical-through-via (VTV) connectors for a first alternative for a first case in accordance with an embodiment of the present application. FIGS. 1C and 1D are schematically cross-sectional views showing first and second types of vertical-through-via (VTV) connectors for a first alternative for a second case in accordance with an embodiment of the present application. FIGS. 1E and 1F are schematically cross-sectional views showing first and second types of vertical-through-via (VTV) connectors for a first alternative for a third case in accordance with an embodiment of the present application. In a first alternative, referring to each of FIGS. 1A, 1C and 1E, a first type of vertical-through-via (VTV) connectors 467 may include (1) a semiconductor substrate 2, i.e., silicon substrate, (2) an insulating dielectric layer 12 on the semiconductor substrate 2, wherein the insulating dielectric layer 12 may include a silicon-oxide layer having a thickness between 0.1 and 2 μm, and wherein multiple blind holes 2a may be formed in the insulating dielectric layer 12 and semiconductor substrate 2, and each of the blind holes 2a may have a depth between 30 μm and 2,000 μm and a diameter or largest transverse dimension between 2 μm and 20 μm or between 4 μm and 10 μm, and (3) multiple through silicon vias (TSVs) 157 each in one of the blind holes 2a, wherein each of the through silicon vias (TSVs) 157 may vertically extend in one of the blind holes 2a in the semiconductor substrate 2 and through the insulating dielectric layer 12. Each of the through silicon vias (TSVs) 157 may include (1) an insulating lining layer 153, such as a layer of thermally grown silicon oxide (SiO₂), a layer of CVD silicon nitride (Si₃N₄) or a combination thereof, on a sidewall and bottom of one of the blind holes 2a, (2) a copper layer 156 electroplated in said one of the blind holes 2a, wherein the copper layer 156 may have a top surface coplanar with a top surface of the insulating dielectric layer 12, (3) an adhesion layer 154, such as a layer of titanium (Ti) or titanium nitride (TiN) having a thickness between 1 nm to 50 nm, on the insulating lining layer 153, between the insulating lining layer 153 and copper layer 156 and at a sidewall and bottom of the copper layer 156, and (4) a seed layer 155, such as a layer of copper having a thickness between 3 nm and 200 nm, between the adhesion layer 154 and copper layer 156 and at a sidewall and bottom of the copper layer 156. Each of the through silicon vias (TSVs) 157 may be used as a vertical through via (VTV) 358 for a dedicated vertical path. Each of the vertical through vias (VTVs) 358 formed by the through silicon vias (TSVs) may have a depth between 30 μm and 200 μm and a largest transverse dimension, such as diameter or width, between 2 μm and 20 μm or between 4 μm and 10 μm.

[0197] Referring to each of FIGS. 1A, 1C and 1E, each of the first type of vertical-through-via (VTV) connectors 467 may further include a passivation layer 14 on a top surface of the insulating dielectric layer 12. The passivation layer 14 may include a mobile ion-catching layer or layers, for example, a combination of silicon nitride, silicon oxynitride, and/or silicon carbon nitride layer or layers deposited by a chemical vapor deposition (CVD) process. For example, the passivation layer 14 may include a silicon-nitride layer having a thickness of more than 0.3 micrometers. Alternatively, the passivation layer 14 may include a polymer layer, such as polyimide, having a thickness between 1 and 5 micrometers. Next, multiple openings 14a may be formed in the passivation layer 14 and each of the openings 14a may expose the copper layer 156 of one of the through silicon vias (TSVs) 157. Each of the openings 14a may have a transverse dimension d, from a top view, between 0.5 and 20 micrometers or between 20 and 200 micrometers. The shape of the opening 14a from a top view may be a circle, and the diameter of the circle-shaped opening 14a may be between 0.5 and 20 micrometers or between 20 and 200 micrometers. Alternatively, the shape of the opening 14a from a top view may be a square, and the width of the square-shaped opening 14a may be between 0.5 and 20 micrometers or between 20 and 200 micrometers. Alternatively, the shape of the opening 14a from a top view may be a polygon, such as hexagon or octagon, and the polygon-shaped opening 14a may have a width between 0.5 and 20 micrometers or between 20 and 200 micrometers. Alternatively, the shape of the opening 14a from a top view may be a rectangle, and the rectangle-shaped opening 14a may have a shorter width between 0.5 and 20 micrometers or between 20 and 200 micrometers.

[0198] Referring to each of FIGS. 1A, 1C and 1E, each of the first type of vertical-through-via (VTV) connectors 467 may further include multiple micro-bumps or micro-pads 34, i.e., metal bumps, pads or conductive interconnects, each on the copper layer 156 of one of the through silicon vias (TSVs) 157 at a bottom of one of the openings 14a in the passivation layer 14. The micro-bumps or micro-pads 34 may be of various types. A first type of micro-bump or micro-pad 34 may include (1) an adhesion layer 26a, such as titanium (Ti) or titanium nitride (TiN) layer having a thickness between 1 nm and 50 nm, on the copper layer 156 of the through silicon vias (TSVs) 157, (2) a seed layer 26b, such as copper, on its adhesion layer 26a and (3) a copper layer 32 having a thickness between 1 μm and 60 μm on its seed layer 26b.

[0199] Alternatively, a second type of micro-bump or micro-pad 34 may include the adhesion layer 26a, seed layer 26b and copper layer 32 as mentioned above, and may further include, as seen in FIG. 1B, a tin-containing solder cap 33 made of tin or a tin-silver alloy having a thickness between 1 μm and 50 μm on its copper layer 32.

[0200] Alternatively, a third type of micro-bump or micro-pad 34 may be a thermal compression bump, including the adhesion layer 26a and seed layer 26b as mentioned above, and may further include, as seen in any of FIGS. 16A, 18A, 28A, 29A, 35A and 36A, a copper layer 37 having a thickness t3 between 2 μm and 20 μm and a largest transverse dimension w3, such as diameter in a circular shape, between 1 μm and 25 μm on its seed layer 26b and a solder cap 38 made of a tin-silver alloy, a tin-gold alloy, a tin-copper alloy, a tin-indium alloy, indium or tin, which has a thickness between 1 μm and 15 μm and a largest transverse dimension, such as diameter in a circular shape, between 1 μm and 15 μm on its copper layer 37. A pitch between neighboring two of the third type of micro-bumps or micro-pads 34 may be between 5 and 30 micrometers or between 10 and 25 micrometers.

[0201] Alternatively, a fourth type of micro-bump or micro-pad 34 may be a thermal compression pad, including the adhesion layer 26a and seed layer 26b as mentioned above, and may further include, as seen in FIG. 18A, a copper layer 48 having a thickness t2 between 1 μm and 20 μm or between 2 μm and 10 μm and a largest transverse dimension w2, such as diameter in a circular shape, between 5 μm and 50 μm, on its seed layer 26b and a solder cap 49 made of a tin-silver alloy, a tin-gold alloy, a tin-copper alloy, a tin-indium alloy, indium, tin or gold, which has a thickness between 0.1 μm and 5 μm on its copper layer 48. A pitch between neighboring two of the fourth type of micro-bumps or micro-pads 34 may be between 5 and 30 micrometers or between 10 and 25 micrometers.

[0202] In the first alternative, a second type of vertical-through-via (VTV) connector 467 as seen in FIG. 1B, 1D or 1F is similar to the first type of vertical-through-via (VTV) connector 467 as illustrated in FIG. 1A, 1C or 1E respectively, but has none of the passivation layer 14 and micro-bumps or micro-pads 34 as illustrated in FIG. 1A, 1C or 1E and the insulating dielectric layer 12 of the second type of vertical-through-via (VTV) connector 467 as seen in each of FIGS. 1B, 1D and 1F may act as an insulating bonding layer 52.

[0203] In the first alternative, for the first case, referring to FIGS. 1A and 1B, a pitch Wp between each neighboring two of the vertical through vias (VTVs) 358 in the semiconductor substrate 2 may range from 20 to 150 micrometers or from 40 to 100 micrometers or may be smaller than 50, 40 or 30 micrometers; and a space W_sptsv between each neighboring two of the vertical through vias (VTVs) 358 in the semiconductor substrate 2 may range from 20 to 150 micrometers or from 40 to 100 micrometers or may be smaller than 50, 40 or 30 micrometers. Multiple trenches 14b for reserved scribe lines may be formed in the passivation layer 14 to form multiple insulating-material islands 14c between neighboring two of the trenches 14b. The vertical through vias (VTVs) 358 arranged in only one line are arranged between neighboring two of the reserved scribe lines 141. Each of the insulating-material islands 14c may be aligned with only one of the vertical through vias (VTVs) 358, and one of the openings 14a in said each of the insulating-material islands 14c may be arranged over said only one of the vertical through vias (VTVs) 358. None of the vertical through vias (VTVs) 358 may be arranged under each of the trenches 14b. Accordingly, the pitch Wp and space W_sptsv between each neighboring two of the vertical through vias (VTVs) 358 may be greater than a width W_sb of the reserved scribe lines 141 or greater than the width W_sb of the reserved scribe lines 141 plus two times of a predetermined space W_sbt between one of the reserved scribe lines 141 and one of said each neighboring two of the vertical through vias (VTVs) 358 adjacent to said one of the first reserved scribe lines 141. For each of the first and second types of vertical-through-via (VTV) connectors 467, the distance W_sbt between its edge and one of its vertical through vias (VTVs) 358 may be smaller than the space W_sptsv between neighboring two of its vertical through vias (VTVs) 358 and optionally its edge may be aligned with an edge of said one of its vertical through vias (VTVs) 358.

[0204] In the first alternative, for the second case, referring to FIGS. 1C and 1D, the vertical through vias (VTVs) 358 may be populated regularly in multiple islands or regions 188 of arrays of vertical through vias (VTVs) with the reserved scribe lines 141 each between neighboring two of the islands or regions 188 of arrays of vertical through vias (VTVs). A pitch Wp between each neighboring two of the vertical through vias (VTVs) 358 aligned with one of the islands or regions 188 of arrays of vertical through vias (VTVs) may range from 5 to 50 micrometers or from 5 to 20 micrometers or may be smaller than 50, 40 or 30 micrometers; and a space W_sptsv between neighboring two of the vertical through vias (VTVs) 358 aligned with one of the islands or regions 188 of arrays of vertical through vias (VTVs) may range from 5 to 50 micrometers or from 5 to 20 micrometers or may be smaller than 50, 40 or 30 micrometers. For each of the islands or regions 188 of arrays of vertical through vias (VTVs), its vertical through vias (VTVs) 358 may be arranged in multiple columns and in multiple rows; its insulating-material island 14c may be aligned with its vertical through vias (VTVs) 358, and multiple of the openings 14a in its insulating-material island 14c may be arranged over its vertical through vias (VTVs) 358 respectively. The pitch Wp and space W_sptsv between each neighboring two of the vertical through vias (VTVs) 358 aligned with one of the islands or regions 188 of arrays of vertical through vias (VTVs) may be smaller than the width W_sb of the reserved scribe lines 141 and/or smaller than a first space W_spild between neighboring two of the vertical through vias (VTVs) 358 aligned with neighboring two of the islands or regions 188 of arrays of vertical through vias (VTVs) respectively and across one of the reserved scribe lines 141 between said neighboring two of the islands or regions 188 of arrays of vertical through vias (VTVs). The space W_spild or a width of the trench 14b between neighboring two of the insulating-material islands 14c may be greater than 50, 40 or 30 micrometers. The space W_spild may be greater than the width W_sb of the reserved scribe lines 141 or greater than the width W_sb of the reserved scribe lines 141 plus two times of a predetermined space W_sbt between one of the reserved scribe lines 141 and one of the vertical through vias (VTVs) 358 adjacent to said one of the reserved scribe lines 141. For each of the first and second types of vertical-through-via (VTV) connectors 467, each of its first and second spaces W_spild between neighboring two of its vertical through vias (VTVs) 358 and across one of its first and second reserved scribe lines 141 and 142 between said neighboring two of its vertical through vias (VTVs) 358 may be greater than 50 or 40 micrometers, and the distance W_sbt between its edge and one of its vertical through vias (VTVs) 358 may be smaller than the space W_sptsv between neighboring two of its vertical through vias (VTVs) 358 and optionally its edge may be aligned with an edge of said one of its vertical through vias (VTVs) 358.

[0205] In the first alternative, for the third case, referring to FIGS. 1E and 1F, a pitch Wp between each neighboring two of the vertical through vias (VTVs) 358 in the semiconductor substrate 2 may range from 5 to 50 micrometers or from 5 to 20 micrometers or may be smaller than 50, 40 or 30 micrometers; and a space W_sptsv between neighboring two of the vertical through vias (VTVs) 358 may range from 5 to 50 micrometers or from 5 to 20 micrometers or may be smaller than 50, 40 or 30 micrometers. Each reserved scribe line 141 may extend in line with multiple of the vertical through vias (VTVs) 358 arranged in a line. Accordingly, the pitch Wp and space W_sptsv between each neighboring two of the vertical through vias (VTVs) 358 may be smaller than a width W_sb of the reserved scribe lines 141 or smaller than the width W_sb of the reserved scribe lines 141 plus two times of a predetermined space W_sbt between one of the reserved scribe lines 141 and one of the vertical through vias (VTVs) 358 adjacent to said one of the reserved scribe lines 141. For each of the first and second types of vertical-through-via (VTV) connectors 467, the distance W_sbt between its edge and one of its vertical through vias (VTVs) 358 may be smaller than the space W_sptsv between neighboring two of its vertical through vias (VTVs) 358 and optionally its edge may be aligned with an edge of said one of its vertical through vias (VTVs) 358, wherein the space W_sptsv between neighboring two of its vertical through vias (VTVs) 358 may be smaller than 50, 40 or 30 micrometers.

[0206] In the first alternative, for the first case, referring to FIG. 1A, a pitch WB_p between each neighboring two of the first, second, third or fourth type of micro-bumps or micro-pads 34 may range from 20 to 150 micrometers or from 40 to 100 micrometers; and a space WB_sptsv between each neighboring two of the first, second, third or fourth type of micro-bumps or micro-pads 34 may range from 20 to 150 micrometers or from 40 to 100 micrometers. The first, second, third or fourth type of micro-bumps or micro-pads 34 arranged in only one line are arranged between neighboring two of the reserved scribe lines 141. Each of the insulating-material islands 14c may be aligned with only one of the first, second, third or fourth type of micro-bumps or micro-pads 34, and one of the openings 14a in said each of the insulating-material islands 14c may be arranged under said only one of the first, second, third or fourth type of micro-bumps or micro-pads 34. Accordingly, the pitch WB_p and space WB_sptsv between each neighboring two of the first, second, third or fourth type of micro-bumps or micro-pads 34 may be greater than the width W_sb of the second reserved scribe lines 142 or greater than the width W_sb of the reserved scribe lines 141 plus two times of a predetermined space WB_sbt between one of the reserved scribe lines 141 and one of said each neighboring two of the first, second, third or fourth type of micro-bumps or micro-pads 34 adjacent to said one of the reserved scribe lines 141. For the first type of vertical-through-via (VTV) connector 467, the distance WB_sbt between its edge and one of its first, second, third or fourth type of micro-bumps or micro-pads 34 may be smaller than the space WB_sptsv between neighboring two of its first, second, third or fourth type of micro-bumps or micro-pads 34 and optionally its edge may be aligned with an edge of said one of its first, second, third or fourth type of micro-bumps or micro-pads 34; alternatively, the distance WB_sbt between its edge and one of its first, second, third or fourth type of micro-bumps or micro-pads 34 may be smaller than 50, 40 or 30 micrometers.

[0207] In the first alternative, for the second case, referring to FIG. 1C, the first, second, third or fourth type of micro-bumps or micro-pads 34 may be populated regularly in multiple islands or regions 88 of arrays of micro-bumps or micro-pads with the reserved scribe lines 141 each between neighboring two of the islands or regions 88 of arrays of micro-bumps or micro-pads. A pitch WB_p between each neighboring two of the first, second, third or fourth type of micro-bumps or micro-pads 34 aligned with one of the islands or regions 88 of arrays of micro-bumps or micro-pads may range from 5 to 50 micrometers or from 5 to 20 micrometers or may be smaller than 50, 40 or 30 micrometers; and a space WB_sptsv between neighboring two of the first, second, third or fourth type of micro-bumps or micro-pads 34 aligned with one of the islands or regions 88 of arrays of micro-bumps or micro-pads may range from 5 to 50 micrometers or from 5 to 20 micrometers or may be smaller than 50, 40 or 30 micrometers. For each of the islands or regions 88 of arrays of micro-bumps or micro-pads, its first, second, third or fourth type of micro-bumps or micro-pads 34 may be arranged in multiple columns and in multiple rows; its insulating-material island 14c may be aligned with its first, second, third or fourth type of micro-bumps or micro-pads 34, and multiple of the openings 14a in its insulating-material island 14c may be arranged under its first, second, third or fourth type of micro-bumps or micro-pads 34 respectively. The pitch WB_p and space WB_sptsv between each neighboring two of the first, second, third or fourth type of micro-bumps or micro-pads 34 aligned with one of the islands or regions 88 of arrays of micro-bumps or micro-pads may be smaller than the width W_sb of the reserved scribe lines 141 and/or smaller than a space WB_spild between neighboring two of the first, second, third or fourth type of micro-bumps or micro-pads 34 aligned with neighboring two of the islands or regions 88 of arrays of micro-bumps or micro-pads respectively and across one of the reserved scribe lines 141 between said neighboring two of the islands or regions 88 of arrays of micro-bumps or micro-pads. The space WB_spild or a width of the trench 14b between neighboring two of the insulating-material islands 14c may be greater than 50, 40 or 30 micrometers. The space WB_spild may be greater than the width W_sb of the reserved scribe lines 141 or greater than the width W_sb of the reserved scribe lines 141 plus two times of a predetermined space WB_sbt between one of the reserved scribe lines 141 and one of the first, second, third or fourth type of micro-bumps or micro-pads 34 adjacent to said one of the reserved scribe lines 141. The first type of vertical-through-via (VTV) connector 467 may include the insulating-material islands 14c having the trench 14b therebetween having a width greater than 50 or 40 micrometers; each of its spaces WB_spild each between neighboring two of its first, second, third or fourth type of micro-bumps or micro-pads 34 and across one of its reserved scribe lines 141 between said neighboring two of its first, second, third or fourth type of micro-bumps or micro-pads 34 may be greater than 50, 40 or 30 micrometers; the distance WB_sbt between its edge and one of its first, second, third or fourth type of micro-bumps or micro-pads 34 may be smaller than the space WB_sptsv between neighboring two of its first, second, third or fourth type of micro-bumps or micro-pads 34 and optionally its edge may be aligned with an edge of said one of its first, second, third or fourth type of micro-bumps or micro-pads 34; alternatively, the distance WB_sbt between its edge and one of its first, second, third or fourth type of micro-bumps or micro-pads 34 may be smaller than 50, 40 or 30 micrometers.

[0208] In the first alternative, for the third case, referring to FIG. 1E, a pitch WB_p between each neighboring two of the first, second, third or fourth type of micro-bumps or micro-pads 34 may range from 5 to 50 micrometers or from 5 to 20 micrometers or may be smaller than 50, 40 or 30 micrometers; and a space WB_sptsv between neighboring two of the first, second, third or fourth type of micro-bumps or micro-pads 34 may range from 5 to 50 micrometers or from 5 to 20 micrometers or may be smaller than 50, 40 or 30 micrometers. Each of the reserved scribe lines 141 may extend in line with multiple of the first, second, third or fourth type of micro-bumps or micro-pads 34 arranged in a line. Accordingly, the pitch WB_p and space WB_sptsv between each neighboring two of the first, second, third or fourth type of micro-bumps or micro-pads 34 may be smaller than the width W_sb of the reserved scribe lines 141 or smaller than the width W_sb of the reserved scribe lines 141 plus two times of a predetermined space W_sbt between one of the reserved scribe lines 141 and one of the first, second, third or fourth type of micro-bumps or micro-pads 34 adjacent to said one of the reserved scribe lines 141. For the first type of vertical-through-via (VTV) connector 467, the distance WB_sbt between its edge and one of its first, second, third or fourth type of micro-bumps or micro-pads 34 may be smaller than the space WB_sptsv between neighboring two of its first, second, third or fourth type of micro-bumps or micro-pads 34 and optionally its edge may be aligned with an edge of said one of its first, second, third or fourth type of micro-bumps or micro-pads 34; alternatively, the distance WB_sbt between its edge and one of its first, second, third or fourth type of micro-bumps or micro-pads 34 may be smaller than 50, 40 or 30 micrometers; the space WB_sptsv between neighboring two of its first, second, third or fourth type of micro-bumps or micro-pads 34 may be smaller than 50, 40 or 30 micrometers.

[0209] Referring to FIGS. 1A-IF for the first alternative, the aspect ratio of the length to the width for each of its first and second types of vertical-through-via (VTV) connectors 467 may be between 2 and 10, between 4 and 10 or between 2 and 40. Each of the first and second types of vertical-through-via (VTV) connectors 467 may be provided with passive elements, such as capacitors, but without any active device, i.e., transistor, therein. Each of the first and second types of vertical-through-via (VTV) connectors 467 may be manufactured by packaging manufacturing companies or facilities without front-end of line manufacturing capability.

[0210] Accordingly, in the first alternative, for each of the first, second and third cases as seen in FIGS. 1A-IF, each of the first and second types of vertical-through-via (VTV) connectors 467 may be arranged with a size for containing the vertical through vias (VTVs) 358 arranged in an array with M1 row(s) by N1 column(s); furthermore, for each of the first, second and third cases as seen in FIGS. 1A, 1C and 1E, the first type of vertical-through-via (VTV) connector 467 may be arranged with a size for containing the first, second, third or fourth type of micro-bumps or micro-pads 34 arranged in an array with M2 row(s) by N2 column(s), wherein M1, M2, N1 and N2 are integers, M1 is greater than N1 and M2 is greater than N2. For an example, each of the numbers M1 and M2 may be greater than or equal to 50 and smaller than or equal to 500, and each of the numbers N1 and N2 may be greater than or equal to 1 and smaller than or equal to 15. For another example, each of the numbers N1 and N2 may be greater than or equal to 30 and smaller than or equal to 200, and each of the numbers M1 and M2 may be greater than or equal to 1 and smaller than or equal to 10.

[0211] FIGS. 2A and 2B are schematically cross-sectional views showing first and second types of vertical-through-via (VTV) connectors for a second alternative for the first case in accordance with an embodiment of the present application. FIGS. 2C and 2D are schematically cross-sectional views showing a process for forming first and second types of vertical-through-via (VTV) connectors for a second alternative for the second case in accordance with an embodiment of the present application. FIGS. 2E and 2F are schematically cross-sectional views showing a process for forming first and second types of vertical-through-via (VTV) connectors for a second alternative for the third case in accordance with an embodiment of the present application. In a second alternative, referring to each of FIGS. 2A, 2C and 2E, a first type of vertical-through-via (VTV) connectors 467 may include (1) multiple semiconductor substrates 2, i.e., silicon substrates, (2) multiple insulating dielectric layers 12 each on a first surface of one of the semiconductor substrates 2, wherein each of the insulating dielectric layers 12 may include a silicon-oxide layer having a thickness between 0.1 and 2 μm, wherein one of the insulating dielectric layers 12 on the first surface of the bottommost one of the semiconductor substrates 2 may be attached to one of the insulating dielectric layers 12 on the first surface of the second bottommost one of the semiconductor substrates 2, (3) one or more insulating bonding layers 52 each on a second surface of one of the second bottommost through topmost ones of the semiconductor substrates 2, wherein the second surface of said one of the second bottommost through topmost ones of the semiconductor substrates 2 is opposite to the first surface of said one of the second bottommost through topmost ones of the semiconductor substrates 2, wherein each of the insulating bonding layers 52 may be made a layer of silicon oxide having a thickness between 1 and 1,000 nanometers, and wherein one of the insulating bonding layers 52 on the second surface of a lower one of the second bottommost through topmost ones of the semiconductor substrates 2 may have silicon oxide bonded to silicon oxide of one of the insulating dielectric layers 12 on the first surface of an upper one of the second bottommost through topmost ones of the semiconductor substrates 2, and (4) multiple through silicon vias (TSVs) 157 in each of the semiconductor substrates 2 and extending vertically through one of the insulating dielectric layers 12 on the first surface of said each of the semiconductor substrates 2 and/or one of the insulating bonding layers 52 on the second surface of said each of the semiconductor substrates 2.

[0212] In the second alternative, referring to each of FIGS. 2A, 2C and 2E, each of the through silicon vias (TSVs) 157 in the bottommost one of the semiconductor substrates 2 and extending vertically through one of the insulating dielectric layers 12 on the first surface of the bottommost one of the semiconductor substrates 2 may include (1) an insulating lining layer 153, such as a layer of thermally grown silicon oxide (SiO₂), a layer of CVD silicon nitride (Si₃N₄) or a combination thereof, on a sidewall and bottom of one of blind holes 2a in the bottommost one of the semiconductor substrates 2, (2) a copper layer 156 electroplated in said one of the blind holes 2a, wherein the copper layer 156 may have a top surface coplanar with a top surface of the insulating dielectric layer 12 on the first surface of the bottommost one of the semiconductor substrates 2, (3) an adhesion layer 154, such as a layer of titanium (Ti) or titanium nitride (TiN) having a thickness between 1 nm to 50 nm, on the insulating lining layer 153, between the insulating lining layer 153 and copper layer 156 and at a sidewall and bottom of the copper layer 156, and (4) a seed layer 155, such as a layer of copper having a thickness between 3 nm and 200 nm, between the adhesion layer 154 and copper layer 156 and at a sidewall and bottom of the copper layer 156.

[0213] In the second alternative, referring to each of FIGS. 2A, 2C and 2E, each of the through silicon vias (TSVs) 157 in each of the second bottommost through topmost ones of the semiconductor substrates 2 and extending vertically through one of the insulating dielectric layers 12 on the first surface of said each of the second bottommost through topmost ones of the semiconductor substrates 2 and one of the insulating bonding layers 52 on the second surface of said each of the second bottommost through topmost ones of the semiconductor substrates 2 may include (1) an insulating lining layer 153, such as a layer of thermally grown silicon oxide (SiO₂), a layer of CVD silicon nitride (Si₃N₄) or a combination thereof, on a sidewall of one of through holes in said each of the second bottommost through topmost ones of the semiconductor substrates 2, (2) a copper layer 156 electroplated in said one of the through holes, wherein the copper layer 156 may have a bottom surface coplanar with a bottom surface of the insulating dielectric layer 12 on the first surface of said each of the second bottommost through topmost ones of the semiconductor substrates 2 and a top surface coplanar with a top surface of the insulating bonding layer 52 on the second surface of said each of the second bottommost through topmost ones of the semiconductor substrates 2, (3) an adhesion layer 154, such as a layer of titanium (Ti) or titanium nitride (TiN) having a thickness between 1 nm to 50 nm, on the insulating lining layer 153, between the insulating lining layer 153 and copper layer 156 and at a sidewall of the copper layer 156, and (4) a seed layer 155, such as a layer of copper having a thickness between 3 nm and 200 nm, between the adhesion layer 154 and copper layer 156 and at a sidewall of the copper layer 156.

[0214] In the second alternative, referring to each of FIGS. 2A, 2C and 2E, multiple of the through silicon vias (TSVs) 157 may be stacked with each other or one another to form a vertical through via (VTV) 358 for a dedicated vertical path, wherein the copper layer 156 of an upper one of the through silicon vias (TSVs) 157 may have the bottom surface bonded to the top surface of the copper layer 156 of a lower one of the through silicon vias (TSVs) 157. Each of the vertical through vias (VTVs) 358 may include multiple of the through silicon vias (TSVs) 157 stacked up to a total height between 100 and 2,000 micrometers, between 100 and 1,000 micrometers or between 100 and 500 micrometers.

[0215] In the second alternative, referring to each of FIGS. 2A, 2C and 2E, the first type of vertical-through-via (VTV) connectors 467 may further include (1) a passivation layer 14, which may have the same specification as that as illustrated in each of FIGS. 1A, 1C and 1E, on the top surface of the insulating bonding layer 52 on the second surface of the topmost one of the semiconductor substrates 2, wherein each opening 14a in the passivation layer 14 may be vertically over the top surface of the copper layer 156 of one of the vertical through vias (VTVs) 358, wherein each of the openings 14a may have the same specification as that as illustrated in each of FIGS. 1A, 1C and 1E, and (2) multiple micro-bump or micro-pad 34, which may be of one of the first through fourth types having the same specifications as the first through fourth types of micro-bumps or micro-pads 34 as illustrated in each of FIGS. 1A, 1C and 1E respectively, each on the top surface of the copper layer 156 of one of the vertical through vias (VTVs) 358.

[0216] In the second alternative, a second type of vertical-through-via (VTV) connector 467 as seen in FIG. 2B, 2D or 2F is similar to the first type of vertical-through-via (VTV) connector 467 as illustrated in FIG. 2A, 2C or 2E respectively, but has none of the passivation layer 14 and micro-bumps or micro-pads 34 as illustrated in FIG. 2A, 2C or 2E.

[0217] In the second alternative, referring to FIGS. 2A and 2B for the first case, the arrangements for the vertical through vias (VTVs) 358 for each of the first and second types of vertical-through-via (VTV) connectors 467 may be the same as those as illustrated in FIGS. 1A and 1B for the first case for the first alternative; the arrangements for the trenches 14b, insulating-material islands 14c and first, second, third or fourth type of micro-bumps or micro-pads 34 for the first type of vertical-through-via (VTV) connector 467 may be the same as those as illustrated in FIG. 1A for the first case for the first alternative.

[0218] Alternatively, in the second alternative, referring to FIGS. 2C and 2D for the second case, the arrangements for the vertical through vias (VTVs) 358 and islands or regions 188 of arrays of vertical through vias (VTVs) for each of the first and second types of vertical-through-via (VTV) connectors 467 may be the same as those as illustrated in FIGS. 1C and 1D for the second case for the first alternative; the arrangements for the islands or regions of arrays 88 of micro-bumps or micro-pads, trenches 14b, insulating-material islands 14c and first, second, third or fourth type of micro-bumps or micro-pads 34 for the first type of vertical-through-via (VTV) connector 467 may be the same as those as illustrated in FIG. 1C for the second case for the first alternative.

[0219] Alternatively, in the second alternative, referring to FIGS. 2E and 2F for the third case, the arrangements for the vertical through vias (VTVs) 358 for each of the first and second types of vertical-through-via (VTV) connectors 467 may be the same as those as illustrated in FIGS. 1E and 1F for the third case for the first alternative; the arrangements for the first, second, third or fourth type of micro-bumps or micro-pads 34 for the first type of vertical-through-via (VTV) connector 467 may be the same as those as illustrated in FIG. 1E for the third case for the first alternative.

[0220] Referring to FIGS. 2A-2F for the second alternative, the aspect ratio of the length to the width for each of the first and second types of vertical-through-via (VTV) connectors 467 may be between 2 and 10, between 4 and 10 or between 2 and 40. Each of the first and second types of vertical-through-via (VTV) connector 467 may be provided with passive elements, such as capacitors, but without any active device, i.e., transistor, therein.

[0221] FIG. 3A is a schematically cross-sectional view showing a decoupling capacitor in a first type of vertical-through-via (VTV) connector in accordance with an embodiment of the present application. FIG. 3B is a schematically top view showing a decoupling capacitor between four vertical through vias (VTVs) in accordance with an embodiment of the present application, wherein FIG. 3A is a schematically cross-sectional view along a cross-sectional line A-A on FIG. 3B. For the first alternative for the first through third cases as illustrated in each of FIGS. 1A, 1C and 1E, the first type of vertical-through-via (VTV) connector 467 may further include a decoupling capacitor 401 therein as seen in FIGS. 3A and 3B, provided with (1) a first electrode 402 in a deep trench 2c having a depth between 30 μm and 2,000 μm in the semiconductor substrate 2 and vertically extending through the insulating dielectric layer 12, (2) a second electrode 404 in a shallow trench 2d having a depth between 5 μm and 30 μm or between 5 and 20 micrometers and less than the depth of the deep trenches 2c in the semiconductor substrate 2 and vertically extending through the insulating dielectric layer 12, and (3) a dielectric layer 403 between the first and second electrodes 402 and 404 and at a sidewall and bottom of the shallow trench 2d. The first electrode 402 of the decoupling capacitor 401 may include (1) an insulating lining layer 153, such as a layer of thermally grown silicon oxide (SiO₂), a layer of CVD silicon nitride (Si₃N₄) or a combination thereof, on a sidewall and bottom of the deep trench 2c, (2) a copper layer 156 electroplated in the deep trench 2c, wherein the copper layer 156 of the first electrode 402 may have a top surface coplanar with a top surface of the insulating dielectric layer 12, (3) an adhesion layer 154, such as a layer of titanium (Ti) or titanium nitride (TiN) having a thickness between 1 nm to 50 nm, on the insulating lining layer 153 of the first electrode 402, between the insulating lining layer 153 and copper layer 156 of the first electrode 402 and at a sidewall and bottom of the copper layer 156 of the first electrode 402, and (4) a seed layer 155, such as a layer of copper having a thickness between 3 nm and 200 nm, between the adhesion layer 154 and copper layer 156 of the first electrode 402 and at a sidewall and bottom of the copper layer 156 of the first electrode 402. The dielectric layer 403 of the decoupling capacitor 401 may be a layer of tantalum oxide (Ta₂O₅), hafnium oxide (HfO₂), zirconium oxide (ZrO₂), titanium oxide (TiO₂) or silicon nitride (Si₃N₄) having a thickness between 100 and 1,000 angstroms on a sidewall and bottom of the shallow trench 2d. The second electrode 404 of the decoupling capacitor 401 may include (1) a copper layer 156 electroplated in the shallow trench 2d, wherein the copper layer 156 of the second electrode 404 may have a top surface coplanar with the top surface of the insulating dielectric layer 12, (2) an adhesion layer 154, such as a layer of titanium (Ti) or titanium nitride (TiN) having a thickness between 1 nm to 50 nm, on the dielectric layer 403 of the decoupling capacitor 401, between the dielectric layer 403 of the decoupling capacitor 401 and the copper layer 156 of the second electrode 404 and at a sidewall and bottom of the copper layer 156 of the second electrode 404, and (3) a seed layer 155, such as a layer of copper having a thickness between 3 nm and 200 nm, between the adhesion layer 154 and copper layer 156 of the second electrode 404 and at a sidewall and bottom of the copper layer 156 of the second electrode 404.

[0222] Accordingly, referring to FIGS. 3A and 3B, the decoupling capacitor 401 may be provided with the dielectric layer 403 between the first and second electrodes 402 and 404 thereof, wherein the first electrode 402 of the decoupling capacitor 401 may have a depth between 30 and 2,000 micrometers and the second electrode 404 of the decoupling capacitor 401 may have a depth between 5 and 30 micrometers or between 5 and 20 micrometers. It is noted that one of the first, second, third or fourth type of micro-bumps or micro-pads 34 may be formed on the copper layer 156 of one of the through silicon vias (TSVs) 157 and the second electrode 404 of the decoupling capacitor 401 beside the copper layer 156 of said one of the through silicon vias (TSVs) 157 to couple said one of the through silicon vias (TSVs) 157 to the second electrode 404 of the decoupling capacitor 401. Each of the through silicon vias (TSVs) 157 may be used as a vertical through via (VTV) 358 for a dedicated vertical path. For an element indicated by the same reference number shown in FIGS. 1A, 1C, 1E, 3A and 3B, the specification of the element as seen in FIGS. 3A and 3B may be referred to that of the element as illustrated in FIGS. 1A, 1C and 1E.

[0223] Alternatively, FIG. 3C is a schematically cross-sectional view showing a decoupling capacitor in a first type of vertical-through-via (VTV) connector in accordance with another embodiment of the present application. FIG. 3D is a schematically top view showing a decoupling capacitor among four through silicon vias (TSVs) in accordance with another embodiment of the present application, wherein FIG. 3C is a schematically cross-sectional view along a cross-sectional line B-B on FIG. 3D. For the first alternative for the first through third cases as illustrated in each of FIGS. 1A, 1C and 1E, the first type of vertical-through-via (VTV) connector 467 may further include a decoupling capacitor 401 therein as seen in FIGS. 3C and 3D, provided with (1) a first electrode 402 in a first shallow trench 2f, which has a depth between 5 μm and 30 μm or between 5 μm and 20 μm and less than the depth of the blind holes 2a, in the semiconductor substrate 2 and vertically extending through the insulating dielectric layer 12, (2) a second electrode 404 in a second shallow trench 2g, which has a depth between 5 μm and 30 μm or between 5 μm and 20 μm and less than the depth of the blind holes 2a, in the semiconductor substrate 2 and vertically extending through the insulating dielectric layer 12, and (3) a dielectric layer 403 between the first and second electrodes 402 and 404 and at a sidewall and bottom of the second shallow trench 2g. The first electrode 402 of the decoupling capacitor 401 may include (1) a copper layer 156 electroplated in the first shallow trench 2f, wherein the copper layer 156 of the first electrode 402 may have a top surface coplanar with a top surface of the insulating dielectric layer 12, (2) an adhesion layer 154, such as a layer of titanium (Ti) or titanium nitride (TiN) having a thickness between 1 nm to 50 nm, on a sidewall and bottom of the first shallow trench 2f and at a sidewall and bottom of the copper layer 156 of the first electrode 402, and (3) a seed layer 155, such as a layer of copper having a thickness between 3 nm and 200 nm, between the adhesion layer 154 and copper layer 156 of the first electrode 402 and at a sidewall and bottom of the copper layer 156 of the first electrode 402. The dielectric layer 403 of the decoupling capacitor 401 may be a layer of tantalum oxide (Ta₂O₅), hafnium oxide (HfO₂), zirconium oxide (ZrO₂), titanium oxide (TiO₂) or silicon nitride (Si₃N₄) having a thickness between 100 and 1,000 angstroms on a sidewall and bottom of the second shallow trench 2g. The second electrode 404 of the decoupling capacitor 401 may include (1) a copper layer 156 electroplated in the second shallow trench 2g, wherein the copper layer 156 of the second electrode 404 may have a top surface coplanar with the top surface of the insulating dielectric layer 12, (2) an adhesion layer 154, such as a layer of titanium (Ti) or titanium nitride (TiN) having a thickness between 1 nm to 50 nm, on the dielectric layer 403 of the decoupling capacitor 401, between the dielectric layer 403 of the decoupling capacitor 401 and the copper layer 156 of the second electrode 404 and at a sidewall and bottom of the copper layer 156 of the second electrode 404, and (4) a seed layer 155, such as a layer of copper having a thickness between 3 nm and 200 nm, between the adhesion layer 154 and copper layer 156 of the second electrode 404 and at a sidewall and bottom of the copper layer 156 of the second electrode 404.

[0224] Accordingly, referring to FIGS. 3C and 3D, the decoupling capacitor 401 may be provided with the dielectric layer 403 between the first and second electrodes 402 and 404 thereof, wherein The first and second electrodes 402 and 404 of the decoupling capacitor 401 may have substantially the same depth between 5 and 30 μm or between 5 and 20 μm and less than the depth of the through silicon vias (TSVs) 157, wherein the depth of the through silicon vias (TSVs) 157 may range from 30 to 2,000 μm. It is noted that a first one of the first, second, third or fourth type of micro-bumps or micro-pads 34 may be formed on the copper layer 156 of a first one of the through silicon vias (TSVs) 157 and the first electrode 402 of the decoupling capacitor 401 beside the copper layer 156 of the first one of the through silicon vias (TSVs) 157 to couple the first one of the through silicon vias (TSVs) 157 to the first electrode 402 of the decoupling capacitor 401; a second one of the first, second, third or fourth type of micro-bumps or micro-pads 34 may be formed on the copper layer 156 of a second one of the through silicon vias (TSVs) 157 and the second electrode 404 of the decoupling capacitor 401 beside the copper layer 156 of the second one of the through silicon vias (TSVs) 157 to couple the second one of the through silicon vias (TSVs) 157 to the second electrode 404 of the decoupling capacitor 401. The first electrode 402 of the decoupling capacitor 401 is configured to electrically couple to the semiconductor substrate 2 and configured to electrically couple to a voltage Vss of ground reference via the first one of the first, second, third or fourth type of micro-bumps or micro-pads 34. Each of the through silicon vias (TSVs) 157 may be used as a vertical through via (VTV) 358 for a dedicated vertical path. For an element indicated by the same reference number shown in FIGS. 1A, 1C, 1E, 3C and 3D, the specification of the element as seen in FIGS. 3C and 3D may be referred to that of the element as illustrated in FIGS. 1A, 1C and 1E.

[0225] For example, the decoupling capacitor 401 as illustrated in each of FIGS. 3A and 3C may have capacitance between 10 and 5,000 nF. The decoupling capacitor 401 as illustrated in each of FIGS. 3A and 3C may be formed (1) for the first case among any four of the vertical through vias (VTVs) 358 and in the semiconductor substrate 2 of the first or second type of vertical-through-via (VTV) connector 467 as seen in FIG. 1A or 1B, (2) for the second case among any four of the vertical through vias (VTVs) 358 and in the semiconductor substrate 2 of the first or second type of vertical-through-via (VTV) connector 467 as seen in FIG. 1C or 1D, or (3) for the third case among any four of the vertical through vias (VTVs) 358 and in the semiconductor substrate 2 of the first or second type of vertical-through-via (VTV) connector 467 as seen in FIG. 1E or IF. Alternatively, the decoupling capacitor 401 as illustrated in each of FIGS. 3A and 3C may be formed (1) for the first case among any four of the vertical through vias (VTVs) 358, i.e., among any four of the through silicon vias (TSVs) 157, and in one of the semiconductor substrates 2 of the first or second type of vertical-through-via (VTV) connector 467 as seen in FIG. 2A or 2B, (2) for the second case among any four of the vertical through vias (VTVs) 358, i.e., among any four of the through silicon vias (TSVs) 157, and in one of the semiconductor substrates 2 of the first or second type of vertical-through-via (VTV) connector 467 as seen in FIG. 2C or 2D, or (3) for the third case among any four of the vertical through vias (VTVs) 358, i.e., among any four of the through silicon vias (TSVs) 157, and in one of the semiconductor substrates 2 of the first or second type of vertical-through-via (VTV) connector 467 as seen in FIG. 2E or 2F.

[0226] FIG. 4A is a schematically cross-sectional view showing a first type of vertical-through-via (VTV) connector for a third alternative for the first case in accordance with an embodiment of the present application. FIG. 4B is a schematically cross-sectional view showing a first type of vertical-through-via (VTV) connector for a third alternative for the second case in accordance with an embodiment of the present application. FIG. 4C is a schematically cross-sectional view showing a first type of vertical-through-via (VTV) connector for a third alternative for the third case in accordance with an embodiment of the present application. In a third alternative, referring to each of FIGS. 4A-4C, a first type of vertical-through-via (VTV) connector 467 may include (1) a glass substrate 202 made of silicon oxide, (2) multiple through glass vias (TGVs) 259 each in the glass substrate 202 and vertically extending through the glass substrate 202, and (3) a glass wetting layer 708, such as a layer of silicon oxide having a thickness between 0.01 and 1 micrometers, at a sidewall of each of the through glass vias (TGVs) 259, around said each of the through glass vias (TGVs) 259 and between said each of the through glass vias (TGVs) 259 and the glass substrate 202. Each of the through glass vias (TGVs) 259 may include (1) a copper post 706 having a circular shape with a diameter or largest transverse dimension between 3 and 30 micrometers and a height between 30 and 100 micrometers in the glass substrate 202 and vertically extending through the glass substrate 202, wherein the glass wetting layer 708 may surround the copper post 706, and wherein the copper post 706 may have a top surface coplanar with a top surface of the glass substrate 202 and a bottom surface coplanar with a bottom surface of the glass substrate 202, and (2) a metal lining layer 707, such as a layer of a titanium-tungsten alloy, tungsten, titanium nitride or a high melting-point metal having a melting temperature greater than 1,100 or 1,500 degrees Celsius, having a thickness between 0.1 and 2 micrometers at a sidewall of the copper post 706, around the copper post 706 and between the copper post 706 and the glass wetting layer 708. Each of the through glass vias (TGVs) 259 may have a thickness between 30 and 100 micrometers to be used as a vertical through via (VTV) 358 for a dedicated vertical path.

[0227] In the third alternative, referring to each of FIGS. 4A-4C, the first type of vertical-through-via (VTV) connector 467 may further include multiple fifth type of micro-bumps or micro-pads 34, i.e., metal bumps or pads, each on the top surface of the copper post 706 of one of the through glass vias (TGVs) 259. Each of the fifth type of micro-bumps or micro-pads 34 may include (1) a coper layer 717 having a thickness between 3 and 10 micrometers on the top surface of the copper post 706 of one of the through glass vias (TGVs) 259, (2) a nickel layer 718 having a thickness between 1 and 5 micrometers on a top and sidewall of the copper layer 717, and (3) a solder layer 719, such as a tin-silver alloy or a tin-lead alloy, having a thickness between 1 and 20 micrometers on a top surface and side surface of the nickel layer 718.

[0228] In the third alternative, referring to FIG. 4A for the first case, the arrangements for the vertical through vias (VTVs) 358 for the first type of vertical-through-via (VTV) connector 467 may be the same as those as illustrated in FIG. 1A for the first case for the first alternative; the arrangements for the fifth type of micro-bumps or micro-pads 34 for the first type of vertical-through-via (VTV) connector 467 may be the same as those for the first, second, third or fourth type of micro-bumps or micro-pads 34 as illustrated in FIG. 1A for the first case for the first alternative.

[0229] In the third alternative, referring to FIG. 4B for the second case, the arrangements for the vertical through vias (VTVs) 358 for the first type of vertical-through-via (VTV) connector 467 may be the same as those as illustrated in FIG. 1C for the second case for the first alternative; the arrangements for the fifth type of micro-bumps or micro-pads 34 for the first type of vertical-through-via (VTV) connector 467 may be the same as those for the first, second, third or fourth type of micro-bumps or micro-pads 34 as illustrated in FIG. 1C for the second case for the first alternative.

[0230] In the third alternative, referring to FIG. 4C for the third case, the arrangements for the vertical through vias (VTVs) 358 for the first type of vertical-through-via (VTV) connector 467 may be the same as those as illustrated in FIG. 1A for the third case for the first alternative; the arrangements for the fifth type of micro-bumps or micro-pads 34 for the first type of vertical-through-via (VTV) connector 467 may be the same as those for the first, second, third or fourth type of micro-bumps or micro-pads 34 as illustrated in FIG. 1A for the third case for the first alternative.

[0231] Referring to each of FIGS. 4A-4C for the third alternative, the aspect ratio of the length to the width for the first type of vertical-through-via (VTV) connector 467 may be between 2 and 10, between 4 and 10 or between 2 and 40. The first type of vertical-through-via (VTV) connector 467 may be provided with passive elements, such as capacitors, but without any active device, i.e., transistor, therein.

[0232] FIG. 5A is a schematically cross-sectional view showing a first type of vertical-through-via (VTV) connector for a fourth alternative for the first case in accordance with an embodiment of the present application. FIG. 5B is a schematically cross-sectional view showing a first type of vertical-through-via (VTV) connector for a fourth alternative for the second case in accordance with an embodiment of the present application. FIG. 5C is a schematically cross-sectional view showing a first type of vertical-through-via (VTV) connector for a fourth alternative for the third case in accordance with an embodiment of the present application. In a fourth alternative, referring to each of FIGS. 5A, 5B and 5C, a first type of vertical-through-via (VTV) connectors 467 may include (1) multiple glass substrates 202, an upper of which may have a bottom surface bonded onto a top surface of a lower one of which, (2) multiple through glass vias (TGVs) 259 in each of the glass substrates 202 and extending vertically through said each of the glass substrates 202, wherein each of the through glass vias (TGVs) 259 may have a thickness between 30 and 100 micrometers, and (3) a glass wetting layer 708, such as a layer of silicon oxide having a thickness between 0.01 and 1 micrometers, at a sidewall of each of the through glass vias (TGVs) 259 in each of the glass substrates 202, around said each of the through glass vias (TGVs) 259 and between said each of the through glass vias (TGVs) 259 and said each of the glass substrates 202. Each of the through glass vias (TGVs) 259 in each of the glass substrates 202 and vertically extending through said each of the glass substrates 202 may include (1) a copper post 706 having a circular shape with a diameter or largest transverse dimension between 3 and 30 micrometers and a height between 30 and 100 micrometers in said each of the glass substrates 202 and vertically extending through said each of the glass substrates 202, wherein the glass wetting layer 708 in said each of the glass substrates 202 may surround the copper post 706, and wherein the copper post 706 may have a top surface coplanar with a top surface of said each of the glass substrates 202 and a bottom surface coplanar with a bottom surface of said each of the glass substrates 202, and (2) a metal lining layer 707, such as a layer of a titanium-tungsten alloy, tungsten, titanium nitride or a high melting-point metal having a melting temperature greater than 1,100 or 1,500 degrees Celsius, having a thickness between 0.1 and 2 micrometers at a sidewall of the copper post 706, around the copper post 706 and between the copper post 706 and the glass wetting layer 708.

[0233] In the fourth alternative, referring to each of FIGS. 5A, 5B and 5C, multiple of the through glass vias (TGVs) 259 may be stacked with each other or one another to form a vertical through via (VTV) 358 for a dedicated vertical path, wherein the copper post 706 of an upper one of the through glass vias (TGVs) 259 may have the bottom surface directly bonded to the top surface of the copper post 706 of a lower one of the through glass vias (TGVs) 259. Each of the vertical through vias (VTVs) 358 may include multiple of the through glass vias (TGVs) 259 stacked up to a total height between 100 and 2,000 micrometers, between 100 and 1,000 micrometers or between 100 and 500 micrometers.

[0234] In the fourth alternative, referring to each of FIGS. 5A, 5B and 5C, the first type of vertical-through-via (VTV) connectors 467 may further include multiple micro-bump or micro-pad 34, which may be of the fifth type having the same specifications as the fifth type of micro-bumps or micro-pads 34 as illustrated in each of FIGS. 4A, 4B and 4C, each on the top surface of the copper post 706 of one of the vertical through vias (VTVs) 358.

[0235] In the fourth alternative, referring to FIG. 5A for the first case, the arrangements for the vertical through vias (VTVs) 358 for the first type of vertical-through-via (VTV) connector 467 may be the same as those as illustrated in FIG. 1A for the first case for the first alternative; the arrangements for the fifth type of micro-bumps or micro-pads 34 for the first type of vertical-through-via (VTV) connector 467 may be the same as those for the first, second, third or fourth type of micro-bumps or micro-pads 34 as illustrated in FIG. 1A for the first case for the first alternative.

[0236] In the fourth alternative, referring to FIG. 5B for the second case, the arrangements for the vertical through vias (VTVs) 358 for the first type of vertical-through-via (VTV) connector 467 may be the same as those as illustrated in FIG. 1C for the second case for the first alternative; the arrangements for the fifth type of micro-bumps or micro-pads 34 for the first type of vertical-through-via (VTV) connector 467 may be the same as those for the first, second, third or fourth type of micro-bumps or micro-pads 34 as illustrated in FIG. 1C for the second case for the first alternative.

[0237] In the fourth alternative, referring to FIG. 5C for the third case, the arrangements for the vertical through vias (VTVs) 358 for the first type of vertical-through-via (VTV) connector 467 may be the same as those as illustrated in FIG. 1A for the third case for the first alternative; the arrangements for the fifth type of micro-bumps or micro-pads 34 for the first type of vertical-through-via (VTV) connector 467 may be the same as those for the first, second, third or fourth type of micro-bumps or micro-pads 34 as illustrated in FIG. 1A for the third case for the first alternative.

[0238] Referring to each of FIGS. 5A-5C for the fourth alternative, the aspect ratio of the length to the width for the first type of vertical-through-via (VTV) connector 467 may be between 2 and 10, between 4 and 10 or between 2 and 40. The first type of vertical-through-via (VTV) connector 467 may be provided with passive elements, such as capacitors, but without any active device, i.e., transistor, therein.

[0239] FIG. 6 is a schematically cross-sectional view showing a first type of vertical-through-via (VTV) connector for a fifth alternative in accordance with an embodiment of the present application. In a fifth alternative, referring to FIG. 6, a first type of vertical-through-via (VTV) connectors 467 may include (1) an epoxy-based polymer layer 317, (2) multiple metal pads 336 at a bottom of the epoxy-based polymer layer 317, wherein each of the metal pads 336 may be made of a nickel layer having a thickness between 1 and 5 micrometers, having a bottom surface coplanar with a bottom surface of the epoxy-based polymer layer 317 and being aligned with one of openings in the epoxy-based polymer layer 317 and at a bottom of said one of the openings in the epoxy-based polymer layer 317, (3) multiple copper posts 318 each in one of the openings in the epoxy-based polymer layer 317 and on a top surface of one of the metal pads 336, wherein each of the copper posts 318 may have a top surface coplanar with a top surface of the epoxy-based polymer layer 317, and (4) multiple sixth type of micro-bumps or micro-pads 34 each on the top surface of one of the copper posts 318, wherein each of the sixth type of micro-bumps or micro-pads 34 may include a nickel layer 320 having a thickness between 1 and 5 micrometers on the top surface of said one of the copper posts 318 and a solder ball 321, such as a tin-silver alloy, having a thickness between 1 and 20 micrometers on a top and side surface of the nickel layer 320. Each of the copper posts 318 and underlying one of the metal pads 336 may be used as a vertical through via (VTV) 358, i.e., through polymer via (TPV), for a dedicated vertical path.

[0240] Referring to each of FIG. 6 for the fifth alternative, the aspect ratio of the length to the width for the first type of vertical-through-via (VTV) connector 467 may be between 2 and 10, between 4 and 10 or between 2 and 40. The first type of vertical-through-via (VTV) connector 467 may be provided with passive elements, such as capacitors, but without any active device, i.e., transistor, therein.

[0241] FIG. 7 is a schematic view showing a block diagram of a programmable logic cell in accordance with an embodiment of the present application. Referring to FIG. 7, a programmable logic block (LB) or element may include one or a plurality of programmable logic cells (LC) 2014 each configured to perform logic operation on its input data set at its input points. Each of the programmable logic cells (LC) 2014 may include multiple memory cells 490, i.e., configuration-programming-memory (CPM) cells, each configured to save or store one of resulting values of a look-up table (LUT) 210 and a selection circuit 211, such as multiplexer (MUXER), having a first set of two input points arranged in parallel for a first input data set, e.g., A0 and A1, and a second set of four input points arranged in parallel for a second input data set, e.g., D0, D1, D2 and D3, each associated with one of the resulting values or programming codes of the look-up table (LUT) 210. The selection circuit 211 is configured to select, in accordance with its first input data set associated with the input data set of said each of the programmable logic cells (LC) 2014, a data input, e.g., D0, D1, D2 or D3, from its second input data set as a data output Dout at its output point acting as a data output of said each of the programmable logic cells (LC) 2014 at an output point of said each of the programmable logic cells (LC) 2014.

[0242] Referring to FIG. 7, the selection circuit 211 may have the second input data set, e.g., D0, D1, D2 and D3, each associated with a data output, i.e., configuration-programming-memory (CPM) data, of one of the memory cells 490, i.e., configuration-programming-memory (CPM) cells. For each of the programmable logic cells (LC) 2014, each of the resulting values or programing codes of its look-up table (LUT) 210 stored in one of its memory cells 490 that may be of a first type, i.e., volatile memory cell such as static random-access memory (SRAM) cell, may be associated with data saved or stored in a non-volatile memory cell, such as ferroelectric random-access-memory (FRAM) cell, magnetoresistive random access memory (MRAM) cell, resistive random access memory (RRAM) cell, anti-fuse or e-fuse. Alternatively, for each of the programmable logic cells (LC) 2014, each of its memory cells 490 may be of a second type, i.e., non-volatile memory cell composed of one or more magnetoresistive random access memory (MRAM) cells, one or more resistive random access memory (RRAM) cells, one or more anti-fuses, one or more e-fuses, or a floating gate of a metal-oxide-semiconductor (MOS) transistor.

[0243] Referring to FIG. 7, each of the programmable logic cells (LC) 2014 may have the memory cells 490, i.e., configuration-programming-memory (CPM) cells, configured to be programed to store or save the resulting values or programing codes of the look-up table (LUT) 210 to perform the logic operation, such as AND operation, NAND operation, OR operation, NOR operation, EXOR operation or other Boolean operation, or an operation combining two or more of the above operations. For this case, each of the programmable logic cells (LC) 2014 may perform the logic operation on its input data set, e.g., A0 and A1, at its input points as a data output Dout at its output point. For more elaboration, each of the programmable logic cells (LC) 2014 may include the number 2ⁿ of memory cells 490, i.e., configuration-programming-memory (CPM) cells, each configured to save or store one of resulting values of the look-up table (LUT) 210 and the selection circuit 211 having a first set of the number n of input points arranged in parallel for a first input data set, e.g., A0-A1, and a second set of the number 2ⁿ of input points arranged in parallel for a second input data set, e.g., D0-D3, each associated with one of the resulting values or programming codes of the look-up table (LUT) 210, wherein the number n may range from 2 to 8, such as 2 for this case. The selection circuit 211 is configured to select, in accordance with its first input data set associated with the input data set of said each of the programmable logic cells (LC) 2014, a data input, e.g., one of D0-D3, from its second input data set as a data output Dout at its output point acting as a data output of said each of the programmable logic cells (LC) 2014 at an output point of said each of the programmable logic cells (LC) 2014.

[0244] FIG. 8 is a circuit diagram illustrating programmable interconnects controlled by a programmable switch cell in accordance with an embodiment of the present application. Referring to FIG. 8, a cross-point switch may be provided for a programmable switch cell 379, i.e., configurable switch cell, including four selection circuits 211 at its top, bottom, left and right sides respectively, each having a multiplexer 213 and a pass/no-pass switch or switch buffer 292 coupling to the multiplexer 213 thereof, and four sets of memory cells 362 each configured to save or store programming codes to control the multiplexer 213 and pass/no-pass switch or switch buffer 292 of one of its four selection circuits 211. For the programmable switch cell 379, the multiplexer 213 of each of its four selection circuits 211 may be configured to select, in accordance with the first input data set thereof at the first set of input points thereof each associated with one of the programming codes saved or stored in its memory cells 362, a data input from the second input data set thereof at the second set of input points thereof as the data output thereof. The pass/no-pass switch 292 of each of its four selection circuits 211 is configured to control, in accordance with a first data input thereof associated with another of the programming codes saved or stored in its memory cells 362, coupling between the input point thereof for a second data input thereof associated with the data output of the multiplexer 213 of said each of its four selection circuits 211 and the output point thereof for a data output thereof and amplify the second data input thereof as the data output thereof to act as a data output of said each of its four selection circuits 211. Each of the second set of three input points of the multiplexer 213 of one of its four selection circuits 211 may couple to one of the second set of three input points of the multiplexer 213 of each of another two of its four selection circuits 211 and to one of the four programmable interconnects 361 coupling to the output point of the other of its four selection circuits 211. Each of the four programmable interconnects 361 may couple to the output point of one of its four selection circuits 211 and one of the second set of three input points of the multiplexer 213 of each of the other three of its four selection circuits 211. Thereby, for each of the four selection circuits 211 of the programmable switch cell 379, its multiplexer 213 may select, in accordance with the first input data set thereof at the first set of input points thereof, a data input from the second input data set thereof at the second set of three input points thereof coupling to respective three of four nodes N23-N26 coupling to respective three of four programmable interconnects 361 extending in four different directions respectively, and its second type of pass/no-pass switch 292 is configured to generate the data output of said each of the four selection circuits 211 at the other of the four nodes N23-N26 coupling to the other of the four programmable interconnects 361.

[0245] For example, referring to FIG. 8, for the top one of the four selection circuits 211 of the programmable switch cell 379, its multiplexer 213 may select, in accordance with the first input data set thereof at the first set of input points thereof each associated with one of the programming codes saved or stored in the memory cells 362 of the programmable switch cell 379, a data input from the second input data set thereof at the second set of three input points thereof coupling to the respective three nodes N24-N26 coupling to the respective three programmable interconnects 361 extending in left, down and right directions respectively, and its pass/no-pass switch 292 is configured, in accordance with another of the programming codes saved or stored in the memory cells 362 of the programmable switch cell 379, to or not to generate the data output of the top one of the four selection circuits 211 of the programmable switch cell 379 at the node N23 coupling to the programmable interconnect 361 extending in an up direction. Thereby, data from one of the four programmable interconnects 361 may be switched by the programmable switch cell 379 to be passed to another one, two or three of the four programmable interconnects 361.

[0246] Referring to FIG. 8, for the programmable switch cell 379, each of the programming codes saved or stored in one of the memory cells 362 that may be of a first type, i.e., volatile memory cell such as static random-access memory (SRAM) cell, may be associated with data saved or stored in a non-volatile memory cell, such as ferroelectric random-access-memory (FRAM) cell, magnetoresistive random access memory (MRAM) cell, resistive random access memory (RRAM) cell, anti-fuse or e-fuse. Alternatively, for the programmable switch cell 379, each of its memory cells 362 may be of a second type, i.e., non-volatile memory cell composed of one or more magnetoresistive random access memory (MRAM) cells, one or more resistive random access memory (RRAM) cells, one or more anti-fuses, one or more e-fuses, or a floating gate of a metal-oxide-semiconductor (MOS) transistor.

[0247] FIG. 9 is a schematically top view showing a block diagram of a standard commodity FPGA IC chip in accordance with an embodiment of the present application. Referring to FIG. 9, the standard commodity FPGA IC chip 200 may include (1) a plurality of programmable logic blocks 201 arranged in an array in a central region thereof, wherein each of the programmable logic blocks 201 may be arranged with multiple programmable logic cells (LC) 2014 as illustrated in FIG. 7 coupling to one another, (2) a plurality of programmable switch cells 379 as illustrated in FIG. 8 arranged around each of the programmable logic blocks (LB) 201, (3) multiple intra-chip interconnects 502 each extending over spaces between neighboring two of the programmable logic blocks 201, wherein the intra-chip interconnects 502 may include the programmable interconnects 361 as seen in FIG. 8 configured to be programmed for interconnection by its memory cells 362 and the non-programmable interconnects 364 as illustrated in FIG. 8 configured not to be programmable for interconnection, and (4) multiple I/O ports 377 having the number ranging from 2 to 64 for example, such as I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4 for this case. Each of the I/O ports 377 may include (1) the small I/O circuits 203 having the number ranging from 4 to 256, such as 64 for this case, arranged in parallel for data transmission with bit width ranging from 4 to 256, such as 64 for this case, and (2) the I/O pads 372 having the number ranging from 4 to 256, such as 64 for this case, arranged in parallel and vertically over the small I/O circuits 203 respectively. Each of its small input/output (I/O) circuits 203 may include a small driver configured to drive data to its external circuits in the same chip package and a small receiver configured to receive data from its external circuits in the same chip package, wherein each of its small input/output (I/O) circuits 203 may have an output capacitance or driving capability or loading, for example, between 0.05 pF and 2 pF or between 0.05 pF and 1 pF, or smaller than 2 pF or 1 pF, and an input capacitance between 0.15 pF and 4 pF or between 0.15 pF and 2 pF, or greater than 0.15 pF; alternatively, each of its small input/output (I/O) circuits 203 may have an I/O power efficiency smaller than 0.5 pico-Joules per bit, per switch or per voltage swing, or between 0.01 and 0.5 pico-Joules per bit, per switch or per voltage swing.

[0248] Referring to FIG. 9, in a first clock cycle, for one of the small input/output (I/O) circuits 203 of the standard commodity FPGA IC chip 200, its small driver may be enabled by a data input at a first input point of its small driver and its small receiver may be inhibited by a data input at a first input point of its small receiver. Thereby, its small driver may amplify a data input at a second input point of its small driver, associated with the resulting value or programming code from one of the memory cells 490 of one of the programmable logic cells 2014 of the standard commodity FPGA IC chip 200 or one of the memory cells 362 of one of the programmable switch cells 379 of the standard commodity FPGA IC chip 200, as a data output of its small driver at an output point of its small driver to be transmitted to one of the I/O pads 372 vertically over said one of the small input/output (I/O) circuits 203 for external connection to the external circuits of the standard commodity FPGA IC chip 200, such as non-volatile memory (NVM) integrated-circuit (IC) chip.

[0249] In a second clock cycle, for said one of the small input/output (I/O) circuits 203 of the standard commodity FPGA IC chip 200, its small driver may be disabled by a data input at the first input point of its small driver and its small receiver may be activated by a data input at the first input point of its small receiver. Thereby, its small receiver may amplify a data input, i.e., a resulting value or programming code, at a second input point of its small receiver associated with data passed from the external circuits of the standard commodity FPGA IC chip 200, such as non-volatile memory (NVM) integrated-circuit (IC) chip, through said one of the I/O pads 372 as an data output of its small receiver at an output point of its small receiver to be passed to and stored in one of the memory cells 490 of one of the programmable logic cells 2014 of the standard commodity FPGA IC chip 200 or one of the memory cells 362 of one of the programmable switch cells 379 of the standard commodity FPGA IC chip 200.

[0250] In a third clock cycle, for said one of the small input/output (I/O) circuits 203 of the standard commodity FPGA IC chip 200, its small driver may be enabled by a data input at the first input point of its small driver and its small receiver may be inhibited by a data input at the first input point of its small receiver. Thereby, its small driver may amplify a data input at the second input point of its small driver, associated with the data output of one of the programmable logic cells 2014 of the standard commodity FPGA IC chip 200 as illustrated in FIG. 7 for example through first one or more of the programmable interconnects 361 of the standard commodity FPGA IC chip 200 and/or one or more of the programmable switch cells 379 of the standard commodity FPGA IC chip 200 each coupled between two of said first one or more of the programmable interconnects 361, as a data output of its small driver at the output point of its small driver to be transmitted to said one of the I/O pads 372 vertically over said one of the small input/output (I/O) circuits 203 for external connection to circuits outside the standard commodity FPGA IC chip 200, such as non-volatile memory (NVM) integrated-circuit (IC) chip.

[0251] In a fourth clock cycle, for said one of the small input/output (I/O) circuits 203 of the standard commodity FPGA IC chip 200, its small driver may be disabled by a data input at the first input point of its small driver and its small receiver may be activated by a data input at the first input point of its small receiver. Thereby, its small receiver may amplify a data input at the second input point of its small receiver transmitted from circuits, such as non-volatile memory (NVM) integrated-circuit (IC) chip, outside the standard commodity FPGA IC chip 200 through said one of the I/O pads 372 as a data output of its small receiver at the output point of its small driver associated with a data input of the input data set of one of the programmable logic cells 2014 of the standard commodity FPGA IC chip 200 as illustrated in FIG. 7 for example through second one or more of the programmable interconnects 361 of the standard commodity FPGA IC chip 200 and/or one or more of the programmable switch cells 379 of the standard commodity FPGA IC chip 200 each coupled between two of said second one or more of the programmable interconnects 361.

[0252] Referring to FIG. 9, the standard commodity FPGA IC chip 200 may further include a chip-enable (CE) pad 209 configured for enabling or disabling the standard commodity FPGA IC chip 200. For example, when the chip-enable (CE) pad 209 is at a logic level of “0”, the standard commodity FPGA IC chip 200 may be enabled to process data and/or operate with circuits outside of the standard commodity FPGA IC chip 200; when the chip-enable (CE) pad 209 is at a logic level of “1”, the standard commodity FPGA IC chip 200 may be disabled not to process data and/or operate with circuits outside of the standard commodity FPGA IC chip 200.

[0253] Referring to FIG. 9, the standard commodity FPGA IC chip 200 may further include multiple input selection (IS) pads 231, e.g., IS1, IS2, IS3 and IS4 pads, each configured to receive a data input associated with the data input at the first input point of the small receiver of each of the small I/O circuits 203 of one of its I/O ports 377, e.g., I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4. For more elaboration, for the standard commodity FPGA IC chip 200, its IS1 pad 231 may receive a data input associated with the data input at the first input point of the small receiver of each of the small I/O circuits 203 of its I/O Port 1; its IS2 pad 231 may receive a data input associated with the data input at the first input point of the small receiver of each of the small I/O circuits 203 of its I/O Port 2; its IS3 pad 231 may receive a data input associated with the data input at the first input point of the small receiver of each of the small I/O circuits 203 of its I/O Port 3; and its IS4 pad may receive a data input associated with the data input at the first input point of the small receiver of each of the small I/O circuits 203 of its I/O Port 4. The standard commodity FPGA IC chip 200 may select, in accordance with logic levels at the input selection (IS) pads 231, e.g., IS1, IS2, IS3 and IS4 pads, one or more from its I/O ports 377, e.g., I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4, to pass data for its input operation. For each of the small I/O circuits 203 of each of the one or more I/O ports 377 selected in accordance with the logic levels at the input selection (IS) pads 231, its small receiver may be activated by the data input at the first input point of its small receiver transmitted from circuits outside of the standard commodity FPGA IC chip 200 through one of the input selection (IS) pads 231 to amplify or pass the data input at the second input point of its small receiver, transmitted from circuits outside the standard commodity FPGA IC chip 200 through one of the I/O pads 372 of said each of the one or more I/O ports 377 selected in accordance with the logic levels at the input selection (IS) pads 231, as the data output of its small receiver associated with a data input of the input data set of one of the programmable logic cells 2014 as seen in FIG. 7 of the standard commodity FPGA IC chip 200 through one or more of the programmable interconnects 361 as seen in FIG. 8 of the standard commodity FPGA IC chip 200, for example. For each of the small I/O circuits 203 of each of the I/O ports 377, not selected in accordance with in accordance with the logic levels at the input selection (IS) pads 231, of the standard commodity FPGA IC chip 200, its small receiver 375 may be inhibited by the data input at the first input point of its small receiver associated with the logic level at one of the input selection (IS) pads 231 of the standard commodity FPGA IC chip 200.

[0254] For example, referring to FIG. 9, provided that the standard commodity FPGA IC chip 200 may have (1) the chip-enable (CE) pad 209 at a logic level of “0”, (2) the IS1 pad 231 at a logic level of “1”, (3) the IS2 pad 231 at a logic level of “0”, (4) the IS3 pad 231 at a logic level of “0” and (5) the IS4 pad 231 at a logic level of “0”, the standard commodity FPGA IC chip 200 may be enabled in accordance with the logic level at its chip-enable (CE) pad 209 and may select, in accordance with the logic levels at its IS1, IS2, IS3 and IS4 pads 231, one or more I/O port, e.g., I/O Port 1, from its I/O ports 377, i.e., I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4, to pass data for the input operation. For each of the small I/O circuits 203 of the selected I/O port 377, i.e., I/O Port 1, of the standard commodity FPGA IC chip 200, its small receiver may be activated by the data input at the first input point of its small receiver associated with the logic level at the IS1 pad 231 of the standard commodity FPGA IC chip 200. For each of the small I/O circuits 203 of each of the unselected I/O ports, i.e., I/O Port 2, I/O Port 3 and I/O Port 4, of the standard commodity FPGA IC chip 200, its small receiver may be inhibited by the data input at the first input point of its small receiver associated with the logic level at one of the IS2, IS3 and IS4 pads 231 of the standard commodity FPGA IC chip 200.

[0255] For example, referring to FIG. 9, provided that the standard commodity FPGA IC chip 200 may have (1) the chip-enable (CE) pad 209 at a logic level of “0”, (2) the IS1 pad 231 at a logic level of “1”, (3) the IS2 pad 231 at a logic level of “1”, (4) the IS3 pad 231 at a logic level of “1” and (5) the IS4 pad 231 at a logic level of “1”, the standard commodity FPGA IC chip 200 may be enabled in accordance with the logic level at its chip-enable (CE) pad 209 and may select, in accordance with the logic levels at its IS1, IS2, IS3 and IS4 pads 231, all from its I/O ports 377, i.e., I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4, to pass data for the input operation at the same clock cycle. For each of the small I/O circuits 203 of each of the selected I/O ports 377, i.e., I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4, of the standard commodity FPGA IC chip 200, its small receiver may be activated by the data input at the first input point of its small receiver associated with the logic level at one of the IS1, IS2, IS3 and IS4 pads 231 of the standard commodity FPGA IC chip 200.

[0256] Referring to FIG. 9, the standard commodity FPGA IC chip 200 may include multiple output selection (OS) pads 232, e.g., OS1, OS2, OS3 and OS4 pads, each configured to receive a data input associated with the data input at the first input point of the small driver of each of the small I/O circuits 203 of one of its I/O ports 377, e.g., I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4. For more elaboration, for the standard commodity FPGA IC chip 200, its OS1 pad 232 may receive a data input associated with the data input at the first input point of the small driver of each of the small I/O circuits 203 of its I/O Port 1; its OS2 pad 232 may receive a data input associated with the data input at the first input point of the small driver of each of the small I/O circuits 203 of its I/O Port 2; its OS3 pad 232 may receive a data input associated with the data input at the first input point of the small driver of each of the small I/O circuits 203 of its I/O Port 3; its OS4 pad 232 may receive a data input associated with the data input at the first input point of the small driver of each of the small I/O circuits 203 of its I/O Port 4. The standard commodity FPGA IC chip 200 may select, in accordance with logic levels at the output selection (OS) pads 232, e.g., OS1, OS2, OS3 and OS4 pads, one or more from its I/O ports 377, e.g., I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4, to pass data for its output operation. For each of the small I/O circuits 203 of each of the one or more I/O ports 377 selected in accordance with the logic levels at the output selection (OS) pads 232, its small driver may be enabled by the data input at the first input point of its small driver transmitted from circuits outside of the standard commodity FPGA IC chip 200 through one of the output selection (OS) pads 232 to amplify or pass the data input at the second input point of its small driver, associated with the data output of one of the programmable logic cells 2014 as seen in FIG. 7 of the standard commodity FPGA IC chip 200 through one or more of the programmable interconnects 361 as seen in FIG. 8 of the standard commodity FPGA IC chip 200, as the data output of its small driver to be transmitted to circuits outside the standard commodity FPGA IC chip 200 through one of the I/O pads 372 of said each of the one or more I/O ports 377 selected in accordance with the logic levels at the output selection (OS) pads 232, for example. For each of the small I/O circuits 203 of each of the I/O ports 377, not selected in accordance with in accordance with the logic levels at the output selection (OS) pads 232, of the standard commodity FPGA IC chip 200, its small driver may be disabled by the data input at the first input point of its small driver associated with the logic level at one of the output selection (OS) pads 232 of the standard commodity FPGA IC chip 200.

[0257] For example, referring to FIG. 9, provided that the standard commodity FPGA IC chip 200 may have (1) the chip-enable (CE) pad 209 at a logic level of “0”, (2) the OS1 pad 232 at a logic level of “0”, (3) the OS2 pad 232 at a logic level of “1”, (4) the OS3 pad 232 at a logic level of “1” and (5) the OS4 pad 232 at a logic level of “1”, the standard commodity FPGA IC chip 200 may be enabled in accordance with the logic level at its chip-enable (CE) pad 209 and may select, in accordance with the logic levels at its OS1, OS2, OS3 and OS4 pads 232, one or more I/O port, e.g., I/O Port 1, from its I/O ports 377, i.e., I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4, to pass data for the output operation. For each of the small I/O circuits 203 of the selected I/O port 377, i.e., I/O Port 1, of the standard commodity FPGA IC chip 200, its small driver may be enabled by the data input at the first input point of its small driver associated with the logic level at the OS1 pad 232 of the standard commodity FPGA IC chip 200. For each of the small I/O circuits 203 of each of the unselected I/O ports, i.e., I/O Port 2, I/O Port 3 and I/O Port 4, of the standard commodity FPGA IC chip 200, its small driver may be disabled by the data input at the first input point of its small driver associated respectively with the logic level at one of the OS2, OS3 and OS4 pads 232 of the standard commodity FPGA IC chip 200.

[0258] For example, referring to FIG. 9, provided that the standard commodity FPGA IC chip 200 may have (1) the chip-enable (CE) pad 209 at a logic level of “0”, (2) the OS1 pad 232 at a logic level of “0”, (3) the OS2 pad 232 at a logic level of “0”, (4) the OS3 pad 232 at a logic level of “0” and (5) the OS4 pad 232 at a logic level of “0”, the standard commodity FPGA IC chip 200 may be enabled in accordance with the logic level at its chip-enable (CE) pad 209 and may select, in accordance with the logic levels at its OS1, OS2, OS3 and OS4 pads 232, all from its I/O ports 377, i.e., I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4, to pass data for the output operation at the same clock cycle. For each of the small I/O circuits 203 of each of the selected I/O ports 377, i.e., I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4, of the standard commodity FPGA IC chip 200, its small driver may be enabled by the data input at the first input point of its small driver associated with the logic level at one of the OS1, OS2, OS3 and OS4 pads 232 of the standard commodity FPGA IC chip 200.

[0259] Thereby, referring to FIG. 9, in a clock cycle, for the standard commodity FPGA IC chip 200, one or more of its I/O ports 377, i.e., I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4, may be selected, in accordance with the logic levels at its IS1, IS2, IS3 and IS4 pads 231, to pass data for its input operation, while another one or more of its I/O ports 377, i.e., I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4, may be selected, in accordance with the logic levels at its OS1, OS2, OS3 and OS4 pads 232, to pass data for its output operation. Its input selection (IS) pads 231 and output selection (OS) pads 232 may be provided as I/O-port selection pads.

[0260] Referring to FIG. 9, the standard commodity FPGA IC chip 200 may further include (1) multiple power pads 205 for applying the voltage Vcc of power supply to its memory cells 490 for the look-up tables (LUT) 210 of its programmable logic cells (LC) 2014 as illustrated in FIG. 7, the selection circuits 211 of its programmable logic cells (LC) 2014, the memory cells 362 of its programmable switch cells 379 as illustrated in FIG. 8, the selection circuits 211 of its programmable switch cells 379 and/or the small drivers and receivers of its small I/O circuits 203 through one or more of its non-programmable interconnects 364, wherein the voltage Vcc of power supply may be between 0.2V and 2.5V, between 0.2V and 2V, between 0.2V and 1.5V, between 0.1V and 1V, or between 0.2V and 1V, or, smaller or lower than or equal to 2.5V, 2V, 1.8V, 1.5V or 1V, and (2) multiple ground pads 206 for providing the voltage Vss of ground reference to its memory cells 490 for the look-up tables (LUT) 210 of its programmable logic cells (LC) 2014 as illustrated in FIG. 7, the selection circuits 211 of its programmable logic cells (LC) 2014, the memory cells 362 of its programmable switch cells 379 as illustrated in FIG. 8, the selection circuits 211 of its programmable switch cells 379 and/or the small drivers 374 and receivers 375 of its small I/O circuits 203 through one or more of its non-programmable interconnects 364.

[0261] Referring to FIG. 9, the standard commodity FPGA IC chip 200 may further include a clock pad (CLK) 229 configured to receive a clock signal from circuits outside of the standard commodity FPGA IC chip 200 and multiple control pads (CP) 378 configured to receive control commands to control the standard commodity FPGA IC chip 200.

[0262] Referring to FIG. 9, for the standard commodity FPGA IC chip 200, its programmable logic cells (LC) 2014 as seen in FIG. 7 may be reconfigurable for artificial-intelligence (AI) application. For example, in a clock cycle, one of the programmable logic cells (LC) 2014 of the standard commodity FPGA IC chip 200 may have the memory cells 490 to be programmed to perform OR operation; however, after one or more events happens, in another clock cycle said one of its programmable logic cells (LC) 2014 of the standard commodity FPGA IC chip 200 may have the memory cells 490 to be programmed to perform NAND operation for better AI performance.

[0263] Referring to FIG. 9, the standard commodity FPGA IC chip 200 may include a cryptography block or circuit configured to decrypt, in accordance with a password or key stored or saved in a non-volatile memory cell of its cryptography block or circuit, which may be composed of one or more magnetoresistive random access memory (MRAM) cells, one or more resistive random access memory (RRAM) cells, one or more anti-fuses, one or more e-fuses, or a floating gate of a metal-oxide-semiconductor (MOS) transistor, encrypted data from a memory integrated-circuit (IC) chip as decrypted data to be passed to the memory cells 490 for the look-up tables (LUT) 210 of its programmable logic cells (LC) 2014 or the memory cells 362 of its programmable switch cells 379 and to encrypt, in accordance with the password or key, data from the memory cells 490 for the look-up tables (LUT) 210 of its programmable logic cells (LC) 2014 or the memory cells 362 of its programmable switch cells 379 as encrypted data to be passed to the memory integrated-circuit (IC) chip.

[0264] Referring to FIG. 9, the standard commodity FPGA IC chip 200 may include a plurality of large input/output (I/O) circuits each having a large driver configured to drive data to its external circuits in a different chip package and a large receiver configured to receive data from its external circuits in a different chip package, wherein each of its large input/output (I/O) circuits may have an output capacitance or driving capability or loading, for example, between 2 pF and 100 pF, between 2 pF and 50 pF, between 2 pF and 30 pF, between 2 pF and 20 pF, between 2 pF and 15 pF, between 2 pF and 10 pF, or between 2 pF and 5 pF, or greater than 2 pF, 5 pF, 10 pF, 15 pF or 20 pF, and an input capacitance between 0.15 pF and 4 pF or between 0.15 pF and 2 pF, or greater than 0.15 pF; alternatively, each of its large input/output (I/O) circuits may have an I/O power efficiency greater than 3, 5 or 10 pico-Joules per bit, per switch or per voltage swing.

[0265] FIG. 10 is a schematically top view showing a block diagram of a dedicated programmable interconnection (DPI) integrated-circuit (IC) chip in accordance with an embodiment of the present application. Referring to FIG. 10, a dedicated programmable interconnection (DPI) integrated-circuit (IC) chip 410 may include (1) multiple memory-array blocks 423 arranged in an array in a central region thereof, (2) multiple groups of programmable switch cells 379 as illustrated in FIG. 8, each group of which is arranged in one or more rings around one of the memory-array blocks 423, and (3) multiple small input/output (I/O) circuits 203 each having a small receiver configured to generate a data output associated with a data input at one of the nodes N23-N26 of one of its programmable switch cells 379 as illustrated in FIG. 8 through one or more of its programmable interconnects 361 and a small driver configured to receive a data input associated with a data output at one of the nodes N23-N26 of another of its programmable switch cells 379 as illustrated in FIG. 8 through another one or more of its programmable interconnects 361, wherein each of its small input/output (I/O) circuits 203 may include a small driver configured to drive data to its external circuits in the same chip package and a small receiver configured to receive data from its external circuits in the same chip package, and each of its small input/output (I/O) circuits 203 may have an output capacitance or driving capability or loading, for example, between 0.05 pF and 2 pF or between 0.05 pF and 1 pF, or smaller than 2 pF or 1 pF, and an input capacitance between 0.15 pF and 4 pF or between 0.15 pF and 2 pF, or greater than 0.15 pF; alternatively, each of its small input/output (I/O) circuits 203 may have an I/O power efficiency smaller than 0.5 pico-Joules per bit, per switch or per voltage swing, or between 0.01 and 0.5 pico-Joules per bit, per switch or per voltage swing.

[0266] Referring to FIG. 10, for the DPIIC chip 410, each of its programmable switch cells 379 as seen in FIG. 8 may include the memory cells 362 in one of its four memory-array blocks 423 arranged in an array and the selection circuits 211 close to said one of its memory-array blocks 423, wherein each of the selection circuits 211 of said each of its programmable switch cells 379 may have the first set of input points for multiple data inputs of the first input data set of said each of its selection circuits 211 each associated with a data output, i.e., configuration-programming-memory (CPM) data, of one of the memory cells 362, i.e., configuration-programming-memory (CPM) cells, of said each of its programmable switch cells 379.

[0267] Referring to FIG. 10, the DPIIC chip 410 may include the I/O pads 372 each vertically over one of its small input/output (I/O) circuits 203. For one of the small input/output (I/O) circuits 203 of the DPIIC chip 410, in a first clock cycle, data from one of the nodes N23-N26 of one of the programmable switch cells 379 of the DPIIC chip 410 as illustrated in FIG. 8 may be associated with the data input of its small driver through one or more of the programmable interconnects 361 programmed by a first group of the programmable switch cells 379 of the DPIIC chip 410 and then its small driver may amplify or pass the data input of its small driver as a data output of its small driver to be transmitted to one of the I/O pads 372 of the DPIIC chip 410 vertically over said one of the small input/output (I/O) circuits 203 of the DPIIC chip 410 for external connection to circuits outside the DPIIC chip 410. In a second clock cycle, data from circuits outside the DPIIC chip 410 may be associated with a data input of its small receiver through said one of the I/O pads 372 of the DPIIC chip 410, and then its small receiver may amplify or pass the data input of its small receiver as a data output of its small receiver to be passed to one of the nodes N23-N26 of another of the programmable switch cells 379 of the DPIIC chip 410 as illustrated in FIG. 8 through another one or more of the programmable interconnects 361 programmed by a second group of the programmable switch cells 379 of the DPIIC chip 410.

[0268] Referring to FIG. 10, the DPIIC chip 410 may further include (1) multiple power pads 205 for applying the voltage Vcc of power supply to the memory cells 362 of its programmable switch cells 379 as illustrated in FIG. 8 and/or the selection circuits 211 of its programmable switch cells 379, wherein the voltage Vcc of power supply may be between 0.2V and 2.5V, between 0.2V and 2V, between 0.2V and 1.5V, between 0.1V and 1V, or between 0.2V and 1V, or, smaller or lower than or equal to 2.5V, 2V, 1.8V, 1.5V or 1V, and (2) multiple ground pads 206 for providing the voltage Vss of ground reference to the memory cells 362 of its programmable switch cells 379 as illustrated in FIG. 8 and/or the selection circuits 211 of its programmable switch cells 379.

[0269] Referring to FIG. 10, the DPIIC chip 410 may further include multiple SRAM cells used as cache memory for data latch or storage and a sense amplifier configured for reading, amplifying or detecting data from its SRAM cells acting as the cache memory.

[0270] Referring to FIG. 10, the DPIIC chip 410 may include a plurality of large input/output (I/O) circuits each having a large driver configured to drive data to its external circuits in a different chip package and a large receiver configured to receive data from its external circuits in a different chip package, wherein each of its large input/output (I/O) circuits may have an output capacitance or driving capability or loading, for example, between 2 pF and 100 pF, between 2 pF and 50 pF, between 2 pF and 30 pF, between 2 pF and 20 pF, between 2 pF and 15 pF, between 2 pF and 10 pF, or between 2 pF and 5 pF, or greater than 2 pF, 5 pF, 10 pF, 15 pF or 20 pF, and an input capacitance between 0.15 pF and 4 pF or between 0.15 pF and 2 pF, or greater than 0.15 pF; alternatively, each of its large input/output (I/O) circuits may have an I/O power efficiency greater than 3, 5 or 10 pico-Joules per bit, per switch or per voltage swing.

[0271] FIG. 11 is a schematically top view showing a block diagram of an auxiliary and supporting (AS) integrated-circuit (IC) chip in accordance with an embodiment of the present application. Referring to FIG. 11, the auxiliary and supporting (AS) integrated-circuit (IC) chip 411 may include one, more or all of the following circuit blocks: (1) a large-input/output (I/O) block 412 configured for serial-advanced-technology-attachment (SATA) ports or peripheral-components-interconnect express (PCIe) ports each having a plurality of large input/output (I/O) circuits configured to couple to a memory integrated-circuit (IC) chip, such as non-volatile memory (NVM) integrated-circuit (IC) chip, NAND flash memory integrated-circuit (IC) chip or NOR flash memory integrated-circuit (IC) chip, for data transmission between the auxiliary and supporting (AS) integrated-circuit (IC) chip 411 and the memory integrated-circuit (IC) chip, wherein each of the large input/output (I/O) circuits may have an output capacitance or driving capability or loading, for example, between 2 pF and 100 pF, between 2 pF and 50 pF, between 2 pF and 30 pF, between 2 pF and 20 pF, between 2 pF and 15 pF, between 2 pF and 10 pF, or between 2 pF and 5 pF, or greater than 2 pF, 5 pF, 10 pF, 15 pF or 20 pF, and an input capacitance between 0.15 pF and 4 pF or between 0.15 pF and 2 pF, or greater than 0.15 pF for example, and alternatively each of the large input/output (I/O) circuits may have an I/O power efficiency greater than 3, 5 or 10 pico-Joules per bit, per switch or per voltage swing, (2) a small-input/output (I/O) block 413 having a plurality of small input/output (I/O) circuits configured to couple to a logic integrated-circuit (IC) chip, such as field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, central-processing-unit (CPU) integrated-circuit (IC) chip, graphic-processing-unit (GPU) integrated-circuit (IC) chip, application-processing-unit (APU) chip or digital-signal-processing (DSP) integrated-circuit (IC) chip, for data transmission between the auxiliary and supporting (AS) integrated-circuit (IC) chip 411 and the logic integrated-circuit (IC) chip, wherein each of the small input/output (I/O) circuits may have an output capacitance or driving capability or loading, for example, between 0.05 pF and 2 pF or between 0.05 pF and 1 pF, or smaller than 2 pF or 1 pF, and an input capacitance between 0.15 pF and 4 pF or between 0.15 pF and 2 pF, or greater than 0.15 pF for example, and alternatively each of the small input/output (I/O) circuits may have an I/O power efficiency smaller than 0.5 pico-Joules per bit, per switch or per voltage swing, or between 0.01 and 0.5 pico-Joules per bit, per switch or per voltage swing, (3) a cryptography block or circuit 517 configured to decrypt, in accordance with a password or key stored or saved in a non-volatile memory cell composed of one or more magnetoresistive random access memory (MRAM) cells, one or more resistive random access memory (RRAM) cells, one or more anti-fuses, one or more e-fuses, or a floating gate of a metal-oxide-semiconductor (MOS) transistor, encrypted data from the memory integrated-circuit (IC) chip as decrypted data to be passed to the logic integrated-circuit (IC) chip and to encrypt, in accordance with the password or key, data from the logic integrated-circuit (IC) chip as encrypted data to be passed to the memory integrated-circuit (IC) chip, (4) a regulating block 415 configured to regulate a voltage of power supply from an input voltage of 12, 5, 3.3 or 2.5 volts as an output voltage of 3.3, 2.5, 1.8, 1.5, 1.35, 1.2, 1.0, 0.75 or 0.5 volts to be delivered to the logic integrated-circuit (IC) chip, and (5) an innovated application-specific-integrated-circuit (ASIC) or customer-owned tooling (COT) block 418, i.e., IAC block, configured to implement intellectual-property (IP) circuits, application-specific (AS) circuits, analog circuits, mixed-mode signal circuits, radio-frequency (RF) circuits, and/or transmitter, receiver, transceiver circuits for customers.

[0272] FIG. 12A is a schematically top view showing arrangement for various semiconductor integrated-circuit (IC) chips or operation units packaged in a standard commodity logic drive in accordance with an embodiment of the present application. Referring to FIG. 12A, a standard commodity logic drive 300 may be packaged with a standard commodity FPGA IC chip 200, graphic-processing-unit (GPU) integrated-circuit (IC) chip 269a, central-processing-unit (CPU) integrated-circuit (IC) chip 269b, tensor-processing-unit (TPU) integrated-circuit (IC) chip 269c, network-processing-unit (NPU) integrated-circuit (IC) chip 269d and digital-signal-processing (DSP) integrated-circuit (IC) chip 270 each assembled in a single-die type or in an operation unit (OU) 190 as seen in FIGS. 17F, 17G, 19G, 19H, 20A, 20B, 21A, 21B, 22H, 23B, 27G, 30C, 34H, 37C, 38B, 39A, 42E, 45B and 48A. Further, the standard commodity logic drive 300 may be packaged with one or more auxiliary and supporting (AS) integrated-circuit (IC) chips 411 (only one is shown therein) each assembled in a single-die type or in an operation unit (OU) 190 as seen in FIGS. 17F, 17G, 19G, 19H, 20A, 20B, 21A, 21B, 22H, 23B, 27G, 30C, 34H, 37C, 38B, 39A, 42E, 45B and 48A. Further, the standard commodity logic drive 300 may be packaged with multiple high-bandwidth-memory (HBM) integrated-circuit (IC) chips 251 each assembled in a single-die type or in an operation unit (OU) 190 as seen in FIGS. 17F, 17G, 19G, 19H, 20A, 20B, 21A, 21B, 22H, 23B, 27G, 30C, 34H, 37C, 38B, 39A, 42E, 45B and 48A. Each of the HBM IC chips 251 in the standard commodity logic drive 300 may be a high speed, high bandwidth, wide bitwidth dynamic-random-access-memory (DRAM) IC chip, high speed, high bandwidth, wide bitwidth cache static-random-access-memory (SRAM) chip, high speed, high bandwidth, wide bitwidth magnetoresistive random-access-memory (MRAM) chip, high speed, high bandwidth, wide bitwidth resistive random-access-memory (RRAM) chip or high speed, high bandwidth, wide bitwidth phase change random access memory (PCM) chips. For the standard commodity logic drive 300, each of its standard commodity FPGA IC chip 200, graphic-processing unit (GPU) integrated-circuit (IC) chip 269a, central-processing-unit (CPU) integrated-circuit (IC) chip 269b, tensor-processing-unit (TPU) integrated-circuit (IC) chip 269c, network-processing-unit (NPU) integrated-circuit (IC) chip 269d and digital-signal-processing (DSP) integrated-circuit (IC) chip 270 in the single-die type may be arranged horizontally adjacent to one of its HBM IC chips 251 in the single-die type for communication therebetween in a high speed, high bandwidth and wide bitwidth. The standard commodity logic drive 300 may be further packaged with one or more non-volatile memory (NVM) IC chips 250, such as NAND flash integrated-circuit (IC) chips, NOR flash integrated-circuit (IC) chips, ferroelectric random-access-memory (FRAM) integrated-circuit (IC) chips, magnetoresistive random access memory (MRAM) integrated-circuit (IC) chips or resistive random access memory (RRAM) integrated-circuit (IC) chips, (only one is shown therein) configured to store the resulting values or programming codes in a non-volatile manner for programming or configuring the programmable logic cells 2014 and programmable switch cells 379 of its standard commodity FPGA IC chip 200 as seen in FIGS. 7 and 8 and for programming or configuring the cross-point switches 379 of its DPIIC chips 410 as seen in FIG. 10, and to store data in a non-volatile manner from its HBM IC chips 251. The standard commodity logic drive 300 may be further packaged with an innovated application-specific-IC (ASIC) or customer-owned-tooling (COT) (abbreviated as IAC below) integrated-circuit (IC) chip 402 including therein intellectual-property (IP) circuits, application-specific (AS) circuits, analog circuits, mixed-mode signal circuits, radio-frequency (RF) circuits, and/or transmitter, receiver or transceiver circuits, etc. The standard commodity logic drive 300 may be further packaged with a dedicated control and input/output (I/O) chip 260 to control data transmission between any two of its standard commodity FPGA IC chip 200, graphic-processing unit (GPU) integrated-circuit (IC) chip 269a, central-processing-unit (CPU) integrated-circuit (IC) chip 269b, tensor-processing-unit (TPU) integrated-circuit (IC) chip 269c, network-processing-unit (NPU) integrated-circuit (IC) chip 269d, digital-signal-processing (DSP) integrated-circuit (IC) chip 270, auxiliary and supporting (AS) integrated-circuit (IC) chip 411, HBM IC chips 251, IAC IC chip 402 and non-volatile memory (NVM) IC chip 250.

[0273] Referring to FIG. 12A, for the standard commodity logic drive, its standard commodity FPGA IC chip 200, graphic-processing unit (GPU) integrated-circuit (IC) chip 269a, central-processing-unit (CPU) integrated-circuit (IC) chip 269b, tensor-processing-unit (TPU) integrated-circuit (IC) chip 269c, network-processing-unit (NPU) integrated-circuit (IC) chip 269d, digital-signal-processing (DSP) integrated-circuit (IC) chip 270, auxiliary and supporting (AS) integrated-circuit (IC) chip 411, HBM IC chips 251, IAC IC chip 402, non-volatile memory (NVM) IC chip 250 and dedicated control and I/O chip 260 may be arranged in an array. The standard commodity logic drive 300 may include multiple inter-chip interconnects 371 each extending alone edges of its standard commodity FPGA IC chip 200, graphic-processing unit (GPU) integrated-circuit (IC) chip 269a, central-processing-unit (CPU) integrated-circuit (IC) chip 269b, tensor-processing-unit (TPU) integrated-circuit (IC) chip 269c, network-processing-unit (NPU) integrated-circuit (IC) chip 269d, digital-signal-processing (DSP) integrated-circuit (IC) chip 270, auxiliary and supporting (AS) integrated-circuit (IC) chip 411, HBM IC chips 251, IAC IC chip 402, non-volatile memory (NVM) IC chip 250 and dedicated control and I/O chip 260.

[0274] Referring to FIG. 12A, the standard commodity logic drive 300 may include a plurality of DPIIC chips 410 aligned with a cross of a vertical bundle of inter-chip interconnects 371 and a horizontal bundle of inter-chip interconnects 371. For the standard commodity logic drive 300, each of its DPIIC chips 410 may be arranged at corners of four of its standard commodity FPGA IC chip 200, graphic-processing unit (GPU) integrated-circuit (IC) chip 269a, central-processing-unit (CPU) integrated-circuit (IC) chip 269b, tensor-processing-unit (TPU) integrated-circuit (IC) chip 269c, network-processing-unit (NPU) integrated-circuit (IC) chip 269d, digital-signal-processing (DSP) integrated-circuit (IC) chip 270, auxiliary and supporting (AS) integrated-circuit (IC) chip 411, HBM IC chips 251, IAC IC chip 402, non-volatile memory (NVM) IC chip 250 and dedicated control and I/O chip 260 around said each of its DPIIC chips 410. The inter-chip interconnects 371 may be formed for the programmable interconnect 361. Data transmission may be built (1) between one of the programmable interconnects 361 of the inter-chip interconnects 371 and one of the programmable interconnects 361 of the standard commodity FPGA IC chip 200 via one of the small input/output (I/O) circuits 203 of the standard commodity FPGA IC chip 200, and (2) between one of the programmable interconnects 361 of the inter-chip interconnects 371 and one of the programmable interconnects 361 of one of the DPIIC chips 410 via one of the small input/output (I/O) circuits 203 of said one of the DPIIC chips 410.

[0275] Referring to FIG. 12A, for the standard commodity logic drive 300, one or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its standard commodity FPGA IC chip 200 in a single-die type or in the operation unit 190 to all of the DPIIC chips 410. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from the standard commodity FPGA IC chip 200 in a single-die type or in the operation unit 190 to its dedicated control and input/output (I/O) chip 260. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its standard commodity FPGA IC chip 200 in a single-die type or in the operation unit 190 to its NVM IC chip 250. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its standard commodity FPGA IC chip 200 in a single-die type or in the operation unit 190 to its GPU chip 269a in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its standard commodity FPGA IC chip 200 in a single-die type or in the operation unit 190 to its CPU chip 269b in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its standard commodity FPGA IC chip 200 in a single-die type or in the operation unit 190 to its DSP chip 270 in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its standard commodity FPGA IC chip 200 in a single-die type to one of its HBMIC chips 251 in a single-die type next to its standard commodity FPGA IC chip 200 and the communication therebetween may have a data bit width of equal to or greater than 64, 128, 256, 512, 1024, 2048, 4096, 8K, or 16K. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its standard commodity FPGA IC chip 200 in a single-die type or in the operation unit 190 to its IAC IC chip 402. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its standard commodity FPGA IC chip 200 in a single-die type or in the operation unit 190 to its TPU chip 269c in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its standard commodity FPGA IC chip 200 in a single-die type or in the operation unit 190 to its NPU chip 269d in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its standard commodity FPGA IC chip 200 in a single-die type to its standard commodity FPGA IC chip 200 in the operation unit 190.

[0276] Referring to FIG. 12A, for the standard commodity logic drive 300, one or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its DPIIC chips 410 to its dedicated control and input/output (I/O) chip 260. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its DPIIC chips 410 to its NVM IC chip 250. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its DPIIC chips 410 to its GPU chip 269a in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its DPIIC chips 410 to its CPU chip 269b in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its DPIIC chips 410 to its DSP chip 270 in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its DPIIC chips 410 to all of its HBM IC chips 251 each in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its DPIIC chips 410 to the others of the DPIIC chips 410. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its DPIIC chips 410 to its IAC IC chip 402. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its DPIIC chips 410 to its TPU chip 269c in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its DPIIC chips 410 to its NPU chip 269d in a single-die type or in the operation unit 190.

[0277] Referring to FIG. 12A, for the standard commodity logic drive 300, one or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its CPU chip 269b in a single-die type or in the operation unit 190 to its GPU chip 269a in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its TPU chip 269c in a single-die type or in the operation unit 190 to its GPU chip 269a in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its NPU chip 269d in a single-die type or in the operation unit 190 to its GPU chip 269a in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its DSP chip 270 in a single-die type or in the operation unit 190 to its GPU chip 269a in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its CPU chip 269b in a single-die type or in its operation unit 190 to its NVM IC chip 250. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its TPU chip 269c in a single-die type or in its operation unit 190 to its NVM IC chip 250. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its NPU chip 269d in a single-die type or in its operation unit 190 to its NVM IC chip 250. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its DSP chip 270 in a single-die type or in its operation unit 190 to its NVM IC chip 250. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its CPU chip 269b in a single-die type to one of its HBM IC chips 251 in a single-die type next to its CPU chip 269b and the communication therebetween may have a data bit width of equal to or greater than 64, 128, 256, 512, 1024, 2048, 4096, 8K, or 16K. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its TPU chip 269c in a single-die type to one of its HBM IC chips 251 in a single-die type next to its TPU chip 269c and the communication therebetween may have a data bit width of equal to or greater than 64, 128, 256, 512, 1024, 2048, 4096, 8K, or 16K. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its NPU chip 269d in a single-die type to one of its HBM IC chips 251 in a single-die type next to its NPU chip 269d and the communication therebetween may have a data bit width of equal to or greater than 64, 128, 256, 512, 1024, 2048, 4096, 8K, or 16K. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its DSP chip 270 in a single-die type to one of its HBM IC chips 251 in a single-die type next to its DSP chip 270 and the communication therebetween may have a data bit width of equal to or greater than 64, 128, 256, 512, 1024, 2048, 4096, 8K, or 16K. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its CPU chip 269b in a single-die type or in its operation unit 190 to the IAC IC chip 402. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its TPU chip 269c in a single-die type or in its operation unit 190 to the IAC IC chip 402. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its NPU chip 269d in a single-die type or in its operation unit 190 to the IAC IC chip 402. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its DSP chip 270 in a single-die type or in its operation unit 190 to its IAC IC chip 402. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its CPU chip 269b in a single-die type or in its operation unit 190 to its DSP chip 270 in a single-die type or in its operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its CPU chip 269b in a single-die type or in its operation unit 190 to its TPU chip 269c in a single-die type or in its operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its CPU chip 269b in a single-die type or in its operation unit 190 to its NPU chip 269d in a single-die type or in its operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its TPU chip 269c in a single-die type or in its operation unit 190 to its NPU chip 269d in a single-die type or in its operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its GPU chip 269a in a single-die type to one of its HBM IC chips 251 in a single-die type next to its GPU chip 269a and the communication therebetween may have a data bit width of equal to or greater than 64, 128, 256, 512, 1024, 2048, 4096, 8K, or 16K. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its GPU chip 269a in a single-die type or in its operation unit 190 to its NVM IC chip 250. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its GPU chip 269a in a single-die type to its GPU chip 269a in its operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its GPU chip 269a in a single-die type or in its operation unit 190 to its IAC IC chip 402. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its NVM IC chip 250 to its dedicated control and input/output (I/O) chip 260. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its HBM IC chips 251 in a single-die type or in its operation unit 190 to its dedicated control and input/output (I/O) chip 260. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its GPU chip 269a in a single-die type or in its operation unit 190 to its dedicated control and input/output (I/O) chip 260. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its CPU chip 269b in a single-die type or in its operation unit 190 to its dedicated control and input/output (I/O) chip 260. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its TPU chip 269c in a single-die type or in its operation unit 190 to its dedicated control and input/output (I/O) chip 260. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its NPU chip 269d in a single-die type or in its operation unit 190 to its dedicated control and input/output (I/O) chip 260. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its DSP chip 270 in a single-die type or in its operation unit 190 to its dedicated control and input/output (I/O) chip 260. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its NVM IC chip 250 to each of its HBM IC chips 251 in a single-die type or in its operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its NVM IC chip 250 to its IAC IC chip 402. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its HBM IC chips 251 in a single-die type or in its operation unit 190 to its IAC IC chip 402. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its IAC IC chip 402 to its dedicated control and input/output (I/O) chip 260. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its HBM IC chips 251 in a single-die type or in its operation unit 190 to one of the others of the HBM IC chips 251 in a single-die type or in its operation unit 190.

[0278] Referring to FIG. 12A, the standard commodity logic drive 300 may include multiple dedicated input/output (I/O) chips 265 in a peripheral region thereof surrounding a central region thereof, in which its standard commodity FPGA IC chip 200, graphic-processing unit (GPU) integrated-circuit (IC) chip 269a, central-processing-unit (CPU) integrated-circuit (IC) chip 269b, tensor-processing-unit (TPU) integrated-circuit (IC) chip 269c, network-processing-unit (NPU) integrated-circuit (IC) chip 269d, digital-signal-processing (DSP) integrated-circuit (IC) chip 270, HBM IC chips 251, IAC IC chip 402, non-volatile memory (NVM) IC chip 250, dedicated control and I/O chip 260 and DPIIC chips 410 are located. For the standard commodity logic drive 300, one or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its standard commodity FPGA IC chip 200 in a single-die type or in its operation unit 190 to all of its dedicated input/output (I/O) chips 265. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its DPIIC chips 410 to all of its dedicated input/output (I/O) chips 265. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its NVM IC chip 250 to all of its dedicated input/output (I/O) chips 265. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its dedicated control and input/output (I/O) chip 260 to all of its dedicated input/output (I/O) chips 265. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its GPU chip 269a in a single-die type or in its operation unit 190 to all of its dedicated input/output (I/O) chips 265. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its CPU chip 269b in a single-die type or in its operation unit 190 to all of its dedicated input/output (I/O) chips 265. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its TPU chip 269c in a single-die type or in its operation unit 190 to all of its dedicated input/output (I/O) chips 265. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its NPU chip 269d in a single-die type or in its operation unit 190 to all of its dedicated input/output (I/O) chips 265. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its DSP chip 270 in a single-die type or in its operation unit 190 to all of its dedicated input/output (I/O) chips 265. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its HBM IC chips 251 in a single-die type or in its operation unit 190 to all of its dedicated input/output (I/O) chips 265. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its IAC IC chip 402 to all of its dedicated input/output (I/O) chips 265. For the standard commodity logic drive 300, its dedicated control and input/output (I/O) chip 260 is configured to control data transmission between each of its dedicated input/output (I/O) chips 265 and one of its standard commodity FPGA IC chip 200, graphic-processing unit (GPU) integrated-circuit (IC) chip 269a, central-processing-unit (CPU) integrated-circuit (IC) chip 269b, tensor-processing-unit (TPU) integrated-circuit (IC) chip 269c, network-processing-unit (NPU) integrated-circuit (IC) chip 269d, digital-signal-processing (DSP) integrated-circuit (IC) chip 270, HBM IC chips 251, IAC IC chip 402, non-volatile memory (NVM) IC chip 250, dedicated control and I/O chip 260 and DPIIC chips 410.

[0279] Referring to FIG. 12A, for the standard commodity logic drive 300 being in operation, each of its DPIIC chips 410 may be arranged with the SRAM cells acting as cache memory to store data from any of its standard commodity FPGA IC chip 200, graphic-processing unit (GPU) integrated-circuit (IC) chip 269a, central-processing-unit (CPU) integrated-circuit (IC) chip 269b, tensor-processing-unit (TPU) integrated-circuit (IC) chip 269c, network-processing-unit (NPU) integrated-circuit (IC) chip 269d, digital-signal-processing (DSP) integrated-circuit (IC) chip 270, auxiliary and supporting (AS) integrated-circuit (IC) chip 411, HBM IC chips 251, IAC IC chip 402, non-volatile memory (NVM) IC chip 250, dedicated control and I/O chip 260 and DPIIC chips 410.

[0280] Referring to FIG. 12A, for the standard commodity logic drive 300, its non-volatile memory (NVM) IC chip 250 may include multiple large input/output (I/O) circuits each having an output capacitance or driving capability or loading, for example, between 2 pF and 100 pF, between 2 pF and 50 pF, between 2 pF and 30 pF, between 2 pF and 20 pF, between 2 pF and 15 pF, between 2 pF and 10 pF, or between 2 pF and 5 pF, or greater than 2 pF, 5 pF, 10 pF, 15 pF or 20 pF, and an input capacitance between 0.15 pF and 4 pF or between 0.15 pF and 2 pF, or greater than 0.15 pF for example; alternatively, each of the large input/output (I/O) circuits of its non-volatile memory (NVM) IC chip 250 may have an I/O power efficiency greater than 3, 5 or 10 pico-Joules per bit, per switch or per voltage swing. Alternatively, its non-volatile memory (NVM) IC chip 250 may include a cryptography block or circuit configured to decrypt, in accordance with a password or key stored or saved in a non-volatile memory cell of the cryptography block or circuit of its non-volatile memory (NVM) IC chip 250, which may be composed of one or more magnetoresistive random access memory (MRAM) cells, one or more resistive random access memory (RRAM) cells, one or more anti-fuses, one or more e-fuses, or a floating gate of a metal-oxide-semiconductor (MOS) transistor, encrypted data from multiple non-volatile memory cells of its non-volatile memory (NVM) IC chip 250 as decrypted data and to encrypt, in accordance with the password or key, data as encrypted data to be stored in multiple non-volatile memory cells of its non-volatile memory (NVM) IC chip 250.

[0281] Referring to FIG. 12A, for a first aspect of the standard commodity logic drive 300, a first one of the large I/O circuits of its NVM IC chip 250 may have a large driver coupling to a large receiver of a second one of the large I/O circuits of one of the AS IC chip 411 via one of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing first encrypted CPM data from the large driver of the first one of the large I/O circuits to the large receiver of the second one of the large I/O circuits. Next, the first encrypted CPM data may be decrypted as illustrated in FIG. 11, in accordance with a password or key, by the cryptography block or circuit 517 of its AS IC chip 411 as first decrypted CPM data. Next, a first one of the small I/O circuits of its AS IC chip 411 may have a small driver coupling to a small receiver of a second one of the small I/O circuits of its standard commodity FPGA IC chip 200 via another of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing the first decrypted CPM data from the small driver of the first one of the small I/O circuits to the small receiver 375 of the second one of the small I/O circuits. Next, one of the first type of memory cells 490 of one of the programmable logic cells (LC) 2014 of its standard commodity FPGA IC chip 200 as seen in FIG. 7 may be programmed or configured in accordance with the first decrypted CPM data, or one of the first type of memory cells 362 of one of the programmable switch cells 379 of its standard commodity FPGA IC chip 200 as seen in FIG. 8 may be programmed or configured in accordance with the first decrypted CPM data. Alternatively, a third one of the small I/O circuits of its standard commodity FPGA IC chip 200 may have a small driver coupling to a small receiver of a fourth one of the small I/O circuits of its AS IC chip 411 via another of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing second CPM data used to program or configure the first type of memory cells 490 of one of the programmable logic cells (LC) 2014 of its standard commodity FPGA IC chip 200 or the first type of memory cells 362 of one of the programmable switch cells 379 of its standard commodity FPGA IC chip 200 from the small driver of the third one of the small I/O circuits to the small receiver of the fourth one of the small I/O circuits. Next, the second CPM data may be encrypted as illustrated in FIG. 11, in accordance with the password or key, by the cryptography block or circuit 517 of its AS IC chip 411 as second encrypted CPM data. Next, a third one of the large I/O circuits of its AS IC chip 411 may have a large driver coupling to a large receiver of a fourth one of the large I/O circuits of its NVM IC chip 250 via another of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing the second encrypted CPM data from the large driver of the third one of the large I/O circuits to the large receiver of the fourth one of the large I/O circuits to be stored in its NVM IC chip 250.

[0282] Referring to FIG. 12A, for a second aspect of the standard commodity logic drive 300, a first one of the large I/O circuits of its NVM IC chip 250 may have a large driver coupling to a large receiver of a second one of the large I/O circuits of its AS IC chip 411 via one of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing first encrypted CPM data from the large driver 274 of the first one of the large I/O circuits to the large receiver 275 of the second one of the large I/O circuits 341. Next, a first one of the small I/O circuits of its AS IC chip 411 may have a small driver coupling to a small receiver of a second one of the small I/O circuits of its standard commodity FPGA IC chip 200 via another of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing the first encrypted CPM data from the small driver 374 of the first one of the small I/O circuits to the small receiver of the second one of the small I/O circuits. Next, its standard commodity FPGA IC chip 200 may include the cryptography block or circuit as illustrated in FIG. 9 configured to decrypt, in accordance with a password or key, the first encrypted CPM data as first decrypted CPM data. Next, one of the first type of memory cells 490 of one of the programmable logic cells (LC) 2014 of its standard commodity FPGA IC chip 200 as seen in FIG. 7 may be programmed or configured in accordance with the first decrypted CPM data, or one of the first type of memory cells 362 of one of the programmable switch cells 379 of its standard commodity FPGA IC chip 200 as seen in FIG. 8 may be programmed or configured in accordance with the first decrypted CPM data. Alternatively, second CPM data used to program or configure the first type of memory cells 490 of one of the programmable logic cells (LC) 2014 of its standard commodity FPGA IC chip 200 or the first type of memory cells 362 of one of the programmable switch cells 379 of its standard commodity FPGA IC chip 200 may be encrypted, in accordance with the password or key, by the cryptography block or circuit of its standard commodity FPGA IC chip 200 as second encrypted CPM data. Next, a third one of the small I/O circuits 203 of its standard commodity FPGA IC chips 200 may have a small driver coupling to a small receiver of a fourth one of the small I/O circuits of its AS IC chip 411 via another of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing the second encrypted CPM data from the small driver 374 of the third one of the small I/O circuits 203 to the small receiver 375 of the fourth one of the small I/O circuits 203. Next, a third one of large I/O circuits of its AS IC chip 411 may have a large driver coupling to a large receiver of a fourth one of the large I/O circuits of its NVM IC chip 250 via another of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing the second encrypted CPM data from the large driver of the third one of the large I/O circuits to the large receiver 275 of the fourth one of the large I/O circuits to be stored in its NVM IC chip 250.

[0283] Referring to FIG. 12A, for a third aspect of the standard commodity logic drive 300, a first one of the large I/O circuits of its NVM IC chip 250 may have a large driver coupling to a large receiver of a second one of the large I/O circuits of its standard commodity FPGA IC chip 200 via one of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing first encrypted CPM data from the large driver of the first one of the large I/O circuits to the large receiver of the second one of the large I/O circuits. Next, its standard commodity FPGA IC chip 200 may include the cryptography block or circuit as illustrated in FIG. 9 configured to decrypt, in accordance with a password or key, the first encrypted CPM data as first decrypted CPM data. Next, one of the first type of memory cells 490 of one of the programmable logic cells (LC) 2014 of its standard commodity FPGA IC chip 200 as seen in FIG. 7 may be programmed or configured in accordance with the first decrypted CPM data, or one of the first type of memory cells 362 of one of the programmable switch cells 379 of its standard commodity FPGA IC chip 200 as seen in FIG. 8 may be programmed or configured in accordance with the first decrypted CPM data. Alternatively, second CPM data used to program or configure the first type of memory cells 490 of one of the programmable logic cells (LC) 2014 of its standard commodity FPGA IC chip 200 or the first type of memory cells 362 of one of the programmable switch cells 379 of its standard commodity FPGA IC chip 200 may be encrypted, in accordance with the password or key, by the cryptography block or circuit of its standard commodity FPGA IC chip 200 as second encrypted CPM data. Next, a third one of the large I/O circuits of its standard commodity FPGA IC chip 200 may have a large driver coupling to a large receiver of a fourth one of the large I/O circuits of its NVM IC chip 250 via another of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing the second encrypted CPM data from the large driver of the third one of the small I/O circuits 203 to the large receiver of the fourth one of the small I/O circuits 203 to be stored in its NVM IC chip 250.

[0284] Referring to FIG. 12A, for a fourth aspect of the standard commodity logic drive 300, its NVM IC chip 250 may include the cryptography block or circuit configured to decrypt, in accordance with a password or key, first encrypted CPM data stored therein as first decrypted CPM data. A first one of the large I/O circuits of its NVM IC chip 250 may have a large driver coupling to a large receiver of a second one of the large I/O circuits of its AS IC chip 411 via one of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing the first decrypted CPM data from the large driver of the first one of the large I/O circuits to the large receiver of the second one of the large I/O circuits. Next, a first one of the small I/O circuits of its AS IC chip 411 may have a small driver coupling to a small receiver of a second one of the small I/O circuits of its standard commodity FPGA IC chip 200 via another of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing the first decrypted CPM data from the small driver of the first one of the small I/O circuits to the small receiver of the second one of the small I/O circuits. Next, one of the first type of memory cells 490 of one of the programmable logic cells (LC) 2014 of its standard commodity FPGA IC chip 200 as seen in FIG. 7 may be programmed or configured in accordance with the first decrypted CPM data, or one of the first type of memory cells 362 of one of the programmable switch cells 379 of its standard commodity FPGA IC chip 200 as seen in FIG. 8 may be programmed or configured in accordance with the first decrypted CPM data. Alternatively, a third one of the small I/O circuits 203 of its standard commodity FPGA IC chip 200 may have a small driver coupling to a small receiver of a fourth one of the small I/O circuits of its AS IC chip 411 via another of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing second CPM data used to program or configure the first type of memory cells 490 of one of the programmable logic cells (LC) 2014 of its standard commodity FPGA IC chip 200 or the first type of memory cells 362 of one of the programmable switch cells 379 of its standard commodity FPGA IC chip 200 from the small driver of the third one of the small I/O circuits to the small receiver of the fourth one of the small I/O circuits. Next, a third one of the large I/O circuits of its AS IC chip 411 may have a large driver coupling to a large receiver of a fourth one of the large I/O circuits of its NVM IC chip 250 via another of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing the second CPM data from the large driver of the third one of the large I/O circuits to the large receiver of the fourth one of the large I/O circuits. The second CPM data may be encrypted, in accordance with the password or key, by the cryptography block or circuit of its NVM IC chip 250 as second encrypted CPM data to be stored in its NVM IC chip 250.

[0285] Referring to FIG. 12A, for a fifth aspect of the standard commodity logic drive 300, its NVM IC chip 250 may include the cryptography block or circuit configured to decrypt, in accordance with a password or key, first encrypted CPM data stored therein as first decrypted CPM data. A first one of the large I/O circuits of its NVM IC chip 250 may have a large driver coupling to a large receiver of a second one of the large I/O circuits of its standard commodity FPGA IC chip 200 via one of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing the first decrypted CPM data from the large driver of the first one of the large I/O circuits to the large receiver of the second one of the large I/O circuits. Next, one of the first type of memory cells 490 of one of the programmable logic cells (LC) 2014 of its standard commodity FPGA IC chip 200 as seen in FIG. 7 may be programmed or configured in accordance with the first decrypted CPM data, or one of the first type of memory cells 362 of one of the programmable switch cells 379 of its standard commodity FPGA IC chip 200 as seen in FIG. 8 may be programmed or configured in accordance with the first decrypted CPM data. Alternatively, a third one of the large I/O circuits of its standard commodity FPGA IC chips 200 may have a large driver coupling to a large receiver of a fourth one of the large I/O circuits of its NVM IC chip 250 via another of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing second CPM data used to program or configure the first type of memory cells 490 of one of the programmable logic cells (LC) 2014 of its standard commodity FPGA IC chip 200 or the first type of memory cells 362 of one of the programmable switch cells 379 of its standard commodity FPGA IC chips 200 from the large driver of the third one of the large I/O circuits to the large receiver of the fourth one of the large I/O circuits. The second CPM data may be encrypted, in accordance with the password or key, by the cryptography block or circuit of its NVM IC chip 250 as second encrypted CPM data to be stored in its NVM IC chip 250.

[0286] FIG. 12B is a block diagram showing interconnection in a standard commodity logic drive in accordance with an embodiment of the present application. Referring to FIG. 12B, for the standard commodity logic drive 300 as illustrated in FIG. 12A, each of its dedicated I/O chips 265 and control and I/O chip 260 may include a first group of small I/O circuits 203 each coupling to one of a first group of small I/O circuits 203 of its FPGA IC chip 200 through one of its inter-chip interconnect 371, i.e., programmable or non-programmable interconnect 361 or 364, and a second group of small I/O circuits 203 each coupling to one of a first group of small I/O circuits 203 of its NVM IC chip 250 through one of its inter-chip interconnect 371, i.e., programmable or non-programmable interconnect 361 or 364. Its FPGA IC chip 200 may include a second group of small I/O circuits 203 each coupling to one of a second group of small I/O circuits 203 of its NVM IC chip 250 through one of its inter-chip interconnect 371, i.e., programmable or non-programmable interconnect 361 or 364. Each of its dedicated I/O chips 265 and control and I/O chip 260 may include (1) a first group of large I/O circuits 341 each coupling to one of its metal bumps, pillars or pads 570 or metal pads 583 as seen in FIGS. 22H, 23B, 27G, 30C, 34H, 37C, 38B, 39A, 42E, 45B and 48A for one or more serial-advanced-technology-attachment (SATA) ports 521 and one of the large I/O circuits 341 of its NVM IC chip 250 through one of its programmable or non-programmable interconnects 361 or 364, (2) a second group of large I/O circuits 341 each coupling to one of its metal bumps, pillars or pads 570 or metal pads 583 for one or more universal serial bus (USB) ports 522 through one of its programmable or non-programmable interconnects 361 or 364, (3) a third group of large I/O circuits 341 each coupling to one of its metal bumps, pillars or pads 570 or metal pads 583 for one or more serializer/deserializer (SerDes) ports 523 through one of its programmable or non-programmable interconnects 361 or 364, (4) a fourth group of large I/O circuits 341 each coupling to one of its metal bumps, pillars or pads 570 or metal pads 583 for one or more wide input/output (I/O) ports 523 through one of its programmable or non-programmable interconnects 361 or 364, (5) a fifth group of large I/O circuits 341 each coupling to one of its metal bumps, pillars or pads 570 or metal pads 583 for one or more peripheral-components-interconnect express (PCIe) ports 525 through one of its programmable or non-programmable interconnects 361 or 364, (6) a sixth group of large I/O circuits 341 each coupling to one of its metal bumps, pillars or pads 570 or metal pads 583 for one or more wireless ports 526 through one of its programmable or non-programmable interconnects 361 or 364, (7) a seventh group of large I/O circuits 341 each coupling to one of its metal bumps, pillars or pads 570 or metal pads 583 for one or more IEEE 1394 ports 527 through one of its programmable or non-programmable interconnects 361 or 364 and (8) an eighth group of large I/O circuits 341 each coupling to one of its metal bumps, pillars or pads 570 or metal pads 583 for one or more thunderbolt ports 528 through one of its programmable or non-programmable interconnects 361 or 364.

[0287] FIGS. 13A and 13B are schematically cross-sectional views showing various fine-line interconnection bridges in accordance with an embodiment of the present application. Referring to FIGS. 13A and 13B, a first or second type of fine-line interconnection bridge (FIB) 690 is provided for horizontal connection to transmit signals in a horizontal direction.

[0288] Referring to FIGS. 13A, a first type of fine-line interconnection bridge (FIB) 690 may include (1) a semiconductor substrate 2, (2) a first interconnection scheme 560 on the semiconductor substrate 2, wherein its first interconnection scheme 560 may include multiple insulating dielectric layers 12 and multiple interconnection metal layers 6 each in neighboring two of the insulating dielectric layers 12, wherein each of the interconnection metal layers 6 of its first interconnection scheme 560 is patterned with multiple metal pads, lines or traces 8 in an upper one of the neighboring two of the insulating dielectric layers 12 of its first interconnection scheme 560 and multiple metal vias 10 in a lower one of the neighboring two of the insulating dielectric layers 12 of its first interconnection scheme 560, wherein between each neighboring two of the interconnection metal layers 6 of its first interconnection scheme 560 is provided one of the insulating dielectric layers 12 of its first interconnection scheme 560, wherein an upper one of the interconnection metal layers 6 of its first interconnection scheme 560 may couple to a lower one of the interconnection metal layers 6 of its first interconnection scheme 560 through an opening in one of the insulating dielectric layers 12 of its first interconnection scheme 560 between the upper and lower ones of the interconnection metal layers 6 of its first interconnection scheme 560, (3) a passivation layer 14 as illustrated in FIG. 1A, 1C or 1E on its first interconnection scheme 560, wherein the topmost one of the interconnection metal layers 6 of its first interconnection scheme 560 may have the metal pads 8 at bottoms of multiple openings 14a in the passivation layer 14, and (4) multiple micro-bumps or micro-pads 34, which may be of one of the first through fourth types having the same specifications as the first through fourth types of micro-bumps or micro-pads 34 respectively as illustrated in FIG. 1A, 1C or 1E, on the metal pads 8 of the topmost one of the interconnection metal layers 6 of its first interconnection scheme 560 at the bottoms of the openings 14a in its passivation layer 14.

[0289] Referring to FIG. 13A, for the first interconnection scheme 560, one of the metal pads, lines or traces 8 of each of its interconnection metal layers 6 may have a thickness between 3 nm and 500 nm and may have a width between 3 nm and 500 nm. A space or pitch between neighboring two of the metal pads, lines or traces 8 of each of its interconnection metal layers 6 may be between 3 nm and 500 nm. Each of its insulating dielectric layers 12 may include a layer of silicon oxide, silicon oxynitride or silicon oxycarbide having a thickness between 3 nm and 500 nm. Each of its interconnection metal layers 6 may include (1) a copper layer 24 having lower portions in openings in a lower one of the insulating dielectric layers 12, such as SiOC layer having a thickness of between 3 nm and 500 nm, and upper portions having a thickness of between 3 nm and 500 nm over the lower one of the insulating dielectric layers 12 and in openings in an upper one of the insulating dielectric layers 12, (2) an adhesion layer 18, such as titanium or titanium nitride having a thickness of between 1 nm and 50 nm, at a bottom and sidewall of each of the lower portions of the copper layer 24 and at a bottom and sidewall of each of the upper portions of the copper layer 24, and (3) a seed layer 22, such as copper, between the copper layer 24 and the adhesion layer 18, wherein the copper layer 24 has a top surface substantially coplanar with a top surface of the upper one of the insulating dielectric layers 12. For an example, the first interconnection scheme 560 may be formed with one or more passive devices, such as resistors, capacitors or inductors.

[0290] Referring to FIGS. 13B, a second type of fine-line interconnection bridge (FIB) 690 may have a structure similar to that as illustrated in FIG. 13A. For an element indicated by the same reference number shown in FIGS. 13A and 13B, the specification of the element as seen in FIG. 13B may be referred to that of the element as illustrated in FIG. 13A. The difference between the first and second types of fine-line interconnection bridges (FIB) 690 is that the second type of fine-line interconnection bridge (FIB) 690 may further include a second interconnection scheme 588 over the passivation layer 14, wherein the second interconnection scheme 588 may include one or more interconnection metal layers 27 coupling to the metal pads 8 of the topmost one of the interconnection metal layers 6 of its first interconnection scheme 560 through the openings 14a in its passivation layer 14, and one or more polymer layers 42, i.e., insulating dielectric layers, each between neighboring two of the interconnection metal layers 27 of its second interconnection scheme 588, under a bottommost one of the interconnection metal layers 27 of its second interconnection scheme 588 or over a topmost one of the interconnection metal layers 27 of its second interconnection scheme 588, wherein an upper one of the interconnection metal layers 27 of its second interconnection scheme 588 may couple to a lower one of the interconnection metal layers 27 of its second interconnection scheme 588 through an opening in one of the polymer layers 42 of its second interconnection scheme 588 between the upper and lower ones of the interconnection metal layers 27 of its second interconnection scheme 588, wherein the topmost one of the interconnection metal layers 27 of its second interconnection scheme 588 may have multiple metal pads at bottoms of multiple openings 42a in the topmost one of the polymer layers 42 of its second interconnection scheme 588, and multiple micro-bumps or micro-pads 34 as illustrated in FIG. 1A, 1C or 1E may be formed on the metal pads of the topmost one of the interconnection metal layers 27 of its second interconnection scheme 588 at the bottoms of the openings 42a in the topmost one of the polymer layers 42 of its second interconnection scheme 588.

[0291] Referring to FIG. 13B, for the second interconnection scheme 588, each of its interconnection metal layers 27 may include (1) a copper layer 40 having lower portions in openings in one of the polymer layers 42 having a thickness of between 0.3 μm and 20 μm, and upper portions having a thickness 0.3 μm and 20 μm over said one of the polymer layers 42, (2) an adhesion layer 28a, such as titanium or titanium nitride having a thickness of between 1 nm and 50 nm, at a bottom and sidewall of each of the lower portions of the copper layer 40 and at a bottom of each of the upper portions of the copper layer 40, and (3) a seed layer 28b, such as copper, between the copper layer 40 and the adhesion layer 28a, wherein said each of the upper portions of the copper layer 40 may have a sidewall not covered by the adhesion layer 28a. For an example, each of the first and second interconnection schemes 560 and 588 may be formed with one or more passive devices, such as resistors, capacitors or inductors.

[0292] FIGS. 14A-14F are schematically cross-sectional views showing various semiconductor integrated-circuit (IC) chips in accordance with an embodiment of the present application. Referring to FIGS. 14A-14F, either type of semiconductor integrated-circuit (IC) chip 100 may be provided for the standard commodity FPGA IC chip 200, DPIIC chip 410, dedicated I/O chip 265, dedicated control and I/O chip 260, NVM IC chip 250, IAC IC chip 402, HBM IC chips 251, GPU chip 269a, CPU chip 269b, TPU chip 269c, NPU chip 269d, digital-signal-processing (DSP) integrated-circuit (IC) chip 270 and auxiliary and supporting (AS) integrated-circuit (IC) chip 411 as seen in FIG. 12A.

[0293] Referring to FIG. 14A, a first type of semiconductor integrated-circuit (IC) chip 100 may have the structure as illustrated in FIG. 13A or 13B. For an element indicated by the same reference number shown in FIGS. 13A, 13B and 14A, the specification of the element as seen in FIG. 14A may be referred to that of the element as illustrated in FIG. 13A or 13B. The difference between the first type of semiconductor integrated-circuit (IC) chip 100 and the second type of fine-line interconnection bridge (FIB) 690 is that the first type of semiconductor integrated-circuit (IC) chip 100 as seen in FIG. 14A may further include multiple semiconductor devices 4 at an active surface of its semiconductor substrate 2 and under its first interconnection scheme 560, wherein each of its semiconductor devices 4 may couple to the interconnection metal layers 6 of its first interconnection scheme 560. For the first type of semiconductor integrated-circuit (IC) chip 100, its semiconductor devices 4 may include a memory cell, logic circuit, passive device, such as resistor, capacitor, inductor or filter, or active device, such as P-type or N-type metal-oxide-semiconductor (MOS) transistor. Multiple of the semiconductor devices 4 may compose the selection circuits 211 of the programmable logic cells (LC) 2014, memory cells 490 of the programmable logic cells (LC) 2014, memory cells 362 for the cross-point switches 379, small I/O circuits 203, large I/O circuits and/or cryptography block or circuit as illustrated in FIGS. 7, 8 and 9, for the standard commodity FPGA IC chip 200 of the standard commodity logic drive 300 as seen in FIG. 12A. The semiconductor devices 4 may compose the memory cells 362 for the programmable switch cells 379 and small I/O circuits 203, as illustrated in FIGS. 8 and 10, for each of the DPIIC chips 410 of the standard commodity logic drive 300 as seen in FIG. 12A. Multiple of the semiconductor devices 4 may compose the large I/O circuits of large-input/output (I/O) block 412, small I/O circuits of the small-input/output (I/O) block 413, cryptography block or circuit 517, regulating block 415 and innovated application-specific-integrated-circuit (ASIC) or customer-owned tooling (COT) block 418, as illustrated in FIG. 11, for the auxiliary and supporting (AS) integrated-circuit (IC) chip 411 of the standard commodity logic drive 300 as seen in FIG. 12A.

[0294] Referring to FIG. 14B, a second type of semiconductor integrated-circuit (IC) chip 100 may have similar structure as illustrated in FIG. 14A. For an element indicated by the same reference number shown in FIG. 1A-IF, 13A, 13B, 14A or 14B, the specification of the element as seen in FIG. 14B may be referred to that of the element as illustrated in FIG. 1A-1F, 13A, 13B or 14A. The difference between the first and second types of semiconductor integrated-circuit (IC) chips 100 is that the second type of semiconductor integrated-circuit (IC) chip 100 may further include multiple through silicon vias (TSVs) 157 as illustrated in FIGS. 1A-IF in its semiconductor substrate 2, wherein each of its through silicon vias (TSVs) 157 may couple to one or more of its semiconductor devices 4 through one or more of the interconnection metal layers 6 of its first interconnection scheme 560.

[0295] Referring to FIG. 14C, a third type of semiconductor integrated-circuit (IC) chip 100 may have similar structure as illustrated in FIG. 14B. For an element indicated by the same reference number shown in FIG. 1A-IF, 13A, 13B, 14A, 14B or 14C, the specification of the element as seen in FIG. 14C may be referred to that of the element as illustrated in FIG. 1A-IF, 13A, 13B, 14A or 14B. The difference between the second and third types of semiconductor integrated-circuit (IC) chips 100 is that each of the through silicon vias (TSVs) 157 of the third type of semiconductor integrated-circuit (IC) chip 100 may have the copper layer 156 having a backside surface coplanar with a backside 2b of the semiconductor substrate 2 of the third type of semiconductor integrated-circuit (IC) chip 100 and have the insulating lining 153 surrounding the adhesion layer 154, seed layer 155 and copper layer 156 of said each of the through silicon vias (TSVs) 157. The third type of semiconductor integrated-circuit (IC) chip 100 may further include a passivation layer 15 on the backside 2b of its semiconductor substrate 2, wherein each opening 15a in its passivation layer 15 may be aligned with the backside of the copper layer 156 of one of its through silicon vias (TSVs) 157. The passivation layer 15 may have the same specifications as those of the passivation layer 14 as illustrated in FIG. 1A, 1C or 1E. The third type of semiconductor integrated-circuit (IC) chip 100 may further include multiple micro-bumps or micro-pads 570 each on the backside of copper layer 156 of one of its through silicon vias (TSVs) 157. The micro-bumps or micro-pads 570 may be of one of the first through fourth types having the same specifications as the first through fourth types of micro-bumps or micro-pads 34 as illustrated in FIG. 1A, 1C or 1E, respectively.

[0296] Referring to FIGS. 14D, a fourth type of semiconductor integrated-circuit (IC) chip 100 may have similar structure as illustrated in FIG. 14A. For an element indicated by the same reference number shown in FIG. 13A, 14A or 14D, the specification of the element as seen in FIG. 14D may be referred to that of the element as illustrated in FIG. 13A or 14A. The difference between the first and fourth types of semiconductor integrated-circuit (IC) chips 100 is that the fourth type of semiconductor integrated-circuit (IC) chip 100 may be provided with (1) an insulating bonding layer 52 at its active side and on the topmost one of the insulating dielectric layers 12 of its first interconnection scheme 560 and (2) multiple metal pads 6a at its active side and in multiple openings 52a in its insulating bonding layer 52 and on the topmost one of the interconnection metal layers 6 of its first interconnection scheme 560, instead of the passivation layer 14 and micro-bumps or micro-pads 34 as seen in FIG. 14A. For the fourth type of semiconductor integrated-circuit (IC) chip 100, its insulating bonding layer 52 may include a silicon-oxide layer having a thickness between 0.1 and 2 μm. Each of its metal pads 6a may include (1) a copper layer 24 having a thickness of between 3 nm and 500 nm in one of the openings 52a in its insulating bonding layer 52, (2) an adhesion layer 18, such as titanium or titanium nitride having a thickness of between 1 nm and 50 nm, at a bottom and sidewall of the copper layer 24 of said each of its metal pads 6a, and (3) a seed layer 22, such as copper, between the copper layer 24 and adhesion layer 18 of said each of its metal pads 6a, wherein the copper layer 24 of said each of its metal pads 6a may have a top surface substantially coplanar with a top surface of the silicon-oxide layer of its insulating bonding layer 52.

[0297] Referring to FIGS. 14E, a fifth type of semiconductor integrated-circuit (IC) chip 100 may have similar structure as illustrated in FIG. 14D. For an element indicated by the same reference number shown in FIG. 1A-IF, 13A, 14A, 14B, 14D or 14E, the specification of the element as seen in FIG. 14E may be referred to that of the element as illustrated in FIG. 1A-IF, 13A, 14A, 14B or 14D. The difference between the fourth and fifth types of semiconductor integrated-circuit (IC) chips 100 is that the fifth type of semiconductor integrated-circuit (IC) chip 100 may further include multiple through silicon vias (TSVs) 157 as illustrated in FIG. 1A-1F in its semiconductor substrate 2, wherein each of its through silicon vias (TSVs) 157 may couple to one or more of its semiconductor devices 4 through one or more the interconnection metal layers 6 of its first interconnection scheme 560.

[0298] Referring to FIG. 14F, a sixth type of semiconductor integrated-circuit (IC) chip 100 may have similar structure as illustrated in FIG. 14E. For an element indicated by the same reference number shown in FIG. 1A-IF, 13A, or 14A-14F, the specification of the element as seen in FIG. 14F may be referred to that of the element as illustrated in FIG. 1A-1F, 13A, or 14A-14E. The difference between the fifth and sixth types of semiconductor integrated-circuit (IC) chips 100 is that the sixth type of semiconductor integrated-circuit (IC) chip 100 may be provided with an insulating bonding layer 521 on a backside 2b of its semiconductor substrate 2, wherein the insulating bonding layer 521 may include a silicon-oxide layer having a thickness between 0.1 and 2 μm. For the sixth type of semiconductor integrated-circuit (IC) chip 100, each of its through silicon vias (TSVs) 157 may include the copper layer 156 having a backside substantially coplanar with a bottom surface of its insulating bonding layer 521 and the insulating lining 153 surrounding the adhesion layer 154, seed layer 155 and copper layer 156 of said each of its through silicon vias (TSVs) 157.

[0299] FIG. 15A is a schematically cross-sectional view showing a first type of memory module in accordance with an embodiment of the present application. Referring to FIG. 15A, a memory module 159 may include (1) multiple memory chips 251, such as volatile-memory (VM) integrated circuit (IC) chips for a VM module, dynamic-random-access-memory (DRAM) IC chips for a high-bitwidth memory (HBM) module, statistic-random-access-memory (SRAM) IC chips for a SRAM module, magnetoresistive random-access-memory (MRAM) IC chips for a MRAM module, resistive random-access-memory (RRAM) IC chips for a RRAM module, ferroelectric random-access-memory (FRAM) IC chips for a FRAM module or phase change random access memory (PCM) IC chips for a PCM module, vertically stacked together, wherein the number of the memory chips 251 in the memory module 159 may have the number equal to or greater than 2, 4, 8, 16, 32, (2) a control chip 688, i.e., ASIC or logic chip, under the stacked memory chips 251, (3) multiple bonded metal contacts 158 between neighboring two of the memory chips 251 and between the bottommost one of the memory chips 251 and the control chip 688, and (4) multiple micro-bumps or micro-pads 34 on a bottom surface of the control chip 688.

[0300] Referring to FIG. 15A, each of the memory chips 251 may have the structure as illustrated in FIG. 14C, which may include the through silicon vias (TSVs) 157 in its semiconductor substrate 2, each aligned with and connected to one of the bonded metal contacts 158 at its backside.

[0301] FIGS. 16A and 16B are schematically cross-sectional views showing a process of bonding a thermal compression bump to a thermal compression pad in accordance with an embodiment of the present application. For a first case, referring to FIGS. 15A, 16A and 16B, an upper one of the memory chips 251 may have the third type of micro-bumps or micro-pads 34 to be bonded to the fourth type of micro-bumps or micro-pads 570 of a lower one of the memory chips 251. For example, the third type of micro-bumps or micro-pads 34 of the upper one of the memory chips 251 may have the solder caps 38 to be thermally compressed, at a temperature between 240 and 300 degrees Celsius, at a pressure between 0.3 and 3 MPa and for a time period between 3 and 15 seconds, onto the metal caps 49 of the fourth type of micro-bumps or micro-pads 570 of the lower one of the memory chips 251 into multiple bonded metal contacts 158 between the upper and lower ones of the memory chips 251. A force applied to the upper one of the memory chips 251 in the thermal compression process may be substantially equal to the pressure times a contact area between one of the third type of micro-bumps or micro-pads 34 and one of the fourth type of micro-bumps or micro-pads 570 times the total number of the third type of micro-bumps or micro-pads 34 of the upper one of the memory chips 251. Each of the third type of micro-bumps or micro-pads 34 of the upper one of the memory chips 251 may have the copper layer 37 having the thickness t3 greater than the thickness t2 of the copper layer 48 of each of the fourth type of micro-bumps or micro-pads 570 of the lower one of the memory chips 251 and having the largest transverse dimension w3 equal to between 0.7 and 0.1 times of the largest transverse dimension w2 of the copper layer 48 of each of the fourth type of micro-bumps or micro-pads 570 of the lower one of the memory chips 251. Alternatively, each of the third type of micro-bumps or micro-pads 34 may be provided with the copper layer 37 having a cross-sectional area equal to between 0.5 and 0.01 times of the cross-sectional area of the copper layer 48 of each of the fourth type of micro-bumps or micro-pads 570 of the lower one of the memory chips 251. For example, for the upper one of the memory chips 251, its third type of micro-bumps or micro-pads 34 may be formed respectively on a front surface of the metal pads 6b provided by the frontmost one of the interconnection metal layers 27 of its second interconnection scheme 588 or by, if the second interconnection scheme 588 is not provided, the frontmost one of the interconnection metal layers 6 of its first interconnection scheme 560, wherein each of the metal pads 6b may have a thickness t1 between 1 and 10 micrometers or between 2 and 10 micrometers and a largest transverse dimension w1, such as diameter in a circular shape, between 1 μm and 25 μm and each of its third type of micro-bumps or micro-pads 34 may be provided with the copper layer 37 having the thickness t3 greater than the thickness t1 of its metal pads 6b and having the largest transverse dimension w3 equal to between 0.7 and 0.1 times of the largest transverse dimension w1 of its metal pads 6b; alternatively, each of its third type of micro-bumps or micro-pads 34 may be provided with the copper layer 37 having a cross-sectional area equal to between 0.5 and 0.01 times of the cross-sectional area of its metal pads 6b. A bonded solder between the copper layers 37 and 48 of each of the bonded metal contacts 158 may be mostly kept on a top surface of the copper layer 48 of one of the fourth type of micro-bumps or micro-pads 570 of the lower one of the memory chips 251 and extends out of the edge of the copper layer 48 of said one of the fourth type of micro-bumps or micro-pads 570 of the lower one of the memory chips 251 less than 0.5 micrometers. Thus, a short between neighboring two of the bonded metal contacts 158 even in a fine-pitched fashion may be avoided.

[0302] Alternatively, for a second case, referring to FIG. 15A, an upper one of the memory chips 251 may have the second type of micro-bumps or micro-pads 34 to be bonded to the first type of micro-bumps or micro-pads 570 of a lower one of the memory chips 251. For example, the second type of micro-bumps or micro-pads 34 of the upper one of the memory chips 251 may have the solder caps 33 to be bonded onto the copper layer 32 of the first type of micro-bumps or micro-pads 570 of the lower one of the memory chips 251 into multiple bonded metal contacts 158 between the upper and lower ones of the memory chips 251. Each of the second type of micro-bumps or micro-pads 34 of the upper one of the memory chips 251 may have the copper layer 32 having a thickness greater than that of the copper layer 32 of each of the first type of micro-bumps or micro-pads 570 of the lower one of the memory chips 251.

[0303] Alternatively, for a third case, referring to FIG. 15A, an upper one of the memory chips 251 may have the first type of micro-bumps or micro-pads 34 to be bonded to the second type of micro-bumps or micro-pads 570 of a lower one of the memory chips 251. For example, the first type of micro-bumps or micro-pads 34 of the upper one of the memory chips 251 may have the electroplated metal layer 32, e.g. copper layer, to be bonded onto the solder caps 33 of the second type of micro-bumps or micro-pads 570 of the lower one of the memory chips 251 into multiple bonded metal contacts 158 between the upper and lower ones of the memory chips 251. Each of the first type of micro-bumps or micro-pads 34 of the upper one of the memory chips 251 may have the copper layer 32 having a thickness greater than that of the copper layer 32 of each of the second type of micro-bumps or micro-pads 570 of the lower one of the memory chips 251.

[0304] Alternatively, for a fourth case, referring to FIG. 15A, an upper one of the memory chips 251 may have the second type of micro-bumps or micro-pads 34 to be bonded to the second type of micro-bumps or micro-pads 570 of a lower one of the memory chips 251. For example, the second type of micro-bumps or micro-pads 34 of the upper one of the memory chips 251 may have the solder caps 33 to be bonded onto the solder caps 33 of the second type of micro-bumps or micro-pads 570 of the lower one of the memory chips 251 into multiple bonded metal contacts 158 between the upper and lower ones of the memory chips 251. Each of the second type of micro-bumps or micro-pads 34 of the upper one of the memory chips 251 may have the copper layer 32 having a thickness greater than that of the copper layer 32 of each of the second type of micro-bumps or micro-pads 570 of the lower one of the memory chips 251.

[0305] Referring to FIG. 15A, each of the through silicon vias (TSVs) 157 of the topmost one of the memory chips 251 may have its sidewall and backside enclosed by its semiconductor substrate 2. The bottommost one of the memory chips 251 may provide the micro-bumps or micro-pads 34 on its bottom surface to be bonded to the micro-bumps or micro-pads 570 on a top surface of the control chip 688 into multiple bonded metal contacts 158 between the control chip 688 and the bottommost one of the memory chips 251. The specification of the bonded metal contacts 158 between the control chip 688 and the bottommost one of the memory chips 251 and the process for forming the same may be referred to the specification of those between the upper and lower ones of the memory chips 251 as above illustrated in FIGS. 15A, 16A and 16B and the above-mentioned process for forming the same.

[0306] Referring to FIG. 15A, the through silicon vias (TSVs) 157 in the memory chips 251, which are aligned in a vertical direction, may couple to each other or one another through the bonded metal contacts 158 therebetween aligned in the vertical direction and with the through silicon vias (TSVs) 157 therein in the vertical direction. Each of the memory chips 251 and control chip 688 may include multiple interconnects 696 each provided by the interconnection metal layers 6 of its first interconnection scheme 560 and/or the interconnection metal layers 27 of its second interconnection scheme 588 to connect one or more of its through silicon vias (TSVs) 157 to one or more of the bonded metal contacts 158 at its bottom surface. An underfill 694, e.g., a polymer layer, may be provided between each neighboring two of the memory chips 251 to enclose the bonded metal contacts 158 therebetween and between the bottommost one of the memory chips 251 and the control chip 688 to enclose the bonded metal contacts 158 therebetween. A molding compound 695, e.g. a polymer, may be formed around the memory chips 251 and over the control chip 688, wherein the topmost one of the memory chips 251 may have a top surface coplanar with a top surface of the molding compound 695.

[0307] Referring to FIG. 15A, for the first type of memory module 159, each of its memory chips 251 may have a data bit-width, equal to or greater than 64, 128, 256, 512, 1024, 2048, 4096, 8K, or 16K, with external circuits of the first type of memory module 159 via its micro-bumps or micro-pads 34. The first type of memory module 159 may include multiple vertical interconnects 699 each composed of one of the through silicon vias (TSVs) 157 in each of the memory chips 251 of the first type of memory module 159, wherein for each of the vertical interconnects 699 of the first type of memory module 159, its through silicon vias (TSVs) 157 in the memory chips 251 of the first type of memory module 159 are aligned with each other or one another and are connected to one or more transistors of the semiconductor devices 4 of the memory chips 251 of the first type of memory module 159. Each of the memory chips 251 and control chip 688 may be provided with one or more small I/O circuits, each having driving capability, loading, output capacitance or input capacitance between 0.05 pF and 2 pF, or 0.05 pF and 1 pF, or smaller than 2 pF or 1 pF, coupling to one of the vertical interconnects 699 of the first type of memory module 159. alternatively each of the small input/output (I/O) circuits may have an I/O power efficiency smaller than 0.5 pico-Joules per bit, per switch or per voltage swing, or between 0.01 and 0.5 pico-Joules per bit, per switch or per voltage swing,

[0308] Referring to FIG. 15A, the control chip 688 may be configured to control data access to the memory chips 251. The control chip 688 may be used for buffering and controlling the memory chips 251. The control chip 688 may include the through silicon vias (TSVs) 157 in its semiconductor substrate 2, each aligned with and connected to one or more of its micro-bumps or micro-pads 34 on its bottom surface.

[0309] Alternatively, FIG. 15C is a schematically cross-sectional view showing a first type of memory module in accordance with another embodiment of the present application. Referring to FIG. 15C, the first type of memory module 159 may have a structure similar to that as illustrated in FIG. 15A. For an element indicated by the same reference number shown in FIGS. 15A and 15C, the specification of the element as seen in FIG. 15C may be referred to that of the element as illustrated in FIG. 15A. The difference between the first type of memory modules 159 as seen in FIGS. 15A and 15C is that a direct bonding process may be performed for the first type of memory module 159 as seen in FIG. 15C. FIGS. 16C and 16D are schematically cross-sectional views showing a direct bonding process in accordance with an embodiment of the present application. Referring to FIGS. 15C, 16C and 16D, each of the memory chips 251 and control chip 688 may have the structure as illustrated in FIG. 14F, which may include the through silicon vias (TSVs) 157 in its semiconductor substrate 2 each aligned with its metal pads 6a at its active side. An upper one of the memory chips 251 may join a lower one of the memory chips 251 and control chip 688 by (1) activating a joining surface, i.e., silicon oxide, of the insulating bonding layer 52 at the active side of the upper one of the memory chips 251 and a joining surface, i.e., silicon oxide, of the insulating bonding layer 521 at the backside of the lower one of the memory chips 251 and control chip 688 with nitrogen plasma for increasing hydrophilic property thereof, (2) next rinsing the joining surface of the insulating bonding layer 52 at the active side of the upper one of the memory chips 251 and the joining surface of the insulating bonding layer 521 at the backside of the lower one of the memory chips 251 and control chip 688 with deionized water for water adsorption and cleaning, (3) next placing the upper one of the memory chips 251 onto the lower one of the memory chips 251 and control chip 688 with each of the metal pads 6a at the active side of the upper one of the memory chips 251 in contact with one of the through silicon vias (TSVs) 157 of the lower one of the memory chips 251 and control chip 688 and with the joining surface of the insulating bonding layer 52 at the active side of the upper one of the memory chips 251 in contact with the joining surface of the insulating bonding layer 521 at the backside of the lower one of the memory chips 251 and control chip 688, and (4) next performing a direct bonding process including (a) oxide-to-oxide bonding at a temperature between 100 and 200 degrees Celsius and for a time period between 5 and 20 minutes to bond the joining surface of the insulating bonding layer 52 at the active side of the upper one of the memory chips 251 to the joining surface of the insulating bonding layer 521 at the backside of the lower one of the memory chips 251 and control chip 688 and (b) copper-to-copper bonding at a temperature between 300 and 350 degrees Celsius and for a time period between 10 and 60 minutes to bond the copper layer 24 of each of the metal pads 6a at the active side of the upper one of the memory chips 251 to the copper layer 156 of one of the through silicon vias (TSVs) 157 of the lower one of the memory chips 251 and control chip 688, wherein the oxide-to-oxide bonding may be caused by water desorption from reaction between the joining surface of the insulating bonding layer 52 at the active side of the upper one of the memory chips 251 and the joining surface of the insulating bonding layer 521 at the backside of the lower one of the memory chips 251, and the copper-to-copper bonding may be caused by metal inter-diffusion between the copper layer 24 of the metal pads 6a at the active side of the upper one of the memory chips 251 and the copper layer 156 of the through silicon vias (TSVs) 157 of the lower one of the memory chips 251 and control chip 688.

[0310] FIGS. 15B and 15D are schematically cross-sectional views showing various second type of memory modules in accordance with an embodiment of the present application. Referring to FIG. 15B, the second type of memory module 159 may have a structure similar to that as illustrated in FIG. 15A. For an element indicated by the same reference number shown in FIGS. 15A and 15B, the specification of the element as seen in FIG. 15B may be referred to that of the element as illustrated in FIG. 15A. Referring to FIG. 15D, the second type of memory module 159 may have a structure similar to that as illustrated in FIG. 15C. For an element indicated by the same reference number shown in FIGS. 15A, 15C and 15D, the specification of the element as seen in FIG. 15D may be referred to that of the element as illustrated in FIG. 15A or 15C. The difference between the first and second types of memory modules 159 is that the second type of memory module 159 may further include multiple dedicated vertical bypasses 698 each composed of one of the through silicon vias (TSVs) 157 in each of the memory chips 251 and control chip 688 of the second type of memory module 159, wherein for each of the dedicated vertical bypasses 698 of the second type of memory module 159, its through silicon vias (TSVs) 157 in the memory chips 251 and control chip 688 of the second type of memory module 159 are aligned with each other or one another and are not connected to any transistor of the memory chips 251 or control chip 688 of the second type of memory module 159.

[0311] FIGS. 17A-17F are schematically cross-sectional views showing a process for fabricating a first type of operation unit in accordance with an embodiment of the present application. Referring to FIG. 17A, a semiconductor wafer 100c may be provided at an active side thereof with the insulating bonding layer 52 and metal pads 6a as illustrated in FIG. 14D, wherein neighboring two of the metal pads 6a of the semiconductor wafer 100c may have a pitch between 3 and 10 micrometers or between 4 and 7 micrometers. Next, referring to FIGS. 17A and 17B, each of first or second type of memory modules 159 may have the same structure as illustrated in FIG. 15C or 15D provided with the insulating bonding layer 52 to be bonded to the insulating bonding layer 52 of the semiconductor wafer 100c and the metal pads 6a, neighboring two of which may have a pitch between 3 and 10 micrometers or between 4 and 7 micrometers, to be bonded to the metal pads 6a of the semiconductor wafer 100c. Each of known-good memory, logic or application-specific-integrated-circuit (ASIC) chips 121 may have the structure as illustrated in FIG. 14E provided at an active side thereof with the insulating bonding layer 52 to be bonded to the insulating bonding layer 52 of the semiconductor wafer 100c and the metal pads 6a, neighboring two of which may have a pitch between 3 and 10 micrometers or between 4 and 7 micrometers, to be bonded to the metal pads 6a of the semiconductor wafer 100c. For example, each of the known-good memory, logic or application-specific-integrated-circuit (ASIC) chips 121 may be (1) an application specific integrated-circuit (ASIC) logic chip, (2) a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip 200 as illustrated in FIG. 9 or dedicated programmable interconnection (DPI) integrated-circuit (IC) chip 410 as illustrated in FIG. 10, (3) a processing and/or computing integrated-circuit (IC) chip, such as graphic-processing-unit (GPU) integrated-circuit (IC) chip, central-processing-unit (CPU) integrated-circuit (IC) chip, tensor-processing-unit (TPU) integrated-circuit (IC) chip, network-processing-unit (NPU) integrated-circuit (IC) chip, application-processing-unit (APU) integrated-circuit (IC) chip, digital-signal-processing (DSP) integrated-circuit (IC) chip, (4) a memory integrated-circuit (IC) chip, such as non-volatile NAND chip, non-volatile NOR flash chip, non-volatile magnetoresistive random-access-memory (MRAM) integrated-circuit (IC) chip, non-volatile resistive random access memory (RRAM) integrated-circuit (IC) chip, non-volatile phase-change random-access-memory (PCM) integrated-circuit (IC) chip, non-volatile ferroelectric-random-access-memory (FRAM) integrated-circuit (IC) chip or high bandwidth dynamic random-access-memory (DRAM) or static random-access-memory (SRAM) memory (HBM) chip, (5) an auxiliary and supporting (AS) integrated-circuit (IC) chip 411 as illustrated in FIG. 11, (6) an IAC IC chip 402 as illustrated in FIG. 12A, (7) a dedicated I/O chip 265 or dedicated control and I/O chip 260 as illustrated in FIGS. 12A and 12B, or (8) a power management integrated-circuit (IC) chip. Multiple second type of vertical-through-via (VTV) connectors 467, each of which may be one as illustrated in any of FIGS. 1B, 1D, 1F, 2B, 2D and 2F, may be provided with the insulating bonding layer 52 to be bonded to the insulating bonding layer 52 of the semiconductor wafer 100c and the vertical through vias (VTVs) 358, neighboring two of which may have a pitch between 3 and 10 micrometers or between 4 and 7 micrometers, to be bonded to the metal pads 6a of the semiconductor wafer 100c.

[0312] Referring to FIGS. 17A and 17B, before the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the second type of vertical-through-via (VTV) connectors 467 are bonded to the semiconductor wafer 100c, a joining surface, i.e., silicon oxide, of the insulating bonding layer 52 at the active side of the semiconductor wafer 100c may be activated with nitrogen plasma for increasing a hydrophilic property thereof, and then the joining surface of the insulating bonding layer 52 at the active side of the semiconductor wafer 100c may be rinsed with deionized water for water adsorption and cleaning. Further, a joining surface, i.e., silicon oxide, of the insulating bonding layer 52 at the active side of the control chip 688 of each of the first or second type of memory modules 159, a joining surface, i.e., silicon oxide, of the insulating bonding layer 52 at the active side of each of the known-good memory, logic or ASIC chips 121 and a joining surface, i.e., silicon oxide, of the insulating bonding layer 52 of each of the second type of vertical-through-via (VTV) connectors 467 may be activated with nitrogen plasma for increasing a hydrophilic property thereof, and then the joining surface of the insulating bonding layer 52 at the active side of the control chip 688 of each of the first or second type of memory modules 159, the joining surface of the insulating bonding layer 52 at the active side of each of the known-good memory, logic or ASIC chips 121, and the joining surface of the insulating bonding layer 52 of each of the second type of vertical-through-via (VTV) connectors 467 may be rinsed with deionized water for water adsorption and cleaning.

[0313] Next, referring to FIGS. 17A and 17B, the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the second type of vertical-through-via (VTV) connectors 467 may be bonded to the semiconductor wafer 100c by (1) picking up each of the first or second type of memory modules 159 to be placed on the semiconductor wafer 100c with each of the metal pads 6a at the active side of the control chip 688 of each of the first or second type of memory modules 159 in contact with one of the metal pads 6a at the active side of the semiconductor wafer 100c and with the joining surface of the insulating bonding layer 52 at the active side of the control chip 688 of each of the first or second type of memory modules 159 in contact with the joining surface of the insulating bonding layer 52 at the active side of the semiconductor wafer 100c, (2) picking up each of the known-good memory, logic or ASIC chips 121 to be placed on the semiconductor wafer 100c with each of the metal pads 6a at the active side of each of the known-good memory, logic or ASIC chips 121 in contact with one of the metal pads 6a at the active side of the semiconductor wafer 100c and with the joining surface of the insulating bonding layer 52 at the active side of each of the known-good memory, logic or ASIC chips 121 in contact with the joining surface of the insulating bonding layer 52 at the active side of the semiconductor wafer 100c, (3) picking up each of the second type of vertical-through-via (VTV) connectors 467 to be placed on the semiconductor wafer 100c with each of the vertical through vias (VTVs) 358 of each of the second type of vertical-through-via (VTV) connectors 467 in contact with one of the metal pads 6a at the active side of the semiconductor wafer 100c and with the joining surface of the insulating bonding layer 52 of each of the second type of vertical-through-via (VTV) connectors 467 in contact with the joining surface of the insulating bonding layer 52 at the active side of the semiconductor wafer 100c, and (4) next performing a direct bonding process including (a) oxide-to-oxide bonding at a temperature between 100 and 200 degrees Celsius and for a time period between 5 and 20 minutes to bond the joining surface of the insulating bonding layer 52 at the active side of the control chip 688 of each of the first or second type of memory modules 159, the joining surface of the insulating bonding layer 52 at the active side of each of the known-good memory, logic or ASIC chips 121 and the joining surface of the insulating bonding layer 52 of each of the second type of vertical-through-via (VTV) connectors 467 to the joining surface of the insulating bonding layer 52 at the active side of the semiconductor wafer 100c and (b) copper-to-copper bonding at a temperature between 300 and 350 degrees Celsius and for a time period between 10 and 60 minutes to bond the copper layer 24 of each of the metal pads 6a at the active side of the control chip 688 of each of the first or second type of memory modules 159 to the copper layer 24 of one of the metal pads 6a at the active side of the semiconductor wafer 100c, to bond the copper layer 24 of each of the metal pads 6a at the active side of each of the known-good memory, logic or ASIC chips 121 to the copper layer 24 of one of the metal pads 6a at the active side of the semiconductor wafer 100c and to bond the copper layer 24 of each of the vertical through vias (VTVs) 358 of each of the second type of vertical-through-via (VTV) connectors 467 to the copper layer 24 of one of the metal pads 6a at the active side of the semiconductor wafer 100c. The oxide-to-oxide bonding may be caused by water desorption from reaction between the joining surface of the insulating bonding layer 52 at the active side of the control chip 688 of each of the first or second type of memory modules 159 and the joining surface of the insulating bonding layer 52 at the active side of the semiconductor wafer 100c, between the joining surface of the insulating bonding layer 52 at the active side of each of the known-good memory, logic or ASIC chips 121 and the joining surface of the insulating bonding layer 52 at the active side of the semiconductor wafer 100c and between the joining surface of the insulating bonding layer 52 of each of the second type of vertical-through-via (VTV) connectors 467 and the joining surface of the insulating bonding layer 52 at the active side of the semiconductor wafer 100c. The copper-to-copper bonding may be caused by metal inter-diffusion between the copper layer 24 of the metal pads 6a at the active side of the control chip 688 of each of the first or second type of memory modules 159 and the copper layer 24 of the metal pads 6a at the active side of the semiconductor wafer 100c, between the copper layer 24 of the metal pads 6a at the active side of each of the known-good memory, logic or ASIC chips 121 and the copper layer 24 of the metal pads 6a at the active side of the semiconductor wafer 100c and between the copper layer 24 of the vertical through vias (VTVs) 358 of each of the second type of vertical-through-via (VTV) connectors 467 and the copper layer 24 of the metal pads 6a at the active side of the semiconductor wafer 100c.

[0314] Next, referring to FIG. 17C, a polymer layer 565, e.g., resin or compound, may be applied to fill a gap between each neighboring two of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the second type of vertical-through-via (VTV) connectors 467 and to cover a backside of each of the first or second type of memory modules 159, a backside of each of the known-good memory, logic or ASIC chips 121 and a backside of each of the second type of vertical-through-via (VTV) connectors 467 by methods, for example, spin-on coating, screen-printing, dispensing or molding. The polymer layer 565 may be, for example, polyimide, BenzoCycloButene (BCB), parylene, parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer, or silicone. The polymer layer 565 may be, for example, photosensitive polyimide/PBO PIMEL™ supplied by Asahi Kasei Corporation, Japan, or epoxy-based molding compounds, resins or sealants provided by Nagase ChemteX Corporation, Japan. The polymer layer 565 may be cured or cross-linked at a temperature higher than or equal to 50, 70, 90, 100, 125, 150, 175, 200, 225, 250, 275 or 300 degrees Celsius.

[0315] Next, referring to FIG. 17D, a chemical mechanical polishing (CMP), polishing or grinding process may be applied to remove a top portion of the polymer layer 565, a top portion of each of the first or second type of memory modules 159, a top portion of each of the known-good memory, logic or ASIC chips 121 and a top portion of each of the second type of vertical-through-via (VTV) connectors 467, to planarize a top surface of the polymer layer 565, a top surface of each of the first or second type of memory modules 159, a top surface of each of the known-good memory, logic or ASIC chips 121 and a top surface of each of the second type of vertical-through-via (VTV) connectors 467 and to expose a backside of each of the vertical through vias (VTVs) 358 of each of the second type of vertical-through-via (VTV) connectors 467, a backside of the copper layer 156 of each of the through silicon vias (TSVs) 157 of the topmost one of the memory chips 251 of each of the first or second type of memory modules 159 and a backside of the copper layer 156 of each of the through silicon vias (TSVs) 157 of each of the known-good memory, logic or ASIC chips 121.

[0316] For each of the through silicon vias (TSVs) 157 of the topmost one of the memory chips 251 of said each of the first or second type of memory modules 159 and the through silicon vias (TSVs) 157 of said each of the known-good memory, logic or ASIC chips 121, its insulating lining layer 153, adhesion layer 154 and seed layer 155 at its backside may be removed to expose a backside of its copper layer 156, which may be coplanar with a backside of said each of the first or second type of memory modules 159, a backside of said each of the known-good memory, logic or ASIC chips 121 and a top surface of the polymer layer 565, and its insulating lining layer 153, adhesion layer 154 and seed layer 155 at a sidewall of its copper layer 156 may be left. For each of the vertical through vias (VTVs) 358 of said each of the second type of vertical-through-via (VTV) connectors 467, if made of one or more of the through silicon vias (TSVs) 157 as illustrated in one of FIGS. 1B, 1D, 1E, 2B, 2D and 2E, its insulating lining layer 153, adhesion layer 154 and seed layer 155 at its backside may be removed to expose a backside of its copper layer 156, which may be coplanar with a backside of said each of the second type of vertical-through-via (VTV) connectors 467 and a top surface of the polymer layer 565, and its insulating lining layer 153, adhesion layer 154 and seed layer 155 at a sidewall of its copper layer 156 may be left.

[0317] Next, referring to FIG. 17E, an insulating dielectric layer 93 may be formed on the top surface of the polymer layer 565, the backside of each of the first or second type of memory modules 159, the backside of each of the known-good memory, logic or ASIC chips 121 and the backside of each of the second type of vertical-through-via (VTV) connectors 467. Each opening in the insulating dielectric layer 93 may be vertically over the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of the topmost one of the memory chips 251 of one of the first or second type of memory modules 159, the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of one of the known-good memory, logic or ASIC chips 121 or the backside of one of the vertical through vias (VTVs) 358 of one of the second type of vertical-through-via (VTV) connectors 467. The insulating dielectric layer 93 may be a layer of polymer, such as polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer or silicone, having a thickness between 3 and 30 micrometers or between 5 and 15 micrometers.

[0318] Next, referring to FIG. 17E, each micro-bump or micro-pad 197, which may be of one of the first through fourth types having the same specifications as the first through fourth types of micro-bumps or micro-pads 34 as illustrated in FIG. 1A, 1C or 1E respectively, may be formed on the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of the topmost one of the memory chips 251 of one of the first or second type of memory modules 159, the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of one of the known-good memory, logic or ASIC chips 121 or the backside of one of the vertical through vias (VTVs) 358 of one of the second type of vertical-through-via (VTV) connectors 467. Said each micro-bump or micro-pad 197 may be of the first type, including (1) an adhesion layer 26a, such as titanium (Ti) or titanium nitride (TiN) layer having a thickness between 1 nm and 50 nm, on the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of the topmost one of the memory chips 251 of one of the first or second type of memory modules 159, the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of one of the known-good memory, logic or ASIC chips 121 or the backside of the copper layer 156 of one of the vertical through vias (VTVs) 358 of one of the second type of vertical-through-via (VTV) connectors 467, (2) a seed layer 26b, such as copper, on its adhesion layer 26a and (3) a copper layer 32 having a thickness between 1 μm and 60 μm on its seed layer 26b.

[0319] Alternatively, referring to FIG. 17E, said each micro-bump or micro-pad 197 may be of the second type, including the adhesion layer 26a, seed layer 26b and copper layer 32 as mentioned above, and further including, as seen in FIG. 17E, a tin-containing solder cap 33 made of tin or a tin-silver alloy having a thickness between 1 μm and 50 μm on its copper layer 32.

[0320] Alternatively, referring to FIG. 17E, said each micro-bump or micro-pad 197 may be of the third type used as a thermal compression bump, including the adhesion layer 26a and seed layer 26b as mentioned above, and further including, as seen in any of 16A, 18A, 28A, 29A, 35A and 36A, a copper layer 37 having a thickness t3 between 2 μm and 20 μm and a largest transverse dimension w3, such as diameter in a circular shape, between 1 μm and 25 μm on its seed layer 26b and a solder cap 38 made of a tin-silver alloy, a tin-gold alloy, a tin-copper alloy, a tin-indium alloy, indium or tin, which has a thickness between 1 μm and 15 μm and a largest transverse dimension, such as diameter in a circular shape, between 1 μm and 15 μm on its copper layer 37. A pitch between neighboring two of the third type of micro-bumps or micro-pads 197 may be between 5 and 30 micrometers or between 10 and 25 micrometers.

[0321] Alternatively, referring to FIG. 17E, said each micro-bump or micro-pad 197 may be of the fourth type used as a thermal compression pad, including the adhesion layer 26a and seed layer 26b as mentioned above, and further including, as seen in FIG. 18A, a copper layer 48 having a thickness t2 between 1 μm and 20 μm or between 2 μm and 10 μm and a largest transverse dimension w2, such as diameter in a circular shape, between 5 μm and 50 μm, on its seed layer 26b and a solder cap 49 made of a tin-silver alloy, a tin-gold alloy, a tin-copper alloy, a tin-indium alloy, indium, tin or gold, which has a thickness between 0.1 μm and 5 μm on its copper layer 48. A pitch between neighboring two of the fourth type of micro-bumps or micro-pads 197 may be between 5 and 30 micrometers or between 10 and 25 micrometers.

[0322] Next, referring to FIG. 17E, the semiconductor wafer 100c, polymer layer 565 and insulating dielectric layer 93 may be cut or diced to form multiple first type of operation units 190 each for a second type of chip-on-chip (COC) component or package, as shown in FIG. 17F by a laser cutting process or by a mechanical cutting process. At this time, the semiconductor wafer 100c may be cut or diced into multiple semiconductor integrated-circuit (IC) chips 399, each of which may have the same specification as the semiconductor integrated-circuit (IC) chip 100 as illustrated in FIG. 14D and may be (1) an application specific integrated-circuit (ASIC) logic chip, (2) a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip 200 as illustrated in FIG. 9 or dedicated programmable interconnection (DPI) integrated-circuit (IC) chip 410 as illustrated in FIG. 10, (3) a processing and/or computing integrated-circuit (IC) chip, such as graphic-processing-unit (GPU) integrated-circuit (IC) chip, central-processing-unit (CPU) integrated-circuit (IC) chip, tensor-processing-unit (TPU) integrated-circuit (IC) chip, network-processing-unit (NPU) integrated-circuit (IC) chip, application-processing-unit (APU) integrated-circuit (IC) chip, digital-signal-processing (DSP) integrated-circuit (IC) chip, (4) a memory integrated-circuit (IC) chip, such as non-volatile NAND chip, non-volatile NOR flash chip, non-volatile magnetoresistive random-access-memory (MRAM) integrated-circuit (IC) chip, non-volatile resistive random access memory (RRAM) integrated-circuit (IC) chip, non-volatile phase-change random-access-memory (PCM) integrated-circuit (IC) chip, non-volatile ferroelectric-random-access-memory (FRAM) integrated-circuit (IC) chip or high bandwidth dynamic random-access-memory (DRAM) or static random-access-memory (SRAM) memory (HBM) chip, (5) an auxiliary and supporting (AS) integrated-circuit (IC) chip 411 as illustrated in FIG. 11, (6) an IAC IC chip 402 as illustrated in FIG. 12A, (7) a dedicated I/O chip 265 or dedicated control and I/O chip 260 as illustrated in FIGS. 12A and 12B, or (8) a power management integrated-circuit (IC) chip.

[0323] Alternatively, FIG. 17G is a schematically cross-sectional view showing a first type of operation unit in accordance with another embodiment of the present application. For an element indicated by the same reference number shown in FIGS. 17A-17G, the specification of the element as seen in FIG. 17G may be referred to that of the element as illustrated in FIGS. 17A-17F. Referring to FIG. 17G, the semiconductor wafer 100c may be provided at an active side thereof with the first, second or fourth type of micro-bumps or micro-pads 34, as illustrated in FIG. 14A, instead of the insulating bonding layer 52 and metal pads 6a. Each of the first or second type of memory modules 159 (only one is shown) formed as illustrated in FIG. 15A or 15B respectively may have the first, second or third type of micro-bumps or micro-pads 34 to be bonded to the first, second or fourth type of micro-bumps or micro-pads 34 preformed at an active side of the semiconductor wafer 100c into multiple bonded metal contacts 563 respectively therebetween. Each of the known-good memory, logic or ASIC chips 121 (only one is shown) may have the structure as illustrated in FIG. 14B provided at an active side thereof with the first, second or third type of micro-bumps or micro-pads 34 to be bonded to the first, second or fourth type of micro-bumps or micro-pads 34 preformed at an active side of the semiconductor wafer 100c into multiple bonded metal contacts 563 respectively therebetween. Each of the first type of vertical-through-via (VTV) connectors 467 as illustrated in any of FIGS. 1A, 1C, 1E, 2A, 2C, 2E, 4A, 4B, 4C, 5A, 5B, 5C and 6 may be provided with the first, second, third, fifth or sixth type of micro-bumps or micro-pads 34 to be bonded to the first, second or fourth type of micro-bumps or micro-pads 34 preformed at the active side of the semiconductor wafer 100c into multiple bonded metal contacts 563 respectively therebetween.

[0324] FIGS. 18A and 18B are schematically cross-sectional views showing a process of bonding a thermal compression bump to a thermal compression pad in accordance with an embodiment of the present application. For a first case, referring to FIGS. 17G, 18A and 18B, each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may have the third type of micro-bumps or micro-pads 34 to be bonded to the fourth type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c. For example, the third type of micro-bumps or micro-pads 34 of said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may have the solder caps 38 to be thermally compressed, at a temperature between 240 and 300 degrees Celsius, at a pressure between 0.3 and 3 Mpa and for a time period between 3 and 15 seconds, onto the metal caps 49 of the fourth type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c into multiple bonded metal contacts 563 between said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 and the semiconductor wafer 100c, wherein neighboring two of the bonded metal contacts 563 may have a pitch between 5 and 30 micrometers or 10 and 25 micrometers. Each of the third type of micro-bumps or micro-pads 34 of said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may have the copper layer 37 having the thickness t3 greater than the thickness t2 of the copper layer 48 of each of the fourth type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c and having the largest transverse dimension w3 equal to between 0.7 and 0.1 times of the largest transverse dimension w2 of the copper layer 48 of each of the fourth type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c. Alternatively, each of the third type of micro-bumps or micro-pads 34 of said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may be provided with the copper layer 37 having a cross-sectional area equal to between 0.5 and 0.01 times of the cross-sectional area of the copper layer 48 of each of the fourth type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c.

[0325] For example, referring to FIGS. 17G, 18A and 18B, for each of the first or second type of memory modules 159, its third type of micro-bumps or micro-pads 34 may be formed respectively on a front surface of the metal pads 6b provided by the frontmost one of the interconnection metal layers 27 of the second interconnection scheme 588 of its control chip 688 or by, if the second interconnection scheme 588 is not provided for its control chip 688, the frontmost one of the interconnection metal layers 6 of the first interconnection scheme 560 of its control chip 688, wherein each of its third type of micro-bumps or micro-pads 34 may be provided with the copper layer 37 having the thickness t3 greater than the thickness t1 of each of the metal pads 6b of its control chip 688 and having the largest transverse dimension w3 equal to between 0.7 and 0.1 times of the largest transverse dimension w1 of each of the metal pads 6b of its control chip 688; alternatively, each of its third type of micro-bumps or micro-pads 34 may be provided with the copper layer 37 having a cross-sectional area equal to between 0.5 and 0.01 times of the cross-sectional area of each of the metal pads 6b of its control chip 688; each of the metal pads 6b of its control chip 688 may have a thickness t1 between 1 and 10 micrometers or between 2 and 10 micrometers and a largest transverse dimension w1, such as diameter in a circular shape, between 1 μm and 25 μm. For each of the known-good memory, logic or ASIC chips 121, its third type of micro-bumps or micro-pads 34 may be formed respectively on a front surface of the metal pads 6b provided by the frontmost one of the interconnection metal layers 27 of its second interconnection scheme 588 or by, if its second interconnection scheme 588 is not provided, the frontmost one of the interconnection metal layers 6 of its first interconnection scheme 560, wherein each of its third type of micro-bumps or micro-pads 34 may be provided with the copper layer 37 having the thickness t3 greater than the thickness t1 of each of its metal pads 6b and having the largest transverse dimension w3 equal to between 0.7 and 0.1 times of the largest transverse dimension w1 of each of its metal pads 6b; alternatively, each of its third type of micro-bumps or micro-pads 34 may be provided with the copper layer 37 having a cross-sectional area equal to between 0.5 and 0.01 times of the cross-sectional area of each of its metal pads 6b; each of its metal pads 6b may have a thickness t1 between 1 and 10 micrometers or between 2 and 10 micrometers and a largest transverse dimension w1, such as diameter in a circular shape, between 1 μm and 25 μm. A bonded solder between the copper layers 37 and 48 of each of the bonded metal contacts 563 may be mostly kept on a top surface of the copper layer 48 of one of the fourth type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c and extends out of the edge of the copper layer 48 of said one of the fourth type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c less than 0.5 micrometers. Thus, a short between neighboring two of the bonded metal contacts 563 even in a fine-pitched fashion may be avoided.

[0326] Alternatively, for a second case, referring to FIG. 17G, each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may have the second type of micro-bumps or micro-pads 34 to be bonded to the first type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c. For example, the second type of micro-bumps or micro-pads 34 of said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may have the solder caps 33 to be bonded onto the copper layer 32 of the first type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c into multiple bonded metal contacts 563 between said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 and the semiconductor wafer 100c. Each of the second type of micro-bumps or micro-pads 34 of said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may have the copper layer 32 having a thickness greater than that of the copper layer 32 of each of the first type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c.

[0327] Alternatively, for a third case, referring to FIG. 17G, each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may have the first type of micro-bumps or micro-pads 34 to be bonded to the second type of metal bumps or pillars 34 of the semiconductor wafer 100c. For example, the first type of micro-bumps or micro-pads 34 of said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may have the electroplated metal layer 32, e.g. copper layer, to be bonded onto the solder caps 33 of the second type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c into multiple bonded metal contacts 563 between said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 and the semiconductor wafer 100c. Each of the first type of micro-bumps or micro-pads 34 of said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may have the copper layer 32 having a thickness greater than that of the copper layer 32 of each of the second type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c.

[0328] Alternatively, for a fourth case, referring to FIG. 17G, each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may have the second type of micro-bumps or micro-pads 34 to be bonded to the second type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c. For example, the second type of micro-bumps or micro-pads 34 of said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may have the solder caps 33 to be bonded onto the solder caps 33 of the second type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c into multiple bonded metal contacts 563 between said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 and the semiconductor wafer 100c. Each of the second type of micro-bumps or micro-pads 34 of said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may have the copper layer 32 having a thickness greater than that of the copper layer 32 of each of the second type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c.

[0329] Next, referring to FIG. 17G, an underfill 564, such as a layer of polymer or epoxy resins or compounds, may be filled into a gap between each of the first or second type of memory modules 159 and the semiconductor wafer 100c to enclose the bonded metal contacts 563 therebetween, into a gap between each of the known-good memory, logic or ASIC chips 121 and the semiconductor wafer 100c to enclose the bonded metal contacts 563 therebetween and into a gap between each of the first type of vertical-through-via (VTV) connectors 467 and the semiconductor wafer 100c to enclose the bonded metal contacts 563 therebetween. The underfill 564 may be cured at temperature equal to or above 100, 120 or 150 degrees Celsius.

[0330] Referring to FIG. 17G, the following process may be referred to the process as illustrated in FIGS. 17C-17F. When the chemical mechanical polishing (CMP), polishing or grinding process as illustrated in FIG. 17D is performed, for each of the vertical through vias (VTVs) 358 of said each of the first type of vertical-through-via (VTV) connectors 467, if made of one or more of the through silicon vias (TSVs) 157 as illustrated in one of FIGS. 1A, 1C, 1E, 2A, 2C and 2E for the first and second alternatives, its insulating lining layer 153, adhesion layer 154 and seed layer 155 at its backside may be removed to expose a backside of its copper layer 156, which may be coplanar with a backside of said each of the first type of vertical-through-via (VTV) connectors 467 and a top surface of the polymer layer 565, and its insulating lining layer 153, adhesion layer 154 and seed layer 155 at a sidewall of its copper layer 156 may be left; for each of the vertical through vias (VTVs) 358 of said each of the first type of vertical-through-via (VTV) connectors 467, if made of one or more of the through glass vias (TGVs) 259 as illustrated in one of FIGS. 4A, 4B, 4C, 5A, 5B and 5C for the third and fourth alternatives, a backside of its copper post 706 may be exposed with being coplanar with a backside of said each of the first type of vertical-through-via (VTV) connectors 467 and the top surface of the polymer layer 565; for each of the vertical through vias (VTVs) 358 of said each of the first type of vertical-through-via (VTV) connectors 467, if made of one or more of the through polymer vias (TPVs) 318 as illustrated in FIG. 6 for the fifth alternative, a backside of its metal pad 336 or copper post 318 may be exposed with being coplanar with a backside of said each of the first type of vertical-through-via (VTV) connectors 467 and the top surface of the polymer layer 565.

[0331] Next, referring to FIG. 17G, each of the micro-bumps or micro-pads 197, which may be of one of the first through fourth types having the same specifications as the first through fourth types of micro-bumps or micro-pads 197 as illustrated in FIG. 17E respectively, may include the adhesion layer 26a on the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of the topmost one of the memory chips 251 of one of the first or second type of memory modules 159, the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of one of the known-good memory, logic or ASIC chips 121 or the backside of one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467. Said each micro-bump or micro-pad 197 may be any of the first through fourth types, including (1) the adhesion layer 26a, such as titanium (Ti) or titanium nitride (TiN) layer having a thickness between 1 nm and 50 nm, on the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of the topmost one of the memory chips 251 of one of the first or second type of memory modules 159, the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of one of the known-good memory, logic or ASIC chips 121, the backside of the copper layer 156 of one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 for the first and second alternatives, the backside of the copper post 706 of one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 for the third and fourth alternatives or the backside of the metal pad 336 or copper post 318 of one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 for the fifth alternative.

[0332] Next, the semiconductor wafer 100c, polymer layer 565 and insulating dielectric layer 93 may be cut or diced to form multiple first type of operation units 190 each for a second type of chip-on-chip (COC) component or package, as shown in FIG. 17G by a laser cutting process or by a mechanical cutting process. At this time, the semiconductor wafer 100c may be cut or diced into multiple semiconductor integrated-circuit (IC) chips 399, each of which may have the same specification as the semiconductor integrated-circuit (IC) chip 100 as illustrated in FIG. 14A or 14B and may be (1) an application specific integrated-circuit (ASIC) logic chip, (2) a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip 200 as illustrated in FIG. 9 or dedicated programmable interconnection (DPI) integrated-circuit (IC) chip 410 as illustrated in FIG. 10, (3) a processing and/or computing integrated-circuit (IC) chip, such as graphic-processing-unit (GPU) integrated-circuit (IC) chip, central-processing-unit (CPU) integrated-circuit (IC) chip, tensor-processing-unit (TPU) integrated-circuit (IC) chip, network-processing-unit (NPU) integrated-circuit (IC) chip, application-processing-unit (APU) integrated-circuit (IC) chip, digital-signal-processing (DSP) integrated-circuit (IC) chip, (4) a memory integrated-circuit (IC) chip, such as non-volatile NAND chip, non-volatile NOR flash chip, non-volatile magnetoresistive random-access-memory (MRAM) integrated-circuit (IC) chip, non-volatile resistive random access memory (RRAM) integrated-circuit (IC) chip, non-volatile phase-change random-access-memory (PCM) integrated-circuit (IC) chip, non-volatile ferroelectric-random-access-memory (FRAM) integrated-circuit (IC) chip or high bandwidth dynamic random-access-memory (DRAM) or static random-access-memory (SRAM) memory (HBM) chip, (5) an auxiliary and supporting (AS) integrated-circuit (IC) chip 411 as illustrated in FIG. 11, (6) an IAC IC chip 402 as illustrated in FIG. 12A, (7) a dedicated I/O chip 265 or dedicated control and I/O chip 260 as illustrated in FIGS. 12A and 12B, or (8) a power management integrated-circuit (IC) chip.

[0333] FIGS. 19A-19G are schematically cross-sectional views showing a process for fabricating a first type of operation unit in accordance with another embodiment of the present application. Referring to FIG. 19A, a semiconductor wafer 100d may be provided at an active side thereof with the insulating bonding layer 52 and metal pads 6a and provided with the through silicon vias (TSVs) 157 in the silicon substrate 2 thereof as illustrated in FIG. 14E, wherein neighboring two of the metal pads 6a of the semiconductor wafer 100d may have a pitch between 3 and 10 micrometers or between 4 and 7 micrometers. Next, referring to FIGS. 19A and 19B, each of first or second type of memory modules 159 may have the same structure as illustrated in FIG. 15C or 15D provided with the insulating bonding layer 52 to be bonded to the insulating bonding layer 52 of the semiconductor wafer 100d and the metal pads 6a, neighboring two of which may have a pitch between 3 and 10 micrometers or between 4 and 7 micrometers, to be bonded to the metal pads 6a of the semiconductor wafer 100d. Each of known-good memory, logic or application-specific-integrated-circuit (ASIC) chips 121 may have the structure as illustrated in FIG. 14D provided at an active side thereof with the insulating bonding layer 52 to be bonded to the insulating bonding layer 52 of the semiconductor wafer 100d and the metal pads 6a, neighboring two of which may have a pitch between 3 and 10 micrometers or between 4 and 7 micrometers, to be bonded to the metal pads 6a of the semiconductor wafer 100d. For example, each of the known-good memory, logic or application-specific-integrated-circuit (ASIC) chips 121 may be (1) an application specific integrated-circuit (ASIC) logic chip, (2) a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip 200 as illustrated in FIG. 9 or dedicated programmable interconnection (DPI) integrated-circuit (IC) chip 410 as illustrated in FIG. 10, (3) a processing and/or computing integrated-circuit (IC) chip, such as graphic-processing-unit (GPU) integrated-circuit (IC) chip, central-processing-unit (CPU) integrated-circuit (IC) chip, tensor-processing-unit (TPU) integrated-circuit (IC) chip, network-processing-unit (NPU) integrated-circuit (IC) chip, application-processing-unit (APU) integrated-circuit (IC) chip, digital-signal-processing (DSP) integrated-circuit (IC) chip, (4) a memory integrated-circuit (IC) chip, such as non-volatile NAND chip, non-volatile NOR flash chip, non-volatile magnetoresistive random-access-memory (MRAM) integrated-circuit (IC) chip, non-volatile resistive random access memory (RRAM) integrated-circuit (IC) chip, non-volatile phase-change random-access-memory (PCM) integrated-circuit (IC) chip, non-volatile ferroelectric-random-access-memory (FRAM) integrated-circuit (IC) chip or high bandwidth dynamic random-access-memory (DRAM) or static random-access-memory (SRAM) memory (HBM) chip, (5) an auxiliary and supporting (AS) integrated-circuit (IC) chip 411 as illustrated in FIG. 11, (6) an IAC IC chip 402 as illustrated in FIG. 12A, (7) a dedicated I/O chip 265 or dedicated control and I/O chip 260 as illustrated in FIGS. 12A and 12B, or (8) a power management integrated-circuit (IC) chip.

[0334] Next, referring to FIGS. 19A and 19B, each of the first or second type of memory modules 159 and the known-good memory, logic or ASIC chips 121 may have the insulating bonding layer 52 bonded to the insulating bonding layer 52 of the semiconductor wafer 100d and the metal pads 6a each bonded to one of the metal pads 6a of the semiconductor wafer 100d. The process for joining each of the first or second type of memory modules 159 and the known-good memory, logic or ASIC chips 121 with the semiconductor wafer 100d by providing each of the first or second type of memory modules 159 and the known-good memory, logic or ASIC chips 121 with the insulating bonding layer 52 bonded to the insulating bonding layer 52 of the semiconductor wafer 100d and with the metal pads 6a each bonded to one of the metal pads 6a of the semiconductor wafer 100d may be referred to that for joining each of the first or second type of memory modules 159 and the known-good memory, logic or ASIC chips 121 with the semiconductor wafer 100c as illustrated in FIGS. 17A and 17B.

[0335] Next, referring to FIG. 19C, a polymer layer 565, e.g., resin or compound, may be applied to fill a gap between each neighboring two of the first or second type of memory modules 159 and the known-good memory, logic or ASIC chips 121 and to cover a backside of each of the first or second type of memory modules 159 and a backside of each of the known-good memory, logic or ASIC chips 121 by methods, for example, spin-on coating, screen-printing, dispensing or molding. The polymer layer 565 may be, for example, polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer, or silicone. The polymer layer 565 may be, for example, photosensitive polyimide/PBO PIMEL™ supplied by Asahi Kasei Corporation, Japan, or epoxy-based molding compounds, resins or sealants provided by Nagase ChemteX Corporation, Japan. The polymer layer 565 may be cured or cross-linked at a temperature higher than or equal to 50, 70, 90, 100, 125, 150, 175, 200, 225, 250, 275 or 300 degrees Celsius.

[0336] Next, referring to FIG. 19D, a chemical mechanical polishing (CMP), polishing or grinding process may be applied to remove a top portion of the polymer layer 565 to planarize a top surface of the polymer layer 565, a top surface of each of the first or second type of memory modules 159 and a top surface of each of the known-good memory, logic or ASIC chips 121 and to expose a backside of the topmost one of the memory chips 251 of each of the first or second type of memory modules 159 and a backside of each of the known-good memory, logic or ASIC chips 121.

[0337] Next, referring to FIG. 19E, a chemical mechanical polishing (CMP), polishing or grinding process may be applied to remove a bottom portion of the semiconductor substrate 2 of the semiconductor wafer 100d and to expose a backside of the copper layer 156 of each of the through silicon vias (TSVs) 157 of the semiconductor wafer 100d. For each of the through silicon vias (TSVs) 157 of the semiconductor wafer 100d, its insulating lining layer 153, adhesion layer 154 and seed layer 155 at its backside may be removed to expose a backside of its copper layer 156, which may be coplanar with a backside of the semiconductor substrate 2 of the semiconductor wafer 100d, and its insulating lining layer 153, adhesion layer 154 and seed layer 155 at a sidewall of its copper layer 156 may be left.

[0338] Next, referring to FIG. 19F, an insulating dielectric layer 93 may be formed on the backside of the semiconductor substrate 2 of the semiconductor wafer 100d. Each opening in the insulating dielectric layer 93 may be vertically under the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of the semiconductor wafer 100d. The insulating dielectric layer 93 may be a layer of polymer, such as polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer or silicone, having a thickness between 3 and 30 micrometers or between 5 and 15 micrometers.

[0339] Next, referring to FIG. 19F, each of the micro-bumps or micro-pads 197, which may be of one of the first through fourth types having the same specifications as the first through fourth types of micro-bumps or micro-pads 197 as illustrated in FIG. 17E respectively, may include the adhesion layer 26a on the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of the semiconductor wafer 100d. Said each micro-bump or micro-pad 197 may be any of the first through fourth types, including (1) the adhesion layer 26a, such as titanium (Ti) or titanium nitride (TiN) layer having a thickness between 1 nm and 50 nm, on the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of the semiconductor wafer 100d.

[0340] Next, the semiconductor wafer 100d and polymer layer 565 may be cut or diced to form multiple first type of operation units 190 each for a first type of chip-on-chip (COC) components or package as shown in FIG. 19G by a laser cutting process or by a mechanical cutting process. At this time, the semiconductor wafer 100d may be cut or diced into multiple semiconductor integrated-circuit (IC) chips 399, each of which may have the same specification as the semiconductor integrated-circuit (IC) chip 100 as illustrated in FIG. 14F and may be (1) an application specific integrated-circuit (ASIC) logic chip, (2) a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip 200 as illustrated in FIG. 9 or dedicated programmable interconnection (DPI) integrated-circuit (IC) chip 410 as illustrated in FIG. 10, (3) a processing and/or computing integrated-circuit (IC) chip, such as graphic-processing-unit (GPU) integrated-circuit (IC) chip, central-processing-unit (CPU) integrated-circuit (IC) chip, tensor-processing-unit (TPU) integrated-circuit (IC) chip, network-processing-unit (NPU) integrated-circuit (IC) chip, application-processing-unit (APU) integrated-circuit (IC) chip, digital-signal-processing (DSP) integrated-circuit (IC) chip, (4) a memory integrated-circuit (IC) chip, such as non-volatile NAND chip, non-volatile NOR flash chip, non-volatile magnetoresistive random-access-memory (MRAM) integrated-circuit (IC) chip, non-volatile resistive random access memory (RRAM) integrated-circuit (IC) chip, non-volatile phase-change random-access-memory (PCM) integrated-circuit (IC) chip, non-volatile ferroelectric-random-access-memory (FRAM) integrated-circuit (IC) chip or high bandwidth dynamic random-access-memory (DRAM) or static random-access-memory (SRAM) memory (HBM) chip, (5) an auxiliary and supporting (AS) integrated-circuit (IC) chip 411 as illustrated in FIG. 11, (6) an IAC IC chip 402 as illustrated in FIG. 12A, (7) a dedicated I/O chip 265 or dedicated control and I/O chip 260 as illustrated in FIGS. 12A and 12B, or (8) a power management integrated-circuit (IC) chip.

[0341] Alternatively, FIG. 19H is a schematically cross-sectional view showing a first type of operation unit in accordance with another embodiment of the present application. For an element indicated by the same reference number shown in FIGS. 19A-19H, the specification of the element as seen in FIG. 19H may be referred to that of the element as illustrated in FIG. 19A-19G. Referring to FIG. 19H, the semiconductor wafer 100d may be provided at an active side thereof with the first, second or fourth type of micro-bumps or micro-pads 34, as illustrated in FIG. 14B, instead of the insulating bonding layer 52 and metal pads 6a. Each of the first or second type of memory modules 159 (only one is shown) formed as illustrated in FIG. 15A or 15B respectively may have the first, second or third type of micro-bumps or micro-pads 34 to be bonded to the first, second or fourth type of micro-bumps or micro-pads 34 preformed at an active side of the semiconductor wafer 100d into multiple bonded metal contacts 563 respectively therebetween, which may have the same specifications or details as those illustrated in FIGS. 17G, 18A and 18B for the first through fourth cases. Each of the known-good memory, logic or ASIC chips 121 (only one is shown) may have the structure as illustrated in FIG. 14B provided at an active side thereof with the first, second or third type of micro-bumps or micro-pads 34 to be bonded to the first, second or fourth type of micro-bumps or micro-pads 34 preformed at an active side of the semiconductor wafer 100d into multiple bonded metal contacts 563 respectively therebetween, which may have the same specifications or details as those illustrated in FIGS. 17G, 18A and 18B for the first through fourth cases.

[0342] Next, referring to FIG. 19H, an underfill 564, such as a layer of polymer or epoxy resins or compounds, may be filled into a gap between each of the first or second type of memory modules 159 and the semiconductor wafer 100d to enclose the bonded metal contacts 563 therebetween and into a gap between each of the known-good memory, logic or ASIC chips 121 and the semiconductor wafer 100c to enclose the bonded metal contacts 563 therebetween. The underfill 564 may be cured at temperature equal to or above 100, 120 or 150 degrees Celsius. The following process may be referred to the process as illustrated in FIGS. 19C-19G.

[0343] FIGS. 20A and 20B are schematically cross-sectional views showing various second type of operation units in accordance with an embodiment of the present application. The second type of operation unit 190 for the second type of chip-on-chip (COC) component or package as seen in FIG. 20A is similar to the first type of operation unit 190 for the second type of chip-on-chip (COC) component or package as illustrated in FIG. 17F, but the difference between the first and second types of operation units 190 for the second type of chip-on-chip (COC) components or packages as seen in FIGS. 17F and 20A is that the second type of operation unit 190 for the second type of chip-on-chip (COC) component or package as seen in FIG. 20A includes (1) an insulating bonding layer 152 on the top surface of the polymer layer 565, the backside of each of the first or second type of memory modules 159, the backside of each of the known-good memory, logic or ASIC chips 121 and the backside of each of the second type of vertical-through-via (VTV) connectors 467 and (2) multiple metal pads 116 each in one of multiple openings in the insulating bonding layer 152 and on the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of the topmost one of the memory chips 251 of one of the first or second type of memory modules 159, the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of one of the known-good memory, logic or ASIC chips 121 or the backside of the copper layer 156 of one of the vertical through vias (VTVs) 358 of one of the second type of vertical-through-via (VTV) connectors 467 for the first and second alternatives, instead of the insulating dielectric layer 93 and the first through fourth types of micro-bumps or micro-pads 197 as illustrated in FIG. 17F. The second type of operation unit 190 for the second type of chip-on-chip (COC) component or package as seen in FIG. 20B is similar to the first type of operation unit 190 for the second type of chip-on-chip (COC) component or package as illustrated in FIG. 17G, but the difference between the first and second types of operation units 190 for the second type of chip-on-chip (COC) components or packages as seen in FIGS. 17G and 20B is that the second type of operation unit 190 for the second type of chip-on-chip (COC) component or package as seen in FIG. 20B includes (1) an insulating bonding layer 152 on the top surface of the polymer layer 565 and (2) multiple metal pads 116 each in one of multiple openings in the insulating bonding layer 152 and on the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of the topmost one of the memory chips 251 of one of the first or second type of memory modules 159, the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of one of the known-good memory, logic or ASIC chips 121, the backside of the copper layer 156 of one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 for the first and second alternatives, the backside of the copper post 706 of one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 for the third and fourth alternatives or the backside of the metal pad 336 or copper post 318 of one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 for the fifth alternative, instead of the insulating dielectric layer 93 and the first through fourth types of micro-bumps or micro-pads 197 as illustrated in FIG. 17G.

[0344] For each of the second type of operation units 190 for the second type of chip-on-chip (COC) components or packages as seen in FIGS. 20A and 20B, its insulating bonding layer 152 may be a silicon-oxide layer having a thickness between 0.1 and 2 μm. Each of its metal pads 116 may include (1) a copper layer 24 having a thickness of between 3 nm and 500 nm in one of the openings in its insulating bonding layer 152, (2) an adhesion layer 18, such as titanium or titanium nitride having a thickness of between 1 nm and 50 nm, at a bottom and sidewall of the copper layer 24 of said each of its metal pads 116 and (3) a seed layer 22, such as copper, between the copper layer 24 and adhesion layer 18 of said each of its metal pads 116, wherein the copper layer 24 of said each of its metal pads 116 may have a top surface substantially coplanar with a top surface of the silicon-oxide layer of its insulating bonding layer 152.

[0345] FIGS. 21A and 21B are schematically cross-sectional views showing various second type of operation units in accordance with another embodiment of the present application. The second type of operation unit 190 for the first type of chip-on-chip (COC) component or package as seen in FIG. 21A is similar to the first type of operation unit 190 for the first type of chip-on-chip (COC) component or package as illustrated in FIG. 19G, but the difference between the first and second types of operation units 190 for the first type of chip-on-chip (COC) components or packages as seen in FIGS. 19G and 21A is that the second type of operation unit 190 for the first type of chip-on-chip (COC) component or package as seen in FIG. 21A includes (1) an insulating bonding layer 152 on the backside of the semiconductor substrate 2 of its semiconductor integrated-circuit (IC) chip 399 and (2) multiple metal pads 116 each in one of multiple openings in the insulating bonding layer 152 and on the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of its semiconductor integrated-circuit (IC) chip 399. The second type of operation unit 190 for the first type of chip-on-chip (COC) component or package as seen in FIG. 21B is similar to the first type of operation unit 190 for the first type of chip-on-chip (COC) component or package as illustrated in FIG. 19H, but the difference between the first and second types of operation units 190 for the first type of chip-on-chip (COC) components or packages as seen in FIGS. 19H and 21B is that the second type of operation unit 190 for the first type of chip-on-chip (COC) component or package as seen in FIG. 21B includes (1) an insulating bonding layer 152 on the backside of the semiconductor substrate 2 of its semiconductor integrated-circuit (IC) chip 399 and (2) multiple metal pads 116 each in one of multiple openings in the insulating bonding layer 152 and on the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of its semiconductor integrated-circuit (IC) chip 399.

[0346] For each of the second type of operation units 190 for the first type of chip-on-chip (COC) components or packages as seen in FIGS. 21A and 21B, its insulating bonding layer 152 may be a silicon-oxide layer having a thickness between 0.1 and 2 μm. Each of its metal pads 116 may include (1) a copper layer 24 having a thickness of between 3 nm and 500 nm in one of the openings in its insulating bonding layer 152, (2) an adhesion layer 18, such as titanium or titanium nitride having a thickness of between 1 nm and 50 nm, at a top and sidewall of the copper layer 24 of said each of its metal pads 116 and (3) a seed layer 22, such as copper, between the copper layer 24 and adhesion layer 18 of said each of its metal pads 116, wherein the copper layer 24 of said each of its metal pads 116 may have a bottom surface substantially coplanar with a bottom surface of the silicon-oxide layer of its insulating bonding layer 152.

[0347] For each of the first and second type of operation units 190 for the second type of chip-on-chip (COC) components or packages as seen in FIGS. 17F and 20A, its semiconductor integrated-circuit (IC) chip 399 may have the semiconductor devices 4 such as transistors at the active surface of the semiconductor substrate 2 thereof as illustrated in FIG. 14D, and the active surface of the semiconductor substrate 2 of its semiconductor integrated-circuit (IC) chip 399 may face an active surface of the semiconductor substrate 2 of each of its known-good memory, logic ASIC chips 121, wherein said each of its known-good memory, logic or ASIC chips 121 may have the semiconductor devices 4 such as transistors at the active surface of the semiconductor substrate 2 thereof as illustrated in FIG. 14E. For each of the first and second type of operation units 190 for the second type of chip-on-chip (COC) components or packages as seen in FIGS. 17G and 20B, its semiconductor integrated-circuit (IC) chip 399 may have the semiconductor devices 4 such as transistors at the active surface of the semiconductor substrate 2 thereof as illustrated in FIG. 14A or 14B, and the active surface of the semiconductor substrate 2 of its semiconductor integrated-circuit (IC) chip 399 may face an active surface of the semiconductor substrate 2 of each of its known-good memory, logic ASIC chips 121, wherein said each of its known-good memory, logic or ASIC chips 121 may have the semiconductor devices 4 such as transistors at the active surface of the semiconductor substrate 2 thereof as illustrated in FIG. 14B. For each of the first and second type of operation units 190 for the first type of chip-on-chip (COC) components or packages as seen in FIGS. 19G and 21A, its semiconductor integrated-circuit (IC) chip 399 may have the semiconductor devices 4 such as transistors at the active surface of the semiconductor substrate 2 thereof as illustrated in FIG. 14E, and the active surface of the semiconductor substrate 2 of its semiconductor integrated-circuit (IC) chip 399 may face an active surface of the semiconductor substrate 2 of each of its known-good memory, logic ASIC chips 121, wherein said each of its known-good memory, logic or ASIC chips 121 may have the semiconductor devices 4 such as transistors at the active surface of the semiconductor substrate 2 thereof as illustrated in FIG. 14D. For each of the first and second type of operation units 190 for the first type of chip-on-chip (COC) components or packages as seen in FIGS. 19H and 21B, its semiconductor integrated-circuit (IC) chip 399 may have the semiconductor devices 4 such as transistors at the active surface of the semiconductor substrate 2 thereof as illustrated in FIG. 14B, and the active surface of the semiconductor substrate 2 of its semiconductor integrated-circuit (IC) chip 399 may face an active surface of the semiconductor substrate 2 of each of its known-good memory, logic ASIC chips 121, wherein said each of its known-good memory, logic or ASIC chips 121 may have the semiconductor devices 4 such as transistors at the active surface of the semiconductor substrate 2 thereof as illustrated in FIG. 14A or 14B. For each of the first and second type of operation units 190 for the first and second types of chip-on-chip (COC) components or packages as seen in FIGS. 17F, 17G, 19G, 19H, 20A, 20B, 21A and 21B, the active surface of the semiconductor substrate 2 of its semiconductor integrated-circuit (IC) chip 399 may face each of its first or second type of memory modules 159. For each of the first and second types of operation units 190 for the first types of chip-on-chip (COC) components or packages as seen in FIGS. 17F and 20A, the active surface of the semiconductor substrate 2 of its semiconductor integrated-circuit (IC) chip 399 may face each of its second type of vertical-through-via (VTV) connectors 467. For each of the first and second types of operation units 190 for the first types of chip-on-chip (COC) components or packages as seen in FIGS. 17G and 20B, the active surface of the semiconductor substrate 2 of its semiconductor integrated-circuit (IC) chip 399 may face each of its first type of vertical-through-via (VTV) connectors 467.

[0348] For each of the first and second type of operation units 190 for the first and second types of chip-on-chip (COC) components or packages as seen in FIGS. 17F, 17G, 19G, 19H, 20A, 20B, 21A and 21B, the control chip 688 of each of its first or second type of memory modules 159 may have multiple small I/O circuits coupling respectively to multiple small I/O circuits of its semiconductor integrated-circuit (IC) chip 399 through the bonded metal pads 6a of the control chip 688 of said each of its second type of memory modules 159 and the bonded metal pads 6a of its semiconductor integrated-circuit (IC) chip 399 as seen in FIG. 17F, 19G, 20A or 21A or through its bonded metal contacts 563 therebetween as seen in FIG. 17G, 19H, 20B or 21B for data transmission therebetween with a data bit width of equal to or greater than 64, 128, 256, 512, 1024, 2048, 4096, 8K, or 16K, wherein each of the small I/O circuits of the control chip 688 of said each of its first or second type of memory modules 159 may have an output capacitance or driving capability or loading, for example, between 0.05 pF and 2 pF or between 0.05 pF and 1 pF, or smaller than 2 pF or 1 pF, and an input capacitance between 0.15 pF and 4 pF or between 0.15 pF and 2 pF, or greater than 0.15 pF; alternatively each of the small input/output (I/O) circuits of the control chip 688 of said each of its first or second type of memory modules 159 may have an I/O power efficiency smaller than 0.5 pico-Joules per bit, per switch or per voltage swing, or between 0.01 and 0.5 pico-Joules per bit, per switch or per voltage swing. Each of its known-good memory, logic or ASIC chips 121 may have multiple small I/O circuits coupling respectively to multiple small I/O circuits of its semiconductor integrated-circuit (IC) chip 399 through the bonded metal pads 6a of said each of its known-good memory, logic or ASIC chips 121 and the bonded metal pads 6a of its semiconductor integrated-circuit (IC) chip 399 as seen in FIG. 17F, 19G, 20A or 21A or through its bonded metal contacts 563 therebetween as seen in FIG. 17G, 19H, 20B or 21B for data transmission therebetween with a data bit width of equal to or greater than 64, 128, 256, 512, 1024, 2048, 4096, 8K, or 16K, wherein each of the small I/O circuits of said each of its known-good memory, logic or ASIC chips 121 may have an output capacitance or driving capability or loading, for example, between 0.05 pF and 2 pF or between 0.05 pF and 1 pF, or smaller than 2 pF or 1 pF, and an input capacitance between 0.15 pF and 4 pF or between 0.15 pF and 2 pF, or greater than 0.15 pF; alternatively each of the small input/output (I/O) circuits of said each of its known-good memory, logic or ASIC chips 121 may have an I/O power efficiency smaller than 0.5 pico-Joules per bit, per switch or per voltage swing, or between 0.01 and 0.5 pico-Joules per bit, per switch or per voltage swing. Each of the small I/O circuits of its semiconductor integrated-circuit (IC) chip 399 may have an output capacitance or driving capability or loading, for example, between 0.05 pF and 2 pF or between 0.05 pF and 1 pF, or smaller than 2 pF or 1 pF, and an input capacitance between 0.15 pF and 4 pF or between 0.15 pF and 2 pF, or greater than 0.15 pF; alternatively each of the small input/output (I/O) circuits of its semiconductor integrated-circuit (IC) chip 399 may have an I/O power efficiency smaller than 0.5 pico-Joules per bit, per switch or per voltage swing, or between 0.01 and 0.5 pico-Joules per bit, per switch or per voltage swing.

[0349] Further, for each of the first and second type of operation units 190 for the first and second types of chip-on-chip (COC) components or packages as seen in FIGS. 17F, 17G, 19G, 19H, 20A, 20B, 21A and 21B, the control chip 688 of one of its first or second type of memory modules 159 or one of its known-good memory, logic or ASIC chips 121 may include multiple non-volatile memory cells configured to store a password or key and a cryptography block or circuit configured (1) to encrypt, in accordance with the password or key, CPM data from the memory cells 490 for the look-up tables (LUT) 210 of the programmable logic cells (LC) 2014 of its semiconductor integrated-circuit (IC) chip 399 or the memory cells 362 of the programmable switch cells 379 of its semiconductor integrated-circuit (IC) chip 399 as encrypted CPM data to be passed to its micro-bumps or micro-pads 197 as seen in FIG. 17F, 17G, 19G or 19H or to its metal pads 116 as seen in FIG. 20A, 20B, 21A or 21B, and (2) to decrypt, in accordance with the password or key, encrypted CPM data from its micro-bumps or micro-pads 197 as seen in FIG. 17F, 17G, 19G or 19H or from its metal pads 116 as seen in FIG. 20A, 20B, 21A or 21B as decrypted CPM data to be passed to the memory cells 490 for the look-up tables (LUT) 210 of the programmable logic cells (LC) 2014 of its semiconductor integrated-circuit (IC) chip 399 or the memory cells 362 of the programmable switch cells 379 of its semiconductor integrated-circuit (IC) chip 399. Further, one of its known-good memory, logic or ASIC chips 121 may include a regulating block configured to regulate a voltage of power supply from an input voltage of 12, 5, 3.3 or 2.5 volts to an output voltage of 3.3, 2.5, 1.8, 1.5, 1.35, 1.2, 1.0, 0.75 or 0.5 volts to be delivered to its semiconductor integrated-circuit (IC) chip 399. Further, one of its known-good memory, logic or ASIC chips 121 may include multiple non-volatile memory cells, such as NAND memory cells, NOR memory cells, RARM cells, MRAM cells, FRAM cells or PCM cells, configured to store CPM data to be passed to the memory cells 490 for the look-up tables (LUT) 210 of the programmable logic cells (LC) 2014 of its semiconductor integrated-circuit (IC) chip 399 for programming or configuring the programmable logic cells (LC) 2014 of its semiconductor integrated-circuit (IC) chip 399 or to the memory cells 362 of the programmable switch cells 379 of its semiconductor integrated-circuit (IC) chip 399 for programming or configuring the programmable switch cells 379 of its semiconductor integrated-circuit (IC) chip 399.

[0350] Further, for each of the first and second type of operation units 190 for the second type of chip-on-chip (COC) components or packages as seen in FIGS. 17F, 17G, 20A and 20B, its semiconductor integrated-circuit (IC) chip 399 may have a large input/output (I/O) circuit coupling to one of its micro-bumps or micro-pads 197 as seen in FIG. 17F or 17G or one of its metal pads 116 as seen in FIG. 20A or 20B for signal or clock transmission or power supply (Vcc) or ground reference (Vss) delivery through one of the dedicated vertical bypasses 698 in one of its second type of memory module 159 as illustrated in FIGS. 15B and 15D, one of the through silicon vias (TSVs) 157 of one of its known-good memory, logic ASIC chips 121 or one of the vertical through vias (VTVs) 358 of one of its first or second type of vertical-through-via (VTV) connectors 467, wherein said one of the dedicated vertical bypasses 698 is not connected to any transistor in the memory chips 251 and control chip 688 of said one of its second type of memory module 159 and said one of the through silicon vias (TSVs) 157 may not be connected to any transistor in said one of its known-good memory, logic or ASIC chips 121, wherein the large input/output (I/O) circuit may have an output capacitance or driving capability or loading between 2 pF and 100 pF, between 2 pF and 50 pF, between 2 pF and 30 pF, between 2 pF and 20 pF, between 2 pF and 15 pF, between 2 pF and 10 pF, or between 2 pF and 5 pF, or greater than 2 pF, 5 pF, 10 pF, 15 pF or 20 pF, and an input capacitance between 0.15 pF and 4 pF or between 0.15 pF and 2 pF, or greater than 0.15 pF for example; alternatively, the large input/output (I/O) circuit may have an I/O power efficiency greater than 3, 5 or 10 pico-Joules per bit, per switch or per voltage swing. One of the vertical interconnects 699 of its first or second type of memory module 159 as illustrated in FIGS. 15A-15D may couple to one of its micro-bumps or micro-pads 197 as seen in FIG. 17F or 17G or to one of its metal pads 116 as seen in FIG. 20A or 20B and couple to its semiconductor integrated-circuit (IC) chip 399 through one of the metal pads 6a of the control chip 688 of its first or second type of memory module 159 as seen in FIG. 17F or 20A or through one of its bonded metal contacts 563 as seen in FIG. 17G or 20B.

[0351] Further, for each of the first and second type of operation units 190 for the first type of chip-on-chip (COC) components or packages as seen in FIGS. 19G, 19H, 21A and 21B, its semiconductor integrated-circuit (IC) chip 399 may have a large input/output (I/O) circuit coupling to one of its micro-bumps or micro-pads 197 as seen in FIG. 19G or 19H or one of its metal pads 116 as seen in FIG. 21A or 21B for signal or clock transmission or power supply (Vcc) or ground reference (Vss) delivery through one of the through silicon vias (TSVs) 157 of its semiconductor integrated-circuit (IC) chip 399, wherein the large input/output (I/O) circuit may have an output capacitance or driving capability or loading between 2 pF and 100 pF, between 2 pF and 50 pF, between 2 pF and 30 pF, between 2 pF and 20 pF, between 2 pF and 15 pF, between 2 pF and 10 pF, or between 2 pF and 5 pF, or greater than 2 pF, 5 pF, 10 pF, 15 pF or 20 pF, and an input capacitance between 0.15 pF and 4 pF or between 0.15 pF and 2 pF, or greater than 0.15 pF for example; alternatively, the large input/output (I/O) circuit may have an I/O power efficiency greater than 3, 5 or 10 pico-Joules per bit, per switch or per voltage swing.

[0352] Further, for each of the first and second type of operation units 190 for the first and second types of chip-on-chip (COC) components or packages as seen in FIGS. 17F, 17G, 19G, 19H, 20A, 20B, 21A and 21B, each of the memory chips 251 and control chip 688 of each of its first or second type of memory modules 159 and each of its known-good memory, logic or ASIC chips 121 may be implemented using a semiconductor note or generation less advanced than or equal to, or above or equal to 20 nm, 30 nm, 40 nm, 50 nm, 90 nm, 130 nm, 250 nm, 350 nm or 500 nm. The semiconductor technology node or generation used in each of the memory chips 251 and control chip 688 of each of its first or second type of memory modules 159 and each of its known-good memory, logic or ASIC chips 121 may be 1, 2, 3, 4, 5 or greater than 5 nodes or generations older, more matured or less advanced than that used in its semiconductor integrated-circuit (IC) chip 399. Transistors used in each of the memory chips 251 and control chip 688 of each of its first or second type of memory modules 159 and each of its known-good memory, logic or ASIC chips may be provided with fully depleted silicon-on-insulator (FDSOI) metal-oxide-semiconductor field effect transistors (MOSFETs), partially depleted silicon-on-insulator (PDSOI) MOSFETs or a planar MOSFETs. Transistors used in each of the memory chips 251 and control chip 688 of each of its first or second type of memory modules 159 and each of its known-good memory, logic or ASIC chips 121 may be different from those used in its semiconductor integrated-circuit (IC) chip 399; each of the memory chips 251 and control chip 688 of each of its first or second type of memory modules 159 and each of its known-good memory, logic or ASIC chips 121 may use planar MOSFETs, while its semiconductor integrated-circuit (IC) chip 399 may use fin field effect transistors (FINFETs) or gate-all-around field effect transistors (GAAFETs). A power supply voltage (Vcc) applied in each of the memory chips 251 and control chip 688 of each of its first or second type of memory modules 159 and each of its known-good memory, logic or ASIC chips 121 may be greater than or equal to 1.5, 2.0, 2.5, 3, 3.3, 4, or 5 voltages, while a power supply voltage (Vcc) applied in its semiconductor integrated-circuit (IC) chip 399 may be smaller than or equal to 1.8, 1.5 or 1 voltage. The power supply voltage applied in each of the memory chips 251 and control chip 688 of each of its first or second type of memory modules 159 and each of its known-good memory, logic or ASIC chips 121 may be higher than that applied in its semiconductor integrated-circuit (IC) chip 399. A gate oxide of a field effect transistor (FET) of each of the memory chips 251 and control chip 688 of each of its first or second type of memory modules 159 and a gate oxide of a field effect transistor (FET) of each of its known-good memory, logic or ASIC chips 121 may have a physical thickness greater than or equal to 5 nm, 6 nm, 7.5 nm, 10 nm, 12.5 nm, or 15 nm, while a gate oxide of a field effect transistor (FET) of its semiconductor integrated-circuit (IC) chip 399 may have a physical thickness less than 4.5 nm, 4 nm, 3 nm or 2 nm. The thickness of the gate oxide of the field effect transistor (FET) of each of the memory chips 251 and control chip 688 of each of its first or second type of memory module 159 and the thickness of the gate oxide of the field effect transistor (FET) of each of its known-good memory, logic or ASIC chips 121 may be greater than that of its semiconductor integrated-circuit (IC) chip 399.

[0353] FIGS. 22A-22H are schematically cross-sectional views showing a process for forming a first type of multichip package in accordance with a first embodiment of the present application. Referring to FIG. 22A, a temporary substrate 590 may be provided with a glass or silicon substrate 589 and a sacrificial bonding layer 591 formed on the glass or silicon substrate 589. The sacrificial bonding layer 591 may have the glass or silicon substrate 589 to be easily debonded or released from a structure subsequently formed on the sacrificial bonding layer 591. For example, the sacrificial bonding layer 591 may be a material of light-to-heat conversion (LTHC) that may be deposited on the glass or silicon substrate 589 by printing or spin-on coating and then cured or dried with a thickness of about 1 micrometer or between 0.5 and 2 micrometers. The LTHC material may be a liquid ink containing carbon black and binder in a mixture of solvents.

[0354] Next, referring to FIG. 22A, multiple semiconductor integrated-circuit (IC) chips 100, each of which may be (1) an application specific integrated-circuit (ASIC) logic chip, (2) a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip 200 as illustrated in FIG. 9 or dedicated programmable interconnection (DPI) integrated-circuit (IC) chip 410 as illustrated in FIG. 10, (3) a processing and/or computing integrated-circuit (IC) chip, such as graphic-processing-unit (GPU) integrated-circuit (IC) chip, central-processing-unit (CPU) integrated-circuit (IC) chip, tensor-processing-unit (TPU) integrated-circuit (IC) chip, network-processing-unit (NPU) integrated-circuit (IC) chip, application-processing-unit (APU) integrated-circuit (IC) chip, digital-signal-processing (DSP) integrated-circuit (IC) chip, (4) a memory integrated-circuit (IC) chip, such as non-volatile NAND chip, non-volatile NOR flash chip, non-volatile magnetoresistive random-access-memory (MRAM) integrated-circuit (IC) chip, non-volatile resistive random access memory (RRAM) integrated-circuit (IC) chip, non-volatile phase-change random-access-memory (PCM) integrated-circuit (IC) chip, non-volatile ferroelectric-random-access-memory (FRAM) integrated-circuit (IC) chip or high bandwidth dynamic random-access-memory (DRAM) or static random-access-memory (SRAM) memory (HBM) chip, (5) an auxiliary and supporting (AS) integrated-circuit (IC) chip 411 as illustrated in FIG. 11, (6) an IAC IC chip 402 as illustrated in FIG. 12A, (7) a dedicated I/O chip 265 or dedicated control and I/O chip 260 as illustrated in FIGS. 12A and 12B, or (8) a power management integrated-circuit (IC) chip, each may have the same specification as illustrated in FIG. 14A or 14B, provided with the first type of micro-bumps or micro-pads 34. Each of the semiconductor integrated-circuit (IC) chips 100 may further include an insulating dielectric layer 257, such as polymer layer, over its first and/or second interconnection scheme(s) 560 and/or 588, covering a top surface and sidewall of the copper layer 32 of each of its first type of micro-bumps or micro-pads 34, wherein the insulating dielectric layer 257 may be, for example, polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer, or silicone; the insulating dielectric layer 257 may be, for example, photosensitive polyimide/PBO PIMEL™ supplied by Asahi Kasei Corporation, Japan, or epoxy-based molding compounds, resins or sealants provided by Nagase ChemteX Corporation, Japan. Each of the semiconductor integrated-circuit (IC) chips 100 may have a backside attached to the sacrificial bonding layer 591 of the temporary substrate 590.

[0355] Further, referring to FIG. 22A, multiple first type of operation units 190, each of which may have the same specification as illustrated in FIG. 17F, 17G, 19G or 19H, each may be provided with the first type of micro-bumps or micro-pads 197. Each of the semiconductor integrated-circuit (IC) chips 100 may further include an insulating dielectric layer 257, such as polymer layer, on its insulating dielectric layer 93, covering a top surface and sidewall of the copper layer 32 of its first type of micro-bumps or micro-pads 197, wherein the insulating dielectric layer 257 may be, for example, polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer, or silicone; the insulating dielectric layer 257 may be, for example, photosensitive polyimide/PBO PIMEL™ supplied by Asahi Kasei Corporation, Japan, or epoxy-based molding compounds, resins or sealants provided by Nagase ChemteX Corporation, Japan. Each of the first type of operation units 190 may have a backside attached to the sacrificial bonding layer 591 of the temporary substrate 590.

[0356] Further, referring to FIG. 22A, multiple first type of vertical-through-via (VTV) connectors 467, each of which may have the same specification as illustrated in FIG. 1A, 1C, 1E, 2A, 2C or 2E, each may be provided with the first type of micro-bumps or micro-pads 34. Alternatively, each of the first type of vertical-through-via (VTV) connectors 467 may have the same specification as illustrated in FIG. 4A, 4B, 4C, 5A, 5B or 5C, but its fifth type of micro-bumps or micro-pads 34 is replaced with the first type of micro-bumps or micro-pads 34 as illustrated in FIG. 1A. Alternatively, each of the first type of vertical-through-via (VTV) connectors 467 may have the same specification as illustrated in FIG. 6, but its sixth type of micro-bumps or micro-pads 34 is replaced with the first type of micro-bumps or micro-pads 34 as illustrated in FIG. 1A. Each of the first type of vertical-through-via (VTV) connectors 467 may further include an insulating dielectric layer 257, such as polymer, at a top thereof, covering a top surface and sidewall of the copper layer 32 of its first type of micro-bumps or micro-pads 34, wherein the insulating dielectric layer 257 may be, for example, polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer, or silicone; the insulating dielectric layer 257 may be, for example, photosensitive polyimide/PBO PIMEL™ supplied by Asahi Kasei Corporation, Japan, or epoxy-based molding compounds, resins or sealants provided by Nagase ChemteX Corporation, Japan. Each of the first type of vertical-through-via (VTV) connectors 467 may have a backside attached to the sacrificial bonding layer 591 of the temporary substrate 590.

[0357] Next, referring to FIG. 22A, a polymer layer 92, e.g., resin or compound, may be applied to fill a gap between each neighboring two of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 and to cover the insulating dielectric layer 257 of each of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 by methods, for example, spin-on coating, screen-printing, dispensing or molding. The polymer layer 92 may be, for example, polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer, or silicone. The polymer layer 92 may be, for example, photosensitive polyimide/PBO PIMEL™ supplied by Asahi Kasei Corporation, Japan, or epoxy-based molding compounds, resins or sealants provided by Nagase ChemteX Corporation, Japan. The polymer layer 92 may be cured or cross-linked at a temperature higher than or equal to 50, 70, 90, 100, 125, 150, 175, 200, 225, 250, 275 or 300 degrees Celsius.

[0358] Next, referring to FIG. 22C, a chemical mechanical polishing (CMP), polishing or grinding process may be applied to remove a top portion of the polymer layer 92 and a top portion of the insulating dielectric layer 257 each of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 and to planarize a top surface of the polymer layer 92, a top surface of the copper layer 32 of each of the first type of micro-bumps or micro-pads 34 of each of the semiconductor integrated-circuit (IC) chips 100, a top surface of the copper layer 32 of each of the first type of micro-bumps or micro-pads 197 of each of the first type of operation units 190 and a top surface of the copper layer 32 of each of the first type of micro-bumps or micro-pads 34 of each of the first type of vertical-through-via (VTV) connectors 467. Thereby, the top surface of the copper layer 32 of each of the first type of micro-bumps or micro-pads 34 of each of the semiconductor integrated-circuit (IC) chips 100, the top surface of the copper layer 32 of each of the first type of micro-bumps or micro-pads 197 of each of the first type of operation units 190 and the top surface of the copper layer 32 of each of the first type of micro-bumps or micro-pads 34 of each of the first type of vertical-through-via (VTV) connectors 467 may be exposed.

[0359] Referring to FIG. 22D, a frontside interconnection scheme for a logic drive or device (FISD) 101 may be formed on the polymer layer 92 and over the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467. The frontside interconnection scheme for a logic drive or device (FISD) 101 may include one or more interconnection metal layers 27 coupling to the first type of micro-bumps or micro-pads 34 of each of the semiconductor integrated-circuit (IC) chips 100, the first type of micro-bumps or micro-pads 197 of each of the first type of operation units 190 and the first type of micro-bumps or micro-pads 34 of each of the first type of vertical-through-via (VTV) connectors 467, and one or more polymer layers 42, i.e., insulating dielectric layers, each between neighboring two of its interconnection metal layers 27, between a bottommost one of its interconnection metal layers 27 and a polished planar surface composed of the top surface of the polymer layer 92, the top surface of the copper layer 32 of each of the first type of micro-bumps or micro-pads 34 of each of the semiconductor integrated-circuit (IC) chips 100, the top surface of the copper layer 32 of each of the first type of micro-bumps or micro-pads 197 of each of the first type of operation units 190 and the top surface of the copper layer 32 of each of the first type of micro-bumps or micro-pads 34 of each of the first type of vertical-through-via (VTV) connectors 467, or on and above a topmost one of its interconnection metal layers 27, wherein the topmost one of its interconnection metal layers 27 may have multiple metal pads at bottoms of multiple openings 42a in the topmost one of its polymer layers 42. Each of the interconnection metal layers 27 may include (1) a copper layer 40 having lower portions in openings in one of the polymer layers 42 having a thickness of between 0.3 μm and 20 μm and upper portions having a thickness 0.3 μm and 20 μm over said one of the polymer layers 42, (2) an adhesion layer 28a, such as titanium or titanium nitride having a thickness of between 1 nm and 50 nm, at a bottom and sidewall of each of the lower portions of the copper layer 40 and at a bottom of each of the upper portions of the copper layer 40, and (3) a seed layer 28b, such as copper, between the copper layer 40 and the adhesion layer 28a, wherein said each of the upper portions of the copper layer 40 may have a sidewall not covered by the adhesion layer 28a. For the frontside interconnection scheme for a logic drive or device (FISD) 101, each of its interconnection metal layers 27 may have a metal line or trace with a thickness between, for example, 0.3 μm and 40 μm, 0.5 μm and 30 μm, 1 μm and 20 μm, 1 μm and 15 μm, 1 μm and 10 μm, or 0.5 μm to 5 μm, or greater than or equal to 0.3 μm, 0.7 μm, 1 μm, 2 μm, 3 μm, 5 μm, 7 μm or 10 μm and a width between, for example, 0.3 μm and 40 μm, 0.5 μm and 30 μm, 1 μm and 20 μm, 1 μm and 15 μm, 1 μm and 10 μm, or 0.5 μm to 5 μm, or greater than or equal to 0.3 μm, 0.7 μm, 1 μm, 2 μm, 3 μm, 5 μm, 7 μm or 10 μm. Each of its polymer layer 42 may be a layer of polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer or silicone, having a thickness between, for example, 0.3 μm and 50 μm, 0.3 μm and 30 μm, 0.5 μm and 20 μm, 1 μm and 10 μm, or 0.5 μm and 5 μm, or thicker than or equal to 0.3 μm, 0.5 μm, 0.7 μm, 1 μm, 1.5 μm, 2 μm, 3 μm or 5 μm. One of its interconnection metal layers 27 may have two planes used respectively for power and ground planes of a power supply and/or used as a heat dissipater or spreader for the heat dissipation or spreading, wherein each of the two planes may have a thickness, for example, between 5 μm and 50 μm, 5 μm and 30 μm, 5 μm and 20 μm, or 5 μm and 15 μm, or greater than or equal to 5 μm, 10 μm, 20 μm, or 30 μm. The two planes may be layout as interlaced or interleaved shaped structures in a plane or may be layout in a fork shape. For the frontside interconnection scheme for a logic drive or device (FISD) 101, each of its interconnection metal layers 27 may extend horizontally across an edge of each of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467. The topmost one of its interconnection metal layers 27 may be patterned with multiple metal pads at bottoms of multiple respective openings in the topmost one of its polymer layers 42.

[0360] Next, the glass or silicon substrate 589 as seen in FIG. 22D may be released from the sacrificial bonding layer 591. For example, in the case that the sacrificial bonding layer 591 is the material of light-to-heat conversion (LTHC) and the substrate 589 is made of glass, a laser light, such as YAG laser having a wavelength of about 1064 nm, an output power between 20 and 50 W and a spot size of 0.3 mm in diameter at a focal point, may be generated to pass from the backside of the glass substrate 589 to the sacrificial bonding layer 591 through the glass substrate 589 to scan the sacrificial bonding layer 591 at a speed of 8.0 m/s, for example, such that the sacrificial bonding layer 591 may be decomposed and thus the glass substrate 589 may be easily released from the sacrificial bonding layer 591. Next, an adhesive peeling tape (not shown) may be attached to a bottom surface of the remainder of the sacrificial bonding layer 591. Next, the adhesive peeling tape may be peeled off to pull the remainder of the sacrificial bonding layer 591 attached to the adhesive peeling tape off such that the backside of each of the semiconductor integrated-circuit (IC) chips 100, the backside of each of the first type of operation units 190, the backside of each of the first type of vertical-through-via (VTV) connectors 467 and a bottom surface of the polymer layer 92 may be exposed as seen in FIG. 22E.

[0361] Next, referring to FIG. 22F, a chemical mechanical polishing (CMP), polishing or grinding process may be applied to remove a bottom portion of the polymer layer 92, a bottom portion of each of the semiconductor integrated-circuit (IC) chips 100, a bottom portion of each of the first type of operation units 190 and a bottom portion of each of the first type of vertical-through-via (VTV) connectors 467 and to expose a backside of each of the vertical through vias (VTVs) 358 of each of the first type of vertical-through-via (VTV) connectors 467. For each of the vertical through vias (VTVs) 358 of said each of the first type of vertical-through-via (VTV) connectors 467, if made of one or more of the through silicon vias (TSVs) 157 as illustrated in one of FIGS. 1A, 1C, 1E, 2A, 2C and 2F, its insulating lining layer 153, adhesion layer 154 and seed layer 155 at its backside may be removed to expose a backside of its copper layer 156, which is coplanar with a backside of said each of the first type of vertical-through-via (VTV) connectors 467 and a bottom surface of the polymer layer 92, and its insulating lining layer 153, adhesion layer 154 and seed layer 155 at a sidewall of its copper layer 156 may be left. For each of the vertical through vias (VTVs) 358 of said each of the first type of vertical-through-via (VTV) connectors 467, if made of one or more of the through glass vias (TGVs) 259 as illustrated in one of FIGS. 4A, 4B, 4C, 5A, 5B and 5C, a backside of its copper post 706 may be exposed with being coplanar with a backside of said each of the first type of vertical-through-via (VTV) connectors 467 and the bottom surface of the polymer layer 92; for each of the vertical through vias (VTVs) 358 of said each of the first type of vertical-through-via (VTV) connectors 467, if made of one or more of the through polymer vias (TPVs) 318 as illustrated in FIG. 6 for the fifth alternative, a backside of its metal pad 336 or copper post 318 may be exposed with being coplanar with a backside of said each of the first type of vertical-through-via (VTV) connectors 467 and the bottom surface of the polymer layer 92.

[0362] Next, referring to FIG. 22G, a backside interconnection scheme for a logic drive or device (BISD) 79 may be formed on the backside of each of the semiconductor integrated-circuit (IC) chips 100, the backside of each of the first type of operation units 190, the backside of each of the first type of vertical-through-via (VTV) connectors 467 and the bottom surface of the polymer layer 92. The backside interconnection scheme for a logic drive or device (BISD) 79 may include an insulating dielectric layer 93 on the backside of each of the semiconductor integrated-circuit (IC) chips 100, the backside of each of the first type of operation units 190, the backside of each of the first type of vertical-through-via (VTV) connectors 467 and the bottom surface of the polymer layer 92. Each opening in the insulating dielectric layer 93 may be vertically under the backside of one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467. The insulating dielectric layer 93 may be a layer of polymer, such as polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer or silicone, having a thickness between 3 and 30 micrometers or between 5 and 15 micrometers. For said one of the first type of vertical-through-via (VTV) connectors 467, if said one of its vertical through vias (VTVs) 358 is made of one or more of the through silicon vias (TSVs) 157 as illustrated in one of FIGS. 1A, 1C, 1E, 2A, 2C and 2E, said each opening in the insulating dielectric layer 93 may be vertically under the backside of the copper layer 156 of said one or more of its through silicon vias (TSVs) 157. For said one of the first type of vertical-through-via (VTV) connectors 467, if said one of its vertical through vias (VTVs) 358 is made of one or more of the through glass vias (TGVs) 259 as illustrated in one of FIGS. 4A, 4B, 4C, 5A, 5B and 5C, said each opening in the insulating dielectric layer 93 may be vertically under the backside of the copper post 706 of said one or more of its through glass vias (TGVs) 259. For said one of the first type of vertical-through-via (VTV) connectors 467, if said one of its vertical through vias (VTVs) 358 is made of one of the through polymer vias (TPVs) as illustrated in FIG. 6, said each opening in the insulating dielectric layer 93 may be vertically under the backside of the metal pad 336 or copper post 318 of said one of its through polymer vias (TPVs). The backside interconnection scheme for a logic drive or device (BISD) 79 may further include an interconnection metal layer on a bottom surface of its insulating dielectric layer 93, coupling to each of the vertical through vias (VTVs) 358 of each of the first type of vertical-through-via (VTV) connectors 467 through one of the opening in its insulating dielectric layer 93. The interconnection metal layer of the backside interconnection scheme for a logic drive or device (BISD) 79 is patterned with multiple metal pads 583, i.e., metal contacts, each formed on the backside of one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 or formed on the bottom surface of the insulating dielectric layer 93 and vertically under the backside of one of the semiconductor integrated-circuit (IC) chips 100, the backside of one of the first type of operation units 190, the backside of one of the first type of vertical-through-via (VTV) connectors 467 or the bottom surface of the polymer layer 92. Each of the metal pads 583 may be of various types. A first type of metal pad 583 may include (1) an adhesion layer 26a, such as titanium (Ti) or titanium nitride (TiN) layer having a thickness between 1 nm and 50 nm, on the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 for one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 as illustrated in one of FIGS. 1A, 1C, 1E, 2A, 2C and 2E, the backside of the copper post 706 of one of the through glass vias (TGVs) 259 for one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 as illustrated in one of FIGS. 4A, 4B, 4C, 5A, 5B and 5C or the backside of the metal pad 336 or copper post 318 of one of the through polymer vias (TPVs) for one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 as illustrated in FIG. 6 or on the bottom surface of the insulating dielectric layer 93, (2) a seed layer 26b, such as copper, on its adhesion layer 26a, and (3) a copper layer 32, i.e., copper pad, having a thickness between 1 μm and 60 μm on its seed layer 26b. Alternatively, a second type of metal pad 583 may include the adhesion layer 26a, seed layer 26b and copper layer 32 as mentioned above, and may further include a nickel layer, i.e., nickel pad, having a thickness between 0.5 μm and 10 μm on its copper layer 32. Alternatively, a tin-containing solder bump made of tin or a tin-silver alloy having a thickness between 1 μm and 50 μm may be formed on the copper layer 32 of each of the first type of metal pads 583 or the nickel layer of each of the second type of metal pads 583.

[0363] Next, referring to FIG. 22G, multiple metal bumps, pillars or pads 570, i.e., metal contacts, may be formed in an array on the metal pads of the topmost one of the interconnection metal layers 27 of the frontside interconnection scheme for a logic drive or device (FISD) 101 at the bottoms of the respective openings 42a in the topmost one of the polymer layers 42 of the frontside interconnection scheme for a logic drive or device (FISD) 101. Each of the metal bumps, pillars or pads 570 may be of various types. A first type of bump, pillar or pad 570 may include (1) an adhesion layer 26a, such as titanium (Ti) or titanium nitride (TiN) layer having a thickness between 1 nm and 50 nm, on the topmost one of the interconnection metal layers 27 of the frontside interconnection scheme for a logic drive or device (FISD) 101, (2) a seed layer 26b, such as copper, on its adhesion layer 26a and (3) a copper layer 32, i.e., copper pad, having a thickness between 1 μm and 60 μm on its seed layer 26b. Alternatively, a second type of metal bump, pillar or pad 570 may include the adhesion layer 26a, seed layer 26b and copper layer 32 as mentioned above, and may further include a tin-containing solder cap 33, i.e., solder bump, made of tin or a tin-silver alloy having a thickness between 1 μm and 50 μm on its copper layer 32. Alternatively, a third type of metal bump, pillar or pad 570 may include a gold layer, i.e., gold bump, having a thickness between 3 and 15 micrometers over the topmost one of the interconnection metal layers 27 of the frontside interconnection scheme for a logic drive or device (FISD) 101.

[0364] Next, referring to FIG. 22G, the polymer layers 42 of the frontside interconnection scheme for a logic drive or device (FISD) 101, the polymer layer 92 and the insulating dielectric layer 93 may be cut or diced to separate multiple individual chip packages 300 as shown in FIG. 22H each for the standard commodity logic drive as illustrated in FIG. 12A by a laser cutting process or by a mechanical cutting process. For the chip package 300 as seen in FIG. 22H, one or more of the interconnection metal layers 27 of its frontside interconnection scheme for a logic drive or device (FISD) 101 may couples each of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 to the other of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467. Each of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 may couple to one of its metal pads 583 through, in sequence, one or more of the interconnection metal layers 27 of its frontside interconnection scheme for a logic drive or device (FISD) 101 and one of the vertical through vias (VTV) 358 of one of its first type of vertical-through-via (VTV) connectors 467 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to said each of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467. Each of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 may couple to one or more of its metal bumps, pillars or pads 570 through each of the interconnection metal layers 27 of its frontside interconnection scheme for a logic drive or device (FISD) 101 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to said each of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467. One of its metal bumps, pillars or pads 570 vertically over each of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 may couple to one of its metal pads 583 vertically under said each of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 through, in sequence, each of the interconnection metal layers 27 of its frontside interconnection scheme for a logic drive or device (FISD) 101, one of the vertical through vias (VTVs) 358 of one of its first type of vertical-through-via (VTV) connectors 467 and the interconnection metal layer of its backside interconnection scheme for a logic drive or device (BISD) 79 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals. Each of its metal bumps, pillars or pads 570 having a number of more than 20 may be vertically aligned with one of its metal pads 583 having a number of more than 20. Each of its metal bumps, pillars or pads 570 having a number of more than 50 may be vertically aligned with one of its metal pads 583 having a number of more than 50. Each of the vertical through vias (VTVs) 358 of each of its first type of vertical-through-via (VTV) connectors 467 may have a depth, for example, between 30 μm and 2,000 μm.

[0365] For the chip package 300 as seen in FIG. 22H, its metal pads 583 arranged in an array may include multiple dummy pads 583a each not connecting to any of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 but having mechanical functions for subsequent package-on-package (POP) assembly, formed on the bottom surface of its insulating dielectric layer 93 and vertically under one of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and polymer layer 92. Each of its dummy pads 583a may have no connection to any of the vertical through vias (VTVs) 358 of any of its first type of vertical-through-via (VTV) connectors 467.

[0366] Alternatively, FIG. 22I is a schematically cross-sectional view showing a first type of single-chip/unit package in accordance with a first embodiment of the present application. The chip package 300 as seen in FIG. 22I may have a similar structure to that as illustrated in FIG. 22H. For an element indicated by the same reference number shown in FIGS. 22H and 22I, the specification of the element as seen in FIG. 22I may be referred to that of the element as illustrated in FIG. 22H. The difference between the chip packages as illustrated in FIGS. 22H and 22I is that the chip package as seen in FIG. 22I includes only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190 having the same specification as illustrated in FIG. 22A and one or more first type of vertical-through-via (VTV) connectors 467 having the same specification as illustrated in FIG. 22A. For the single-chip/unit package 300 as seen in FIG. 22I, its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190 may couple to one of its metal pads 583 through, in sequence, one or more of the interconnection metal layers 27 of its frontside interconnection scheme for a logic drive or device (FISD) 101 and one of the vertical through vias (VTVs) 358 of one of its first type of vertical-through-via (VTV) connectors 467 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190. Each of its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190 and its first type of vertical-through-via (VTV) connectors 467 may couple to one or more of its metal bumps, pillars or pads 570 through each of the interconnection metal layers 27 of its frontside interconnection scheme for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190. One of its metal bumps, pillars or pads 570 vertically over its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190 may couple to one of its metal pads 583 vertically under its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190 through, in sequence, each of the interconnection metal layers 27 of its frontside interconnection scheme for a logic drive or device (FISD) 101, one of the vertical through vias (VTVs) 358 of one of its first type of vertical-through-via (VTV) connectors 467 and the interconnection metal layer of its backside interconnection scheme for a logic drive or device (BISD) 79 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals. Each of its metal bumps, pillars or pads 570 having a number of more than 20 may be vertically aligned with one of its metal pads 583 having a number of more than 20. Alternatively, each of its metal bumps, pillars or pads 570 having a number of more than 50 may be vertically aligned with one of its metal pads 583 having a number of more than 50. For example, its more than twenty first metal contacts, i.e., metal bumps, pillars or pads 570, may be vertically over its only one semiconductor integrated-circuit (IC) chip 100 and its more than twenty second metal contacts, i.e., metal pads 583, may be vertically under its only one semiconductor integrated-circuit (IC) chip 100. Each of the vertical through vias (VTVs) 358 of each of its first type of vertical-through-via (VTV) connector(s) 467 may have a depth, for example, between 30 μm and 2,000 μm.

[0367] FIGS. 23A and 23B are schematically cross-sectional views showing a process for forming a second type of multichip package in accordance with a first embodiment of the present application. For an element indicated by the same reference number shown in FIGS. 22A-22H, 23A and 23B, the specification of the element as seen in FIG. 23A or 23B may be referred to that of the element as illustrated in FIGS. 22A-22H. After the structure as seen in FIG. 22F is formed, a backside interconnection scheme for a logic drive or device (BISD) 79 may be formed on the backside of each of the semiconductor integrated-circuit (IC) chips 100, the backside of each of the first type of operation units 190, the backside of each of the first type of vertical-through-via (VTV) connectors 467 and the bottom surface of the polymer layer 92. The backside interconnection scheme for a logic drive or device (BISD) 79 may include one or more interconnection metal layers 27 coupling to each of the vertical through vias (VTVs) 358 of each of the first type of vertical-through-via (VTV) connectors 467 and one or more polymer layers 42, i.e., insulating dielectric layers, each between neighboring two of its interconnection metal layers 27, under the bottommost one of its interconnection metal layers 27 or over the topmost one of its interconnection metal layers 27, wherein an upper one of its interconnection metal layers 27 may couple to a lower one of its interconnection metal layers 27 through an opening in one of its polymer layers 42 between the upper and lower ones of its interconnection metal layers 27. The topmost one of its polymer layers 42 may be between the topmost one of its interconnection metal layers 27 and the backside of each of the semiconductor integrated-circuit (IC) chips 100, between the topmost one of its interconnection metal layers 27 and the backside of each of the first type of operation units 190, between the topmost one of its interconnection metal layers 27 and the backside of each of the first type of vertical-through-via (VTV) connectors 467 and between the topmost one of its interconnection metal layers 27 and the bottom surface of the polymer layer 92, wherein each opening in the topmost one of its polymer layers 42 may be vertically under the backside of one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467. For the backside interconnection scheme for a logic drive or device (BISD) 79, each of its interconnection metal layers 27 may extend horizontally across an edge of each of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467. The bottommost one of its interconnection metal layers 27 may be patterned with multiple metal pads 583 aligned with multiple respective openings in the bottommost one of its polymer layers 42.

[0368] Referring to FIG. 23A, for the backside interconnection scheme for a logic drive or device (BISD) 79, each of its polymer layers 42 may be a layer of polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer or silicone, having a thickness between, for example, 0.3 μm and 50 μm, 0.3 μm and 30 μm, 0.5 μm and 20 μm, 1 μm and 10 μm, or 0.5 μm and 5 μm, or thicker than or equal to 0.3 μm, 0.5 μm, 0.7 μm, 1 μm, 1.5 μm, 2 μm, 3 μm or 5 μm. Each of its interconnection metal layers 27 may be provided with multiple metal traces or lines each including (1) a copper layer 40 having one or more upper portions in openings in one of its polymer layers 42 having a thickness between 0.3 μm and 20 μm, and an lower portion having a thickness 0.3 μm and 20 μm under said one of its polymer layers 42, (2) an adhesion layer 28a, such as titanium or titanium nitride having a thickness between 1 nm and 50 nm, at a top and sidewall of each of the one or more upper portions of the copper layer 40 of said each of the metal traces or lines and at a top of the lower portion of the copper layer 40 of said each of the metal traces or lines, and (3) a seed layer 28b, such as copper, between the copper layer 40 and adhesion layer 28a of said each of the metal traces or lines, wherein the lower portion of the copper layer 40 of said each of the metal traces or lines may have a sidewall not covered by the adhesion layer 28a of said each of the metal traces or lines. Each of its interconnection metal layers 27 may provide multiple metal lines or traces with a thickness between, for example, 0.3 μm and 40 μm, 0.5 μm and 30 μm, 1 μm and 20 μm, 1 μm and 15 μm, 1 μm and 10 μm, or 0.5 μm to 5 μm, or thicker than or equal to 0.3 μm, 0.7 μm, 1 μm, 2 μm, 3 μm, 5 μm, 7 μm or 10 μm, and a width between, for example, 0.3 μm and 40 μm, 0.5 μm and 30 μm, 1 μm and 20 μm, 1 μm and 15 μm, 1 μm and 10 μm, or 0.5 μm to 5 μm, or wider than or equal to 0.3 μm, 0.7 μm, 1 μm, 2 μm, 3 μm, 5 μm, 7 μm or 10 μm. Each of its interconnection metal layers 27 may have two planes used respectively for power and ground planes of a power supply and/or used as a heat dissipater or spreader for the heat dissipation or spreading, wherein each of the two planes may have a thickness, for example, between 5 μm and 50 μm, 5 μm and 30 μm, 5 μm and 20 μm, or 5 μm and 15 μm; or thicker than or equal to 5 μm, 10 μm, 20 μm, or 30 μm. The two planes may be layout as interlaced or interleaved shaped structures in a plane or may be layout in a fork shape.

[0369] Referring to FIG. 23A, each of the metal pads 583 may be of various types. A first type of metal pad 583 may include (1) an adhesion layer 28a, such as titanium (Ti) or titanium nitride (TiN) layer having a thickness between 1 nm and 50 nm, on a bottom surface of a second bottommost one of the polymer layers 42 of the backside interconnection scheme for a logic drive or device (BISD) 79, (2) a seed layer 28b, such as copper, on a bottom surface of its adhesion layer 28a, and (3) a copper layer 40, i.e., copper pad, having a thickness between 0.3 μm and 20 μm on a bottom surface of its seed layer 28b and at a top of one of the openings in the bottommost one of its polymer layers 42. Alternatively, a second type of metal pad 583 may include the adhesion layer 28a, seed layer 28b and copper layer 40 as mentioned above, and may further include a nickel layer, i.e., nickel pad, having a thickness between 0.5 μm and 10 μm on a bottom surface of its copper layer 32 and in one of the openings in the bottommost one of its polymer layers 42. Alternatively, a tin-containing solder bump made of tin or a tin-silver alloy having a thickness between 1 μm and 50 μm may be formed under the bottom surface of the copper layer 32 of each of the first type of metal pads 583 or a bottom surface of the nickel layer of each of the second type of metal pads 583.

[0370] Next, referring to FIG. 23A, metal bumps, pillars or pads 570 may be formed in an array on the metal pads of the topmost one of the interconnection metal layers 27 of the frontside interconnection scheme for a logic drive or device (FISD) 101 at the bottoms of the respective openings 42a in the topmost one of the polymer layers 42 of the frontside interconnection scheme for a logic drive or device (FISD) 101. Each of the metal bumps, pillars or pads 570 may be of one of the first through third types having the same specifications as the first through third types of metal bumps, pillars or pads 570 as illustrated in FIGS. 22G, respectively.

[0371] Next, referring to FIG. 23A, the polymer layers 42 of the frontside interconnection scheme for a logic drive or device (FISD) 101, the polymer layer 92 and the polymer layers 42 of the backside interconnection scheme for a logic drive or device (BISD) 79 may be cut or diced to separate multiple individual chip packages 300 as shown in FIG. 23B each for the standard commodity logic drive as illustrated in FIG. 12A by a laser cutting process or by a mechanical cutting process. For the chip package 300 as seen in FIG. 23B, each of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 may couple to one of its metal pads 583 through, in sequence, one or more of the interconnection metal layers 27 of its frontside interconnection scheme for a logic drive or device (FISD) 101, one of the vertical through vias (VTVs) 358 of one of its first type of vertical-through-via (VTV) connectors 467 and each of the interconnection metal layer 27 of its backside interconnection scheme for a logic drive or device (BISD) 79 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to said each of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190. One of its metal bumps, pillars or pads 570 vertically over each of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 may couple to one of its metal pads 583 vertically under said each of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 through, in sequence, each of the interconnection metal layers 27 of its frontside interconnection scheme for a logic drive or device (FISD) 101, one of the vertical through vias (VTVs) 358 of one of its first type of vertical-through-via (VTV) connectors 467 and each of the interconnection metal layers 27 of its backside interconnection scheme for a logic drive or device (BISD) 79 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals. Each of its metal bumps, pillars or pads 570 having a number of more than 20 may be vertically aligned with one of its metal pads 583 having a number of more than 20. Alternatively, each of its metal bumps, pillars or pads 570 having a number of more than 50 may be vertically aligned with one of its metal pads 583 having a number of more than 50. Each of the vertical through vias (VTVs) 358 of each of its first type of vertical-through-via (VTV) connectors 467 may have a depth, for example, between 30 μm and 2,000 μm.

[0372] Alternatively, the chip packages 300 may further include multiple dummy chips 409 each arranged between two of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467, between its edge and one of its first type of semiconductor chips 100 or between its edge and one of its first type of vertical-through-via (VTV) connectors 467, as seen in FIGS. 23C and 23D, wherein each of the dummy chips 409 may not provide any electrical function.

[0373] FIG. 23C is a schematically top view showing a second type of multichip package in accordance with a first embodiment of the present application, wherein FIG. 23B is a schematically cross-sectional view along a cross-sectional line C-C on FIG. 23C, and FIG. 23D is a schematically cross-sectional view along a cross-sectional line D-D on FIG. 23C. For an element indicated by the same reference number shown in FIGS. 22A-22H and 23A-23D, the specification of the element as seen in FIG. 23C or 23D may be referred to that of the element as illustrated in FIG. 22A-22H, 23A or 23B. For a process for fabricating the chip packages 300, multiple dummy chips 409 may be further provided to have a backside side of each of the dummy chips 409 attached to the sacrificial bonding layer 591 in the step as illustrated in FIG. 22A. Next, in the step as illustrated in FIG. 22B, the polymer layer 92 may be formed further over a frontside of each of the dummy chips 409 and in multiple gaps each between one of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 and one of the dummy chips 409. Next, in the step as illustrated in FIG. 22C, the chemical mechanical polishing (CMP), polishing or grinding process may be performed further to remove a top portion of each of the dummy chips 409 and to planarize the frontside of each of the dummy chips 409 with the top surface of the polymer layer 92. Next, in the step as illustrated in FIG. 22D, the bottommost one of the polymer layers 42 of the frontside interconnection scheme for a logic drive or device (FISD) 101 may be further formed on the frontside of each of the dummy chips 409. Next, in the step as illustrated in FIG. 22E, the temporary substrate (T-sub) 590 as shown in FIG. 22D may be removed further from the backside of each of the dummy chips 409. Next, in the step as illustrated in FIG. 22F, the chemical mechanical polishing (CMP), polishing or grinding process may be applied further to remove a bottom portion of each of the dummy chips 409. Next, in the step as illustrated in FIG. 23A, the topmost one of the polymer layers 42 of the backside interconnection scheme for a logic drive or device (BISD) 79 may be further formed on the backside of each of the dummy chips 409. Next, in the step as illustrated in FIG. 23A, one or more of the metal bumps, pillars or pads 570 may be formed vertically over each of the dummy chips 409. Next, referring to FIG. 23A, the polymer layers 42 of the front side interconnection scheme for a logic drive or device (FISD) 101, the polymer layer 92, one or more of the dummy chips 409 and the polymer layers 42 of the backside interconnection scheme for a logic drive or device (BISD) 79 may be cut or diced to separate the individual chip packages 300 as shown in each of FIGS. 23B-23D by a laser cutting process or by a mechanical cutting process, and thus each of said one or more of the dummy chips 409 may have a sidewall 409a exposed and not covered by the polymer layer 92. For each of the chip packages 300 as seen in FIGS. 23B-23D, when a width or distance Wd1 between neighboring two of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 may range from 500 to 2500 micrometers or from 700 to 1800 micrometers or may be greater than 600, 800, 1200 or 1500 micrometers, one of its dummy chips 409 may be arranged between said neighboring two of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467.

[0374] When a width or distance Wd2 between one of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 and its edge may range from 500 to 2500 micrometers or from 700 to 1800 micrometers or may be greater than 600, 800, 1200 or 1500 micrometers, one of its dummy chips 409 may be arranged between said one of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 and its edge. A width or distance Wd3 between one of its dummy chips 409 and its edge may range from 30 to 300 micrometers, from 50 to 200 micrometers or from 80 to 120 micrometers or may be smaller than 300 or 200 micrometers. A width or distance Wd4 between one of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 and one of its first type of vertical-through-via (VTV) connectors 467 may range from 30 to 300 micrometers, from 50 to 200 micrometers or from 80 to 120 micrometers or may be smaller than 300 or 200 micrometers. A width or distance Wd5 between one of its first type of vertical-through-via (VTV) connectors 467 and one of its dummy chips 409 may range from 30 to 300 micrometers, from 50 to 200 micrometers or from 80 to 120 micrometers or may be smaller than 300 or 200 micrometers. A width or distance Wd6 between one of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 and one of its dummy chips 409 may range from 30 to 300 micrometers, from 50 to 200 micrometers or from 80 to 120 micrometers or may be smaller than 300 or 200 micrometers.

[0375] Alternatively, FIG. 23E is a schematically cross-sectional view showing a second type of single-chip/unit package in accordance with a first embodiment of the present application. The chip package 300 as seen in FIG. 23E may have a similar structure to that as illustrated in FIG. 23B. For an element indicated by the same reference number shown in FIGS. 22A-22I, 23A, 23B and 23E, the specification of the element as seen in FIG. 23E may be referred to that of the element as illustrated in FIG. 22A-22I, 23A or 23B. The difference between the chip packages as illustrated in FIGS. 23B and 23E is that the chip package as seen in FIG. 23E may include only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190 having the same specification as illustrated in FIG. 22A and one or more first type of vertical-through-via (VTV) connectors 467 having the same specification as illustrated in FIG. 22A. For the single-chip/unit package 300 as seen in FIG. 23E, its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190 may couple to one of its metal pads 583 through, in sequence, one or more of the interconnection metal layers 27 of its frontside interconnection scheme for a logic drive or device (FISD) 101, one of the vertical through vias (VTVs) 358 of one of its first type of vertical-through-via (VTV) connectors 467 and each of the interconnection metal layer 27 of its backside interconnection scheme for a logic drive or device (BISD) 79 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190. One of its metal bumps, pillars or pads 570 vertically over its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190 may couple to one of its metal pads 583 vertically under its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190 through, in sequence, each of the interconnection metal layers 27 of its frontside interconnection scheme for a logic drive or device (FISD) 101, one of the vertical through vias (VTVs) 358 of one of its first type of vertical-through-via (VTV) connectors 467 and each of the interconnection metal layers 27 of its backside interconnection scheme for a logic drive or device (BISD) 79 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals. Each of its metal bumps, pillars or pads 570 having a number of more than 20 may be vertically aligned with one of its metal pads 583 having a number of more than 20. Alternatively, each of its metal bumps, pillars or pads 570 having a number of more than 50 may be vertically aligned with one of its metal pads 583 having a number of more than 50. For example, its more than twenty first metal contacts, i.e., metal bumps, pillars or pads 570, may be vertically over its only one semiconductor integrated-circuit (IC) chip 100 and its more than twenty second metal contacts, i.e., metal pads 583, may be vertically under its only one semiconductor integrated-circuit (IC) chip 100. Each of the vertical through vias (VTVs) 358 of each of its first type of vertical-through-via (VTV) connector(s) 467 may have a depth, for example, between 30 μm and 2,000 μm.

[0376] FIGS. 24A and 24B are schematically cross-sectional views showing a process for forming various package-on-package (POP) assemblies for multiple first type of chip packages in accordance with a first embodiment of the present application. Multiple first type of chip packages 300 as illustrated in FIG. 22H may be provided to be stacked together to form a package-on-package (POP) assembly as seen in FIG. 24A.