SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

[0001] This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2025-041727, filed on Mar. 14, 2025, the entire contents of which are incorporated herein by reference.

[0002] The embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof.

[0003] Some semiconductor storage devices such as a NAND flash memory have a stacked structure including an array chip where a memory cell array is arranged, and a CMOS (Complementary Metal Oxide Semiconductor) chip where a CMOS circuit is arranged.

[0023] In general, a semiconductor device according to the present embodiment includes a first structure and a second structure. A plurality of semiconductor elements are formed in the first structure. The second structure is stacked on the first structure. The second structure includes a substrate, a plurality of second semiconductor elements located on a first surface of the substrate, and isolation parts each located between adjacent ones of the second semiconductor elements and penetrating through the substrate between the first surface and a second surface of the substrate on the opposite side to the first surface. A first conductor is located between the first structure and the second structure and is electrically separated from the substrate. Each of the isolation parts includes a first isolation part extending from the first surface toward the second surface and where a width thereof in a perpendicular direction to a first direction from the first surface to the second surface decreases from the first surface toward the second surface, and a second isolation part extending from the second surface toward the first surface and where a width thereof in a perpendicular direction to the first direction decreases from the second surface toward the first surface.

[0024] Hereinafter, devices of the present disclosure will be described with reference to the drawings.

[0025] The present invention is not limited to the embodiments. In the present specification and the drawings, elements identical to those described in the foregoing drawings are denoted by like reference characters and detailed explanations thereof are omitted as appropriate.

[0026] As used in the present specification and the claims, when a first element is “connected” to another second element, the first element can be connected to the second element directly, or via an element that becomes conductive either constantly or selectively. While it is assumed that a +Z direction is an upward direction and a −Z direction is a downward direction in the present specification and the drawings, it is sometimes assumed in FIGS. 13 to 16 that the −Z direction is conversely the upward direction and the +Z direction is the downward direction.

[0027] FIG. 1 is a block diagram illustrating a configuration example of a storage device 1 according to a first embodiment. The storage device 1 as one example of a semiconductor device is a device that stores therein data using memory cells. The storage device 1 is, for example, a NAND flash memory. The storage device 1 is controlled by an external memory controller. The storage device 1 operates, for example, based on a command CMD and address information ADD received from the memory controller. The storage device 1 receives data DAT to be written, and outputs data stored in the storage device 1.

[0028] The storage device 1 includes constituent elements such as a memory cell array 10, row decoders 11, a register 12, a sequencer 13, a voltage generation circuit 14, a driver 15, and a sense amplifier 17.

[0029] The memory cell array 10 is a set of arrayed memory cells. The memory cell array 10 includes a plurality of memory blocks (blocks) BLK. Each block BLK includes a plurality of memory cell transistors MT (see FIG. 2). A region where the memory cell array 10 is arranged also includes lines such as word lines WL (see FIG. 2) and bit lines BL (see FIG. 2).

[0030] The row decoders 11 are circuits for selecting a block BLK. The row decoders 11 transfer a voltage supplied from the driver 15 to one block BLK selected based on a block address received by the row decoders 11 from the register 12.

[0031] The register 12 is a circuit that retains a command CMD and address information ADD received by the storage device 1. The command CMD instructs various operations including a data read operation, a data write operation, and a data erase operation to the sequencer 13. The address information ADD designates an access target in the memory cell array 10.

[0032] The sequencer 13 is a circuit that controls the entire operation of the storage device 1. The sequencer 13 controls the row decoders 11, the driver 15, and the sense amplifier 17 on the basis of the command CMD received by the sequencer 13 to perform various operations including a data read operation, a data write operation, and a data erase operation.

[0033] The voltage generation circuit 14 is a circuit that generates different levels of voltages. The voltage generation circuit 14 receives a power voltage from outside the storage device 1 and generates voltages from the power voltage. The voltage generation circuit 14 supplies the generated voltages to constituent elements such as the memory cell array 10, the driver 15, and the sense amplifier 17.

[0034] The driver 15 is a circuit that applies various voltages required for the operation of the storage device 1 to some constituent elements. The driver 15 receives plural voltages from the voltage generation circuit 14 and supplies selected ones of the voltages to one or more row decoders 11.

[0035] The sense amplifier 17 is a circuit that outputs a signal based on data stored in the memory cell array 10. The sense amplifier 17 senses the state of a relevant memory cell transistor MT (hereinafter, also simply “memory cell”) and generates read data on the basis of the sensed state. The sense amplifier 17 applies a voltage based on data to be written, to a bit line BL.

[0036] FIG. 2 is a block diagram illustrating a configuration example of the storage device according to the first embodiment. A plurality of the blocks BLK, for example, all the blocks BLK include constituent elements and connections illustrated in FIG. 2.

[0037] One block BLK includes a plurality of string units SU. FIG. 2 illustrates an example of five string units SU_0 to SU_4.

[0038] As illustrated in FIG. 2, each of m bit lines BL_0 to BL_m-1 is connected to one NAND string NS in each of the string units SU_0 to SU_4 in each block BLK. In this example, m is a positive integer.

[0039] Each NAND string NS includes one selection gate transistor ST, n memory cell transistors MT (MT_0 to MT_n-1), and one selection gate transistor DT (DT_0, DT_1, DT_2, DT_3, or DT_4). In this example, n is a positive integer. Each of the memory cell transistors MT is an element that functions as a memory cell and stores therein data in a nonvolatile manner. Each memory cell transistor MT includes a control gate electrode or a gate electrode (a word line WL) and a charge accumulation film insulated from the peripheral part, and stores therein data in a nonvolatile manner on the basis of charges in the charge accumulation film. Data is written to each of the memory cell transistors MT by injection of electrons into the charge accumulation film.

[0040] The selection gate transistor ST, the memory cell transistors MT_0 to MT_n-1, and the selection gate transistor DT are connected in series in this order between a source line SL and one bit line BL.

[0041] A plurality of NAND strings NS respectively connected to a plurality of different bit lines BL constitute one string unit SU. In each string unit SU, the control gate electrodes of the memory cell transistors MT_0 to MT_n-1 are connected to word lines WL_0 to WL_n-1, respectively. A set of memory cell transistors MT sharing a word line WL in one string unit SU is referred to as “cell unit CU”.

[0042] The selection gate transistors DT_0 to DT_4 belong to the string units SU_0 to SU_4, respectively. In FIG. 2, illustrations of the selection gate transistors DT_2, DT_3, and DT_4 are omitted. The gates of the selection gate transistors DT_0 in the NAND strings NS in the string unit SU_0 are connected to a selection gate line SGDL_0. Similarly, the gates of the selection gate transistors DT_1, DT_2, DT_3, and DT_4 in the associated NAND strings NS in the string units SU_1, SU_2, SU_3, and SU_4 are connected to selection gate lines SGDL_1, SGDL_2, SGDL_3, and SGDL_4, respectively.

[0043] The gates of the selection gate transistors ST are connected to a selection gate line SGSL.

[0044] FIG. 3 is a perspective view illustrating a configuration example of the storage device according to the first embodiment. The storage device 1 includes a first structure 100, a second structure 200, and a third structure 300. The first structure 100, the second structure 200, and the third structure 300 spread along an XY plane and are stacked in the Z direction. The second structure 200 is located on a surface (the upper surface) of the first structure 100 on a side in the Z direction. The third structure 300 is located on the upper surface of the second structure 200.

[0045] Each of the first structure 100, the second structure 200, and the third structure 300 includes a plurality of semiconductors, a plurality of various conductors, and a plurality of insulators formed on a substrate using the substrate. Each of the first structure 100, the second structure 200, and the third structure 300 includes a plurality of elements and lines realized by semiconductors, conductors, and insulators. Each of the first structure 100, the second structure 200, and the third structure 300 includes an electrical circuit including elements and lines. The elements and lines in the first structure 100, the elements and lines in the second structure 200, and the elements and lines in the third structure 300 are electrically connected to each other. Each of the first structure 100, the second structure 200, and the third structure 300 is formed as an individual semiconductor chip. The first structure 100, the second structure 200, and the third structure 300 are bonded to each other to be a semiconductor chip of one storage device 1.

[0046] A set of the first structure 100 and the second structure 200 includes the row decoders 11, the register 12, the sequencer 13, the voltage generation circuit 14, the driver 15, and the sense amplifier 17. The first structure 100 includes any constituent elements among the row decoders 11, the register 12, the sequencer 13, the voltage generation circuit 14, the driver 15, and the sense amplifier 17. The second structure 200 includes any constituent elements among the row decoders 11, the register 12, the sequencer 13, the voltage generation circuit 14, the driver 15, and the sense amplifier 17. For example, the first structure 100 includes semiconductor elements constituting the row decoders 11, the register 12, the sequencer 13, the voltage generation circuit 14, and the driver 15. The second structure 200 includes semiconductor elements constituting the sense amplifier 17. Each of the row decoders 11, the register 12, the sequencer 13, the voltage generation circuit 14, the driver 15, and the sense amplifier 17 is constituted of a CMOS circuit including a p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an n-type MOSFET. Each of the first structure 100 and the second structure 200 is, for example, a CMOS chip including such a CMOS circuit.

[0047] The third structure 300 is, for example, an array chip including the memory cell array 10 and a plurality of external connection terminals PD. The external connection terminals PD are exposed on the upper surface of the third structure 300.

[0048] FIG. 4 is a conceptual diagram illustrating a configuration example of the storage device according to the first embodiment. FIG. 4 illustrates the structure illustrated in FIG. 3 in an exploded manner.

[0049] The first structure 100 includes a plurality of conductive joint terminals BP1. The joint terminals BP1 are exposed on the upper surface of the first structure 100. The joint terminals BP1 are connected to the elements in the first structure 100.

[0050] The second structure 200 includes a plurality of conductive joint terminals BP2L and a plurality of conductive joint terminals BP2U. The joint terminals BP2L are exposed on a surface (the lower surface) of the second structure 200 on a side in the-Z direction. The joint terminals BP2L are connected to the elements in the second structure 200. The joint terminals BP2L have the same layout as that of the joint terminals BP1 of the first structure 100. The joint terminals BP2L are arrayed in such a manner that each of the joint terminals BP2L is in contact with one of the joint terminals BP1 of the first structure 100 corresponding to this joint terminal BP2L when the first structure 100 and the second structure 200 are joined to each other. A certain joint terminal BP2L and one of the joint terminals BP1 of the first structure 100 corresponding to the certain joint terminal BP2L are elements functioning as the same node in a circuit.

[0051] The joint terminals BP2U are exposed on the upper surface of the second structure 200. The joint terminals BP2U are connected to the elements in the second structure 200.

[0052] The third structure 300 includes a plurality of conductive joint terminals BP3. The joint terminals BP3 are exposed on the lower surface of the third structure 300. The joint terminals BP3 are connected to the elements in the third structure 300. The joint terminals BP3 have the same layout as that of the joint terminals BP2U of the second structure 200. The joint terminals BP3 are arrayed in such a manner that each of the joint terminals BP3 is in contact with one of the joint terminals BP2U of the second structure 200 corresponding to this joint terminal BP3 when the second structure 200 and the third structure 300 are joined to each other. A certain joint terminal BP3 and one of the joint terminals BP2U of the second structure 200 corresponding to the certain joint terminal BP3 are elements functioning as the same node in a circuit.

[0053] FIG. 5 is a sectional view illustrating a configuration example of the storage device according to the first embodiment. The first structure 100 is bonded to the second structure 200 on the side of a second surface F2 of a substrate W2 to be stacked thereon. The third structure 300 is bonded to the second structure 200 on the side of a first surface F1 of the substrate W2 to be stacked thereon.

[0054] The first structure 100 further includes a substrate W1, transistors Tr1, contacts CS1, C0, C1, C2, and C3, conductors L0, L1, and L2, and insulators 21 and 22. In the following descriptions, conductors also include semiconductors having a conductivity due to inclusion of a metallic material or impurities. In one example, the substrate W1 includes silicon. In one example, each of the contacts CS1, C0, C1, C2, and C3 and the conductors L0, L1, and L2 includes copper or tungsten. In one example, each of the insulators 21 and 22 includes silicon oxide.

[0055] The transistors Tr1 are positioned in a region of an upper part of the substrate W1 and near the upper surface. Each of the transistors Tr1 includes a gate insulator on the upper surface of the substrate W1, a gate electrode on the upper surface of the gate insulator, and a region (source/drain region) of one pair of a source and a drain sandwiching a region below the gate electrode. Each of the transistors Tr1 is electrically connected to any of conductors (for example, word lines WL) 31, 33, and 36 via a conductor (for example, a line) L3 and a through-electrode TSV of the second structure 200. Accordingly, the transistors Tr1 of the first structure 100 can constitute the driver (drive circuit) 15 that controls the voltages of the conductors 31, 33, and 36.

[0056] Each contact C0 is in contact on the lower surface with the upper surface of the gate electrode of one transistor Tr1. Each contact CS1 is in contact on the lower surface with one source/drain region.

[0057] Each conductor L0 is in contact on the lower surface with one contact C0 or CS1. Each contact C1 is in contact on the lower surface with the upper surface of one conductor L0.

[0058] Each conductor L1 is in contact on the lower surface with the upper surface of one contact C1. Each contact C2 is in contact on the lower surface with the upper surface of one conductor L1.

[0059] Each conductor L2 is in contact on the lower surface with the upper surface of one contact C2. Each contact C3 is in contact on the lower surface with the upper surface of one conductor L2.

[0060] A set of the transistor Tr1, the contacts CS1, C0, C1, C2, and C3, and the conductors L0, L1, and L2 realizes a circuit included in the first structure 100. Therefore, the first structure 100 has any shapes and arrangement of the transistors Tr1, the contacts CS1, C0, C1, C2, and C3, and the conductors L0, L1, and L2 realizing circuits included in the first structure 100.

[0061] The insulator 21 is arranged from the level of the upper surface of the substrate W1 to the level of the upper surfaces of the contacts C3. The insulator 21 fills a region where the constituent elements are not arranged in the first structure 100, that is, a region where the transistors Tr1, the contacts CS1, C0, C1, C2, and C3, and the conductors L0, L1, and L2 are not arranged.

[0062] Each joint terminal BP1 is in contact on the lower surface with the upper surface of one contact C3. The insulator 22 fills a region where the joint terminals BP1 are not located in a layer where the joint terminals BP1 are positioned.

[0063] The second structure 200 further includes the substrate W2, transistors Tr2, contacts CS2, CS5, C4, C5, C7, C8, C9, and C10, conductors L3, L4, L5, and L6, and insulators 24, 25, 26, and 27. The substrate W2 includes the first surface F1, and the second surface F2 on the opposite side to the first surface F1. In one example, the substrate W2 includes silicon. The thickness of the substrate W2 is, for example, 0.2 to 2 μm (micrometer). In one example, each of the contacts CS2, CS5, C4, C5, C7, C8, C9, and C10, and the conductors L3, L4, L5, and L6 includes copper or tungsten. In one example, each of the insulators 24, 25, 26, and 27 includes silicon oxide. The upper surface of the second structure 200 is on the side of the first surface F1 of the substrate W2 and the lower surface of the second structure 200 is on the side of the second surface F2 of the substrate W2.

[0064] Each joint terminal BP2L is positioned in the lowermost layer of the second structure 200. The insulator 24 fills a region where the joint terminals BP2L are not located in the layer where the joint terminals BP2L are positioned.

[0065] Each contact C4 is in contact on the lower surface with the upper surface of one joint terminal BP2L.

[0066] Each conductor L3 is in contact on the lower surface with the upper surface of one contact C4. In one example, each of the conductors L3 includes copper (Cu), aluminum (Al), and (or) tungsten (W). Each contact C5 is in contact on the lower surface with the upper surface of one conductor L3. The conductors L3 are electrically connected to the voltage generation circuit 14 to receive a high positive voltage. The conductors L3 are arranged on the side of the second surface F2 of the substrate W2 with the insulator 25 interposed therebetween. Each of the conductors L3 is electrically connected to a transistor Tr1 in the first structure 100 via the contact C4 and the like. The conductors L3 are located between the first structure 100 and the second structure 200 and are electrically insulated from the substrate W2 by the insulator 25. Each of the conductors L3 is electrically connected to conductors 31, 33, or 36 of the third structure 300 via a through-electrode TSV and the like.

[0067] The insulator 25 is arranged from the level of the upper surfaces of the joint terminals BP2L and the upper surface of the insulator 24 to the level of the upper surfaces of the contacts C5. The insulator 25 fills a region where the contacts C4 and C5, and the conductors L3 are not arranged in a region above the joint terminals BP2L and the insulator 24.

[0068] The substrate W2 is positioned on the upper surface of the insulator 25. The through-electrodes TSV penetrate through the substrate W2 from the upper surface of the substrate W2 to the lower surface thereof. Each through-electrode TSV is in contact on the lower surface with the upper surface of one contact C5. Insulators SP penetrate through the substrate W2 from the upper surface of the substrate W2 to the lower surface thereof. Each insulator SP covers the side surface of one through-electrode TSV. Each of the through-electrodes TSV is electrically separated from the substrate W2 by the insulator SP.

[0069] The transistors Tr2 are arranged on the side of the first surface F1 of the substrate W2. Each of the transistors Tr2 includes a gate insulator on the upper surface of the substrate W2, a gate electrode on the upper surface of the gate insulator, and a region (source/drain region) of one pair of a source and a drain sandwiching a region below the gate electrode. Each of the transistors Tr2 is electrically connected to any of semiconductor layers SM of memory pillars MP. Accordingly, the transistors Tr2 of the second structure 200 constitute the sense amplifier 17 that detects data stored in memory cells via the associated semiconductor layers SM of the memory pillars MP.

[0070] Each contact C7 is in contact on the lower surface with the upper surface of the gate electrode of one transistor Tr2. Each contact CS2 is in contact on the lower surface with one source/drain region. Each contact CS5 is in contact on the lower surface with the upper surface of one through-electrode TSV.

[0071] Each conductor L4 is in contact on the lower surface with the upper surface of one contact C7, CS2, or CS5. Each contact C8 is in contact on the lower surface with the upper surface of one conductor L4.

[0072] Each conductor L5 is in contact on the lower surface with the upper surface of one contact C8. Each contact C9 is in contact on the lower surface with the upper surface of one conductor L5.

[0073] Each conductor L6 is in contact on the lower surface with the upper surface of one contact C9. Each contact C10 is in contact on the lower surface with the upper surface of one conductor L6.

[0074] A set of the transistor Tr2, the contacts CS2, CS5, C4, C5, C7, C8, C9, and C10, and the conductors L3, L4, L5, and L6 realizes a circuit included in the second structure 200. Therefore, the second structure 200 has any shapes and arrangement of the transistors Tr2, the contacts CS2, CS5, C4, C5, C7, C8, C9, and C10, and the conductors L3, L4, L5, and L6 realizing circuits included in the second structure 200.

[0075] The insulator 26 extends from the level of the upper surface of the substrate W2 to the level of the upper surfaces of the contacts C10. The insulator 26 fills a region where constituent elements are not arranged in a region from the level of the upper surface of the substrate W2 to the level of the upper surfaces of the contacts C10, that is, a region where the transistors Tr2, the contacts CS2, CS5, C7, C8, C9, and C10, and the conductors L4, L5, and L6 are not arranged.

[0076] Each joint terminal BP2U is in contact on the lower surface with the upper surface of one contact C10. The insulator 27 fills a region where the joint terminals BP2U are not located in a layer where the joint terminals BP2U are positioned.

[0077] The third structure 300 further includes contacts C11, C12, and C13, conductors L7, L8, 31, 33, 36, and 38, insulators 29, 34, 35, 37, 40, and 41, and memory pillars MP.

[0078] Each joint terminals BP3 is positioned in the lowermost layer of the third structure 300. The insulator 29 fills a region where the joint terminals BP3 are not located in the layer where the joint terminals BP3 are positioned.

[0079] Each contact C11 is in contact on the lower surface with the upper surface of one joint terminal BP3.

[0080] Each conductor L7 is in contact on the lower surface with the upper surface of one contact C11. Each contact C12 is in contact on the lower surface with the upper surface of one conductor L7.

[0081] Each conductor L8 is in contact on the lower surface with the upper surface of one contact C12.

[0082] The conductor 31 is positioned above the conductors L8. The conductor 31 has a plate-like shape along the XY plane. The conductor 31 functions as at least a part of a selection gate line SGDL. The lower surface of the conductor 31 is exposed and has a stepped terrace at ends.

[0083] The insulator 32 is positioned on the upper surface of the conductor 31. The insulator 32 has a plate-like shape along the XY plane.

[0084] The conductors 33 and the insulators 34 are stacked alternately one by one in the Z direction on the upper surface of the insulator 32 to constitute a stacked body. The conductors 33 and the insulators 34 each have a plate-like shape along the XY plane. Each conductor 33 functions as at least a part of a word line WL. FIG. 5 illustrates an example where n=8, that is, the number of memory cell transistors MT is eight. The conductors 33 function as at least a part of word lines WL0, WL1, WL2, WL3, WL4, WL5, WL6, and WL7 in this order from the lowermost one, respectively. The lower surface of each conductor 33 is exposed and has a stepped terrace at ends.

[0085] The insulator 35 is positioned on the upper surface of the uppermost conductor 33.

[0086] The conductor 36 is positioned on the upper surface of the insulator 35. The conductor 36 functions as at least a part of a selection gate line SGSL.

[0087] The insulator 37 is positioned on the upper surface of the conductor 36. The conductor 38 is positioned on the upper surface of the insulator 37. The lower surface of the conductor 38 is exposed and has a terrace at ends. The conductor 38 functions as, for example, a source layer.

[0088] The memory pillars MP extend along a Z-axis and penetrate through the stacked body including the conductors 31, 33, and 36 and the insulators 32, 34, 35, and 37. Each memory pillar MP includes an insulator CI, the semiconductor layer SM, and a memory film SS penetrating through the stacked body. The semiconductor layer SM covers the side surface of the insulator CI. The memory film SS covers the side surface of the semiconductor layer SM and is located between the semiconductor layer SM and the stacked body. The memory film SS is open at the upper end of the associated memory pillar MP. A part of the semiconductor layer SM is positioned in the opening and is in contact on the upper surface with the conductor 38.

[0089] It is also possible that an upper part of each of the memory pillars MP is positioned in the conductor 38, the memory film SS is open at a portion facing the conductor 38, and a part of the conductor 38 is positioned in the opening.

[0090] A portion facing the conductor 31 in each memory pillar MP functions as one selection gate transistor DT. A portion facing a conductor 33 in each memory pillar MP functions as one memory cell transistor MT. That is, each of the memory pillars MP constitutes a memory cell at an intersecting portion with one of the conductors 33. A portion facing the conductor 36 in each memory pillar MP functions as one selection gate transistor ST. The lower surface of the semiconductor layer SM is exposed on the lower surface of each memory pillar MP. The upper surface of the semiconductor layer SM is exposed on the upper surface of each memory pillar MP. As described above, the third structure 300 is constituted as an array chip including a memory cell array.

[0091] Each contact C13 is in contact on the lower surface with the upper surface of one conductor L8. Each of some contacts C13 is in contact on the upper surface with the lower surface of the semiconductor layer SM of one memory pillar MP. Each of some contacts C13 is in contact on the upper surface with the lower surface of one terrace portion of the conductors 31, 33, and 36.

[0092] The insulator 40 extends from the level of the upper surface of the insulator 29 to the level of the upper surface of the conductor 38. The insulator 40 fills a region where constituent elements are not arranged in the third structure 300, that is, a region where the contacts C11, C12, and C13, the conductors L7, L8, 31, 33, 36, and 38, the insulators 40, 32, 34, 35, and 37, and the memory pillars MP are not arranged.

[0093] The insulator 41 is positioned on the upper surfaces of the conductor 38 and the insulator 40.

[0094] FIG. 6 is a sectional view illustrating a configuration example of a memory pillar of the storage device according to the first embodiment. FIG. 6 illustrates a cross-sectional structure of a memory pillar along the XY plane. In one example, the memory film SS includes a tunnel insulator TI, a charge accumulation film CA, and a block insulator BI.

[0095] The tunnel insulator TI surrounds the side surface of the semiconductor layer SM. The charge accumulation film CA surrounds the side surface of the tunnel insulator TI. The block insulator BI surrounds the side surface of the charge accumulation film CA. The conductor 31, 33, or 36 surrounds the side surface of the block insulator BI.

[0096] The semiconductor layer SM functions as channels (current paths) of the memory cell transistors MT and the selection gate transistors DT and ST. In one example, each of the tunnel insulator TI and the block insulator BI includes silicon oxide. The charge accumulation film CA accumulates charges therein. In one example, the charge accumulation film CA includes silicon nitride.

[0097] FIG. 7 is a sectional view illustrating a configuration example of the second structure according to the first embodiment. FIG. 7 illustrates a structure of the substrate W2 of the second structure 200 and a peripheral part thereto.

[0098] The second structure 200 further includes shallow trench isolation parts STI, n-well regions nw, and p-well regions pw. The numbers of the p-well regions pw and the n-well regions nw are not limited to specific values.

[0099] The substrate W2 includes p-type impurities. examples of the p-type impurities include boron (B).

[0100] Each of the n-well regions nw is positioned between adjacent two of the shallow trench isolation parts STI. The n-well regions nw spread from the upper surface of the substrate W2 to the lower surface thereof. The n-well regions nw include n-type impurities. Examples of the n-type impurities include phosphorus (P) and arsenic (As).

[0101] Each of the p-type well regions pw is positioned between adjacent two of the shallow trench isolation parts STI. The p-well regions pw spread from the upper surface of the substrate W2 to the lower surface thereof. The p-well regions pw include p-type impurities. In one example, the p-well regions pw include p-type impurities of a concentration equal to or higher than 1×10¹⁴ [atoms/cm³] and equal to or lower than 2×10¹⁶ [atoms/cm³] in a region including a boundary with the insulator 25. In one example, the concentration of the impurities is an average concentration.

[0102] Each of the shallow trench isolation parts STI is arranged between adjacent ones of a plurality of transistors Tr2_p and Tr2_n and penetrates through the substrate W2 in the Z direction. Each of the shallow trench isolation parts STI includes a first isolation part STIa and a second isolation part STIb.

[0103] The first isolation part STIa extends in the-Z direction from the first surface F1 of the substrate W2 toward the second surface F2 thereof. That is, the first isolation part STIa is formed in the −Z direction from the first surface F1 toward the second surface F2. Therefore, the width of the first isolation part STIa in the XY plane decreases from the first surface F1 toward the second surface F2 in the −Z direction. The area of the first isolation part STIa in the XY plane decreases from the first surface F1 toward the second surface F2 in the −Z direction. That is, the side surface of the first isolation part STIa tapers in such a manner as to approach the center of the first isolation part STIa in the −Z direction.

[0104] The second isolation part STIb extends in the +Z direction from the second surface F2 of the substrate W2 toward the first surface F1. That is, the second isolation part STIb is formed in the +Z direction from the second surface F2 toward the first surface F1. Therefore, the width of the second isolation part STIb in the XY plane decreases from the second surface F2 toward the first surface F1 in the +Z direction. The area of the second isolation part STIb in the XY plane decreases from the second surface F2 toward the first surface F1 in the +Z direction. That is, the side surface of the second isolation part STIb tapers in such a manner as to approach the center of the second isolation part STIb in the +Z direction.

[0105] Each of the second isolation parts STIb is positioned below (in the −Z direction) one of the first isolation parts STIa in the substrate W2. The second isolation part STIb is in contact with the lower surface of the first isolation part STIa and reaches the second surface F2 of the substrate W2. The first and second isolation parts STIa and STIb (the shallow trench isolation part STI) are in contact with adjacent two of the n-well regions nw and the p-well regions pw and electrically isolate these adjacent two regions from each other. The second isolation part STIb is constituted of, for example, an insulating material such as a silicon dioxide material. The first isolation part STIa is formed from the side of the first surface F1 of the substrate W2 while the second isolation part STIb is formed from the side of the second surface F2 of the substrate W2. Therefore, the side surfaces of the first isolation part STIa and the second isolation part STIb are inclined in opposite directions to each other. That is, the side surfaces of the first isolation part STIa and the second isolation part STIb are inverse tapers with respect to each other. The first isolation part STIa and the second isolation part STIb are connected to each other in the substrate W2 between the first surface F1 and the second surface F2.

[0106] As described above, each of the first isolation parts STIa and the associated second isolation part STIb are formed in the opposite directions to each other from the first surface F1 and the second surface F2, respectively, and are in contact with each other on a contact face Fcnt between the first surface F1 and the second surface F2. Therefore, each of the shallow trench isolation parts STI as a whole penetrates through the substrate W2 in the Z direction. The shallow trench isolation parts STI are constituted of an insulating material such as silicon oxide, as an example. Accordingly, each of the shallow trench isolation parts STI electrically isolates adjacent ones of the n-well regions nw and the p-well regions pw from each other.

[0107] The transistors Tr2 include p-type transistors Tr2_p and n-type transistors Tr2_n. The transistors Tr2_p and Tr2_n are MOSFETs constituting the CMOS described above. The transistors Tr2_p and Tr2_n can be constituted of an LV (Low Voltage) transistor having a relatively low threshold voltage and a VLV (Very Low Voltage) transistor having a lower threshold voltage. In this case, the n-well regions nw and the p-well regions pw are formed to have relatively low impurity concentrations. Therefore, the p-well regions pw (or the n-well regions nw) are in a state of being easily inverted by a voltage of the conductors L3. However, since each of the shallow trench isolation parts STI electrically isolates adjacent ones of the n-well regions nw and the p-well regions pw in the present embodiment, a leak current between adjacent n-well regions nw or between adjacent p-well regions pw can be suppressed.

[0108] Each of the transistors Tr2_p is arranged in an active area between adjacent two of the shallow trench isolation parts STI. Each of the transistors Tr2_p is positioned in an n-well region nw and above the n-well region nw. Each of the transistors Tr2_p includes a gate insulator GO, a gate electrode GC, and a region (source/drain region) SD_p of one pair of a source and a drain. The gate insulator GO is positioned on the upper surface of the substrate W2. In one example, the gate insulator GO includes silicon oxide. The gate electrode GC is positioned on the upper surface of the gate insulator GO. In one example, the gate electrode GC includes polysilicon that has a conductive property due to implantation of impurities. The source/drain region SD_p sandwiches a portion of a region including the upper surface of the substrate W2 below the gate electrode GC. The source/drain region SD_p includes p-type impurities.

[0109] Each of the transistors Tr2_n is arranged in an active area between adjacent two of the shallow trench isolation parts STI. Each of the transistors Tr2_n is positioned in a p-well region pw and above the p-well region pw. Each of the transistors Tr2_n includes a gate insulator GO, a gate electrode GC, and a region (source/drain region) SD_n of one pair of a source and a drain. The source/drain region SD_n sandwiches a portion of a region including the upper surface of the substrate W2 below the gate electrode GC. The source/drain region SD_n includes n-type impurities.

[0110] The side surface of each of the contacts CS2, CS5, and C7 has a tapered shape similarly to the first isolation parts STIa. The area of each of the contacts CS2, CS5, and C7 in the XY plane is larger at the upper end than at the lower end, and decreases from the upper end to the lower end (in the −Z direction) in one example.

[0111] Each of the through-electrodes TSV, the insulators SP, and the contacts C5 has an inverse tapered shape similarly to the second isolation parts STIb. The area of each of the through-electrodes TSV, the insulators SP, and the contacts C5 in the XY plane is smaller at the upper end than at the lower end, and increases from the upper end to the lower end (in the −Z direction) in one example.

[0112] A manufacturing method of the storage device 1 according to the first embodiment is described next.

[0113] A manufacturing process of the storage device 1 includes a process of individually manufacturing the first structure 100, the second structure 200, and the third structure 300, and a process of bonding the manufactured first, second, and third structures 100, 200, and 300 to each other. A manufacturing method of the second structure 200 according to the present embodiment is described below.

[0114] FIGS. 8 to 16 are sectional views illustrating one example of the manufacturing method of the second structure of the storage device according to the first embodiment.

[0115] As illustrated in FIG. 8, the n-well regions nw and the p-well regions pw are formed on the substrate W2 using a lithography technique and an ion implantation technique. The substrate W2 is, for example, a semiconductor substrate such as a silicon substrate. The n-well regions nw are formed, for example, by implanting n-type impurities such as phosphorus (P) or arsenic (As) from the first surface F1. The p-well regions pw are formed, for example, by implanting p-type impurities such as boron (B) from the first surface F1. The n-well regions nw and the p-well regions pw are formed adjacently to each other.

[0116] Either the n-well regions nw or the p-well regions pw can be formed first.

[0117] Next, as illustrated in FIG. 9, the source/drain regions SD_n and SD_p are formed on the substrate W2 using a lithography technique and an ion implantation technique. The source/drain regions SD_n are formed, for example, by implanting n-type impurities such as phosphorus (P) or arsenic (As) in the p-well regions pw from the first surface F1. The source/drain regions SD_p are formed, for example, by implanting p-type impurities such as boron (B) in the n-well regions nw from the first surface F1.

[0118] Either the source/drain regions SD_n or SD_p can be formed first.

[0119] Next, a material for a hard mask 52 is deposited on the first surface F1 of the substrate W2. The material for the hard mask 52 in the formation region for the first isolation parts STIa is selectively removed using a lithography technique and an etching technique.

[0120] Next, the substrate W2 is etched from the first surface F1 toward the second substrate F2 by an etching technique such as an RIE (Reactive Ion Etching) method or the like using the hard mask 52 as a mask. Accordingly, trenches 51 are formed in the formation region for the first isolation parts STIa. That is, each of the trenches 51 is formed from the first surface F1 toward the second surface F2 in a boundary region between an adjacent p-well region pw and an adjacent n-well region nw as illustrated in FIG. 10.

[0121] The trenches 51 are formed in the-Z direction from the first surface F1 of the substrate W2 toward the second surface F2. Therefore, the width of each of the trenches 51 in the XY plane decreases from the first surface F1 toward the second surface F2 in the-Z direction. The area of each of the trenches 51 in the XY plane decreases from the first surface F1 toward the second surface F2 in the-Z direction. That is, the side surface of each of the trenches 51 tapers in such a manner as to approach the center of the trench 51 in the-Z direction.

[0122] Next, an insulating material for the first isolation parts STIa is deposited on the substrate W2 using a CVD (Chemical Vapor Deposition) method or the like, and is polished using a CMP (Chemical Mechanical Polishing) method or the like. The first isolation parts STIa are thereby formed in the trenches 51 as illustrated in FIG. 11.

[0123] Each of the first isolation parts STIa has a shape along the shape of the trenches 51. That is, each of the first isolation parts STIa extends in the −Z direction from the first surface F1 of the substrate W2 toward the second surface F2. The width of each of the first isolation parts STIa in the XY plane decreases from the first surface F1 toward the second surface F2 in the −Z direction. The area of each of the first isolation parts STIa in the XY plane decreases from the first surface F1 toward the second surface F2 in the −Z direction. That is, the side surface of each of the first isolation parts STIa tapers in such a manner as to approach the center of the associated trench 51 in the-Z direction.

[0124] Next, after the hard mask 52 is removed, the gate insulators GO, the gate electrodes GC, sidewall insulators SW, the insulator 26, and the contacts CS2, CS5, and C7 are formed as illustrated in FIG. 12.

[0125] For example, the gate insulators GO can be formed by a thermal oxidation method. The gate electrodes GC can be formed, for example, by depositing a material for the gate electrodes GC by the CVD method and subsequently processing the material using a photolithography process and anisotropic etching. The sidewall insulators SW can be formed by depositing a material for the sidewall insulators SW by the CVD method and subsequently anisotropically etching back the material.

[0126] Next, the insulator 26 is deposited on a structure of the gate electrodes GC and the like.

[0127] Next, contact holes for the contacts CS2, CS5, and C7 are formed using a lithography technique and an etching technique. Next, a conductive material is filled in the contact holes, whereby the contacts CS2, CS5, and C7 are formed.

[0128] Next, the second surface F2 of the substrate W2 is polished using the CMP method or the like as illustrated in FIG. 13. At that time, the third structure 300 formed separately from the second structure is bonded to the insulator 26 on the side of the first surface F1 of the substrate W2. A support substrate may be bonded instead of the third structure 300. FIG. 13 illustrates a structure obtained by vertically inverting the structure illustrated in FIG. 12 in the Z direction.

[0129] Next, the substrate W2 is etched from the second surface F2 toward the first surface F1 using a lithography technique and an etching technique such as the RIE method. Trenches 53 are thereby formed in the formation region for the second isolation parts STIb. That is, each of the trenches 53 is formed in the +Z direction from the second surface F2 toward the first surface F1 in a boundary region between an adjacent p-well region pw and an adjacent n-well region nw as illustrated in FIG. 14.

[0130] The trenches 53 are formed in the +Z direction from the second surface F2 of the substrate W2 toward the first surface F1. Therefore, the width of each of the trenches 53 in the XY plane decreases from the second surface F2 toward the first surface F1 in the +Z direction. The area of each of the trenches 53 in the XY plane decreases from the second surface F2 toward the first surface F1 in the +Z direction. That is, the side surface of each of the trenches 53 tapers in such a manner as to approach the center of the trench 53 in the +Z direction.

[0131] Next, an insulating material for the second isolation parts STIb is deposited on the substrate W2 using the CVD method or the like, and the material for the second isolation parts STIb is polished using the CMP method or the like. The second isolation parts STIb are thereby formed in the trenches 53 as illustrated in FIG. 15.

[0132] Each of the second isolation parts STIb has a shape along the shape of the trenches 53. That is, each of the second isolation parts STIb extends in the +Z direction from the second surface F2 of the substrate W2 toward the first surface F1. The width of each of the second isolation parts STIb in the XY plane decreases from the second surface F2 toward the first surface F1 in the +Z direction. The area of each of the second isolation parts STIb in the XY plane decreases from the second surface F2 toward the first surface F1 in the +Z direction. That is, the side surface of each of the second isolation parts STIb tapes in such a manner as to approach the center of the associated trench 53 in the +Z direction.

[0133] When each of the second isolation parts STIb is in contact with a portion of the bottom part of the associated first isolation part STIa, the shallow trench isolation part STI can penetrate through the substrate W2 and isolate an n-well region nw and a p-well region pw from each other. Therefore, alignment in the formation process of the trenches 53 can be lower in the accuracy than that of alignment of other lines (for example, bit lines and word lines). Therefore, the second isolation parts STIb can be relatively easily formed. Since the first isolation parts STIa are formed from the first surface F1 of the substrate W2 and the second isolation parts STIb are formed from the second surface F2, the aspect ratios of the trenches 51 and 53 can be lower than that of one trench penetrating through the substrate W2. Accordingly, the trenches 51 and 53 can be relatively easily formed using the RIE method.

[0134] Next, the insulator 25 is deposited on the second surface F2 of the substrate W2.

[0135] Next, through-holes 54 penetrating through the insulator 25 and the substrate W2 are formed using a lithography technique and an etching technique as illustrated in FIG. 16. Each of the through-holes 54 extends from the second surface F2 of the substrate W2 to the first surface F1 thereof to reach a contact CS5. Since the through-holes 54 are formed in the +Z direction from the second surface F2 of the substrate W2 to the first surface F1, the width of each of the through-holes 54 in the XY plane decreases from the second surface F2 toward the first surface F1 in the +Z direction. The area of each of the through-holes 54 in the XY plane decreases from the second surface F2 toward the first surface F1 in the +Z direction. That is, the side surface of each of the through-holes 54 tapers in such a manner as to approach the center of the through-hole 54 in the +Z direction.

[0136] Next, as illustrated in FIG. 17, an insulator SP (for example, a spacer film) is formed on the inner wall of each of the through-holes 54. Next, the insulator SP at a bottom part of each of the through-holes 54 is removed by etching back to expose the upper surface of the associated contact CS5 at the bottom part of the through-hole 54. Next, a material (for example, tungsten) for the through-electrodes TSV is formed in the inner side of each of the insulators SP. Each of the through-holes TSV is thereby formed to be electrically connected to the conductors L3 in a state where the through-holes TSV are electrically separated from the substrate W2 as illustrated in FIG. 17.

[0137] Subsequently, the insulator 25 is further deposited above the second surface F2 of the substrate W2, and the contacts C5 and the conductors L3 are formed. Furthermore, the insulator 24, the contacts C4, the joint terminals BP2L (see FIG. 5), and the like are formed. The second structure 200 is thereby obtained.

[0138] Subsequently, the first structure 100 manufactured separately from the second structure 200 is bonded to the second structure 200 on the side of the second surface F2. In a case where the support substrate has been bonded to the second structure 200 on the side of the first surface F1, the support substrate is detached and the third structure 300 is bonded to the second structure 200 on the side of the first surface F1. By dicing the bonded first to third structures 100 to 300, the structures are singulated into semiconductor chips including the first to third structures 100 to 300. The storage device 1 according to the present embodiment is thereby completed.

[0139] According to the first embodiment, the first isolation part STIa and the second isolation part STIb constituting each of the shallow trench isolation parts STI are provided between an n-well region nw and a p-well region pw. The first isolation part STIa and the second isolation part STIb are formed from the first surface F1 and the second surface F2, respectively, and are connected to each other between the first surface F1 and the second surface F2. Therefore, each of the shallow trench isolation parts STI as a whole penetrates through the substrate W2 in the Z direction. The shallow trench isolation parts STI are constituted of, for example, an insulating material such as silicon oxide. Accordingly, each of the shallow trench isolation parts STI physically and electrically separate adjacent ones of the n-well regions nw and the p-well regions pw from each other. Therefore, a leak current between n-well regions nw or between p-well regions pw, or a leak current between the transistors Tr2_n and Tr2_p can be suppressed more reliably.

[0140] For example, in a case where the first to third structures 100 to 300 are stacked as illustrated in FIG. 5, there is a case where a conductor L3 connected to the first or third structure 100 or 300 via a through-electrode TSV is arranged near the substrate W2 in the second structure 200. When a high voltage (for example, 30V) is applied to such a conductor L3, an inverted layer is sometimes formed on the second surface F2 of p-well regions pw. In the present embodiment, the first and second isolation parts STIa and STIb are provided between each of the p-well regions pw and an adjacent n-well region nw. Therefore, even when such an inverted layer is formed in p-well regions pw, a leak current is unlikely to flow between adjacent n-well regions nw. When a low voltage is applied to the conductor L3, an inverted layer is formed on the second surface F2 of n-well regions nw. In the present embodiment, the first and second isolation parts STIa and STIb are provided between each of the p-well regions pw and an adjacent n-well region nw. Therefore, even when an inverted layer is formed in n-well regions nw, a leak current is unlikely to flow between adjacent p-well regions pw. In this way, the storage device 1 according to the present embodiment can suppress a leak current.

[0141] FIG. 18 is a sectional view illustrating a configuration example of a second structure according to a second embodiment. In the second embodiment, an impurity layer pw2 is provided on each of the p-well regions pw on the side of the second surface F2. The impurity layers pw2 are higher in the p-type impurity concentration (for example, the boron concentration) than that of the p-well regions pw on the side of the first surface F1. For example, the impurity concentration of the impurity layers pw2 is equal to or higher than 5.0×10¹⁶ atoms/cm³. Therefore, even when a high voltage is applied to the conductors L3, the impurity layers pw2 are less likely to be inverted. Accordingly, the storage device 1 according to the second embodiment can suppress a leak current more reliably.

[0142] An n-type impurity layer may be provided on each of the n-well regions nw on the side of the second surface F2 assuming that a negative voltage is applied to the conductors L3. In this case, the n-type impurity layers are higher in the n-type impurity concentration than that of the n-well regions nw on the side of the first surface F1. Therefore, even when a low voltage is applied to the conductors L3, the n-well regions nw are less likely to be inverted. A leak current between adjacent p-well regions pw may be suppressed in this way.

[0143] FIG. 19 is a sectional view illustrating a configuration example of a storage device according to a third embodiment. In the third embodiment, instead of the conductors L3, conductors L10 that face the p-well regions pw and transmit a positive high voltage are positioned in the first structure 100.

[0144] The second structure 200 does not include the conductors L3 and the contacts C4. Meanwhile, the first structure 100 further includes the conductors L10 and contacts C15.

[0145] Each of the contacts C5 is in contact on the lower surface on the side of the second surface F2 with the upper surface of a joint terminal BP2L. Each contact C3 is in contact on the upper surface with the lower surface of one conductor L10. Each contact C15 is in contact on the lower surface with the upper surface of one conductor L10. Each contact C15 is in contact on the upper surface with the lower surface of one joint terminal BP1. The conductors L10 can receive a positive high voltage or a negative high voltage similarly to the conductors L3. Therefore, when the thickness of the insulator 25 and the thickness of a portion of the insulator 21 upper than the upper surfaces of the conductors L10 are small and the conductors L10 are close to the substrate W2, there is a risk that the p-well regions pw are inverted.

[0146] However, in the third embodiment, similarly in the first or second embodiment, the first isolation part STIa and the second isolation part STIb are provided between each of the n-well regions nw and an adjacent p-well region pw. Accordingly, the third embodiment can obtain the same effects as those of the first or second embodiment.

[0147] The foregoing descriptions are based on the examples in which the semiconductor device of the embodiments described above is a storage device. The embodiments described above are applicable to structures that are bonded to each other and that include the transistors Tr2 and the conductors L3 (or L10) as the first structure 100 and the second structure 200. Examples of such other semiconductor devices include an image sensor and ICs (Integrated Circuits). In this case, the third structure 300 is not provided. Alternatively, the third structure 300 has semiconductor elements other than a memory cell array.

[0148] While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.