SEMICONDUCTOR PACKAGE

[0001] This application is a Continuation of U.S. Patent Application No. 17/813,362, filed on Jul. 19, 2022, which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0131968, filed on Oct. 5, 2021, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties.

[0002] The present inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package including a laser mark.

[0003] A laser mark indicating product information may be marked on a surface of a semiconductor package including a semiconductor chip. As semiconductor packages are becoming thinner, it may be difficult to form a laser mark without damage to the semiconductor package. For example, during the formation of a laser mark with a laser on a semiconductor package, heat is generated, and may damage the semiconductor package. In addition, a laser mark needs to have good visibility to be easily recognized by a user. However, in many instances, the laser used in forming the laser mark may be reflected at the surface of the semiconductor package, or transmitted right through the semiconductor package, and thus, forming the laser mark may be difficult, and the visibility of the laser mark formed may be relatively low.

[0004] The present inventive concept provides a semiconductor package including a laser mark that has visibility without package damage.

[0005] According to an embodiment of the present inventive concept, there is provided a semiconductor package including: an encapsulation layer sealing at least one semiconductor chip; a redistribution level layer arranged on the encapsulation layer; a laser mark metal layer arranged on the redistribution level layer; and a laser mark arranged inside the laser mark metal layer.

[0006] According to an embodiment of the present inventive concept, there is provided a semiconductor package including: a fan-in region in which a semiconductor chip is located, and a fan-out region surrounding the fan-in region and including a package element including an inner wiring layer; a package body level layer including an encapsulation layer sealing the semiconductor chip in the fan-in region and the inner wiring layer in the fan-out region; a first redistribution level layer arranged on a lower surface of the package body level layer and including a first redistribution layer and a first redistribution insulating layer, in which the first redistribution layer extends from the fan-in region to the fan-out region, and the first redistribution insulating layer insulates the first redistribution layer; a second redistribution level layer arranged on an upper surface of the package body level layer and including a second redistribution layer and a second redistribution insulating layer, in which the second redistribution layer extends from the fan-in region to the fan-out region and the second redistribution insulating layer insulates the second redistribution layer; a laser mark metal layer arranged on the second redistribution level layer; and a laser mark arranged inside the laser mark metal layer.

[0007] According to an embodiment of the present inventive concept, there is provided a semiconductor package including: a fan-in region in which a semiconductor chip is located, and a fan-out region surrounding the fan-in region and including an inner wiring layer; a package body level layer including an encapsulation layer sealing the semiconductor chip in the fan-in region and the inner wiring layer in the fan-out region; a first redistribution level layer arranged on a lower surface of the package body level layer and including a first redistribution layer and a first redistribution insulating layer, in which the first redistribution layer extends from the fan-in region to the fan-out region and the first redistribution insulating layer insulates the first redistribution layer; a second redistribution level layer arranged on an upper surface of the package body level layer and including a second redistribution layer and a second redistribution insulating layer, in which the second redistribution layer extends from the fan-in region to the fan-out region and the second redistribution insulating layer insulates the second redistribution layer; a laser mark metal layer arranged on the second redistribution level layer in the fan-in region and configured to have a plurality of sub-metal layers; and a laser mark arranged inside the laser mark metal layer.

[0023] Hereinafter, embodiments of the present inventive concept will be described in detail with reference to the accompanying drawings. Embodiments of the present inventive concept may be implemented as one of them, and also, the embodiments described below may be implemented by combining at least two of the embodiments. Therefore, the present inventive concept shall not be interpreted by limiting the same to a single embodiment.

[0024] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0025] FIG. 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present inventive concept.

[0026] In detail, FIG. 1 illustrating a semiconductor package PK1 may be a cross-sectional view in XZ direction (e.g., XZ plane), that is, in an X-direction and a Z-direction. The semiconductor package PK1 may be a fan-out semiconductor package. For example, the semiconductor package PK1 may be a fan-out wafer level-package (FOWLP) type, which is an enhancement of standard wafer-level packaging (WLP) solutions.

[0027] The semiconductor package PK1 may include a fan-in region FI in which a semiconductor chip 22 is located and a fan-out region FO on both sides of the fan-in region FI. The fan-out region FO may surround the fan-in region FI on a plane. While the semiconductor chip 22 is described as a single chip in FIG. 1, the present inventive concept is not limited thereto. For example, in an embodiment of the present inventive concept, the semiconductor chip 22 may include a plurality of stacked chips.

[0028] The semiconductor chip 22 may include, for example, a logic chip, a power management integrated circuit (PMIC) chip, or a memory chip. In an embodiment of the present inventive concept, the logic chip may include, for example, a memory controller chip, a central processing unit (CPU) chip, a graphic processing unit (GPU) chip, a field programmable gate array (FPGA) chip, a digital signal processor (DSP) chip, an application specific integrated circuit (ASIC) chip, or an application processor (AP) chip.

[0029] In an embodiment of the present inventive concept, the memory chip may include, for example, a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a flash memory chip, an electrically erasable and programmable read-only memory (EEPROM) chip, a phase-change random access memory (PRAM) chip, a magnetic random access memory (MRAM) chip, ferroelectric random access memory (FeRAM) chip, or a resistive random access memory (RRAM) chip.

[0030] The semiconductor chip 22 may include a front surface 22a and a rear surface 22b positioned opposite to the front surface 22a. The front surface 22a may be an active surface, and the rear surface 22b may be a non-active surface. A chip solder ball 24 is arranged on the front surface 22a, and may include a chip connection ball or a chip connection bump. For example, chip solder ball 24 may include a solder material, such as one or more of, for example, tin (Sn), silver (Ag), zinc (Zn), lead (Pb), and any alloy thereof.

[0031] The fan-out region FO may include a package element FE1 including an inner wiring layer 20. The inner wiring layer 20 may include a metal post layer, for example, a copper (Cu) post layer. In an embodiment of the present inventive concept, the inner wiring layer 20 may have a pillar shape, and may include metal, such as one or more of, for example, copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), and any alloy thereof. The inner wiring layer 20 may be a metal via layer. The package element FE1 may further include a fan-out encapsulation layer 26b sealing the inner wiring layer 20. The fan-out encapsulation layer 26b may include an epoxy molding compound (EMC), but the material of the fan-out encapsulation layer 26b is not particularly limited. For example, any other suitable thermosetting resin or thermoplastic resin may be used as the fan-out encapsulation layer 26b.

[0032] The semiconductor chip 22 of the fan-in region FI may be sealed by a fan-in encapsulation layer 26a. In an embodiment of the present inventive concept, the fan-in encapsulation layer 26a may seal at least one semiconductor chip. For example, the fan-in encapsulation layer 26a may seal the single semiconductor chip 22 as illustrated in FIG. 1, or may seal a plurality of semiconductor chips. The fan-in encapsulation layer 26a may be in a single body with the fan-out encapsulation layer 26b constituting the package element FE1. The fan-in encapsulation layer 26a may include a material the same as that of the fan-out encapsulation layer 26b constituting the package element FE1.

[0033] The semiconductor chip 22 in the fan-in region FI, the fan-in encapsulation layer 26a sealing the semiconductor chip 22 in the fan-in region FI, and the package element FE1 including the inner wiring layer 20 and the fan-out encapsulation layer 26b in the fan-out region FO may constitute a package body level layer FBD1.

[0034] The semiconductor package PK1 may include a first redistribution level layer RDL1 and a second redistribution level layer RDL2. As the first redistribution level layer RDL1 is formed on the front surface 22a of the semiconductor chip 22, the first redistribution level layer RDL1 may be referred to as a front surface redistribution level layer. As the second redistribution level layer RDL2 is formed on the rear surface 22b of the semiconductor chip 22, the second redistribution level layer RDL2 may be referred to as a rear surface redistribution level layer. The second redistribution level layer RDL2 may not be directly in physical contact with the rear surface 22b of the semiconductor chip 22, but the present inventive concept is not limited thereto. For example, the second redistribution level layer RDL2 may be directly in physical contact with a top surface of the fan-out encapsulation layer 26b and the rear surface 22b of the semiconductor chip 22.

[0035] The first redistribution level layer RDL1 may be arranged on a lower surface of the package body level layer FBD1 and include a first redistribution layer 12 extending from the fan-in region FI to the fan-out region FO, and a first redistribution insulating layer 10 that insulates the first redistribution layer 12. The first redistribution layer 12 may be formed of a metal layer including, for example, copper (Cu), aluminum (Al), nickel (Ni), titanium (Ti), or an alloy thereof. The first redistribution layer 12 may be formed of a single layer or multiple layers of the metal material described above.

[0036] The first redistribution insulating layer 10 may include a dielectric layer. The first redistribution insulating layer 10 may include an organic polymer including, for example, polybenzoxazole (PBO), benzocyclobutene (BCB), polyimide (PI), or the like. Alternatively, the organic polymer included in the first redistribution insulating layer 10 may include a photo-imageable dielectric (PID) material such as, for example, photosensitive polyimide (PSPI). The first redistribution insulating layer 10 may include an inorganic material such as, for example, silicon oxide (SiO₂), silicon nitride (Si₃N₄), or silicon oxynitride (SiON).

[0037] The first redistribution level layer RDL1 may include, on a lower side thereof, a first redistribution pad 14 electrically connected to the first redistribution layer 12. The first redistribution pad 14 may include a metal layer, for example, a copper (Cu) layer, a nickel (Ni) layer or a gold (Au) layer.

[0038] In FIG. 1, for convenience, the first redistribution pad 14 is illustrated as being included in the first redistribution level layer RDL1, but the present inventive concept is not limited thereto. For example, the first redistribution pad 14 may also be formed on the first redistribution level layer RDL1. In other words, the first redistribution pad 14 may be formed on a bottom surface of the first redistribution level layer RDL1, and may not be located inside the first redistribution level layer RDL1. A first solder ball 16 may be arranged on the first redistribution pad 14. The first solder ball 16 may be an external connection terminal for connection to an external device. For example, the external device may be electrically connected to the first redistribution level layer RDL1 through the first solder ball 16, for example, electrically connected to the first redistribution layer 12 and the first redistribution pad 14 through the first solder ball 16.

[0039] The first redistribution level layer RDL1 may include, on an upper side thereof, a chip connection pad 18 and a post connection pad 19 that are electrically connected to the first redistribution layer 12. The chip connection pad 18 and the post connection pad 19 may include a metal layer, such as, for example, a copper (Cu) layer or an aluminum (Al) layer.

[0040] In an embodiment of the present inventive concept, the chip connection pad 18 and the post connection pad 19 may be formed on the first redistribution insulating layer 10 of the first redistribution level layer RDL1 and thus included in the package body level layer FBD1. In an embodiment of the present inventive concept, the chip connection pad 18 and the post connection pad 19 may be formed inside the first redistribution insulating layer 10 and thus included in the first redistribution level layer RDL1. The chip connection pad 18 may be electrically connected to the chip solder ball 24 of the semiconductor chip 22. For example, the chip connection pad 18 may be provided to electrically connect the semiconductor chip 22 to other components, for example, to an external power source. The post connection pad 19 may be electrically connected to the inner wiring layer 20, that is, a metal post layer.

[0041] The second redistribution level layer RDL2 may be arranged on an upper surface of the package body level layer FBD1 and include a second redistribution layer 30 extending from the fan-in region FI to the fan-out region FO, and a second redistribution insulating layer 28 that insulates the second redistribution layer 30. The second redistribution layer 30 may include a material the same as that of the first redistribution layer 12. The second redistribution insulating layer 28 may include a material the same as that of the first redistribution insulating layer 10.

[0042] The semiconductor package PK1 may include a second redistribution pad 32 and a laser mark metal layer 34. The second redistribution pad 32 and the laser mark metal layer 34 may be simultaneously formed at the same level. For example, the second redistribution pad 32 and the laser mark metal layer 34 may be formed of the same material. The second redistribution pad 32 may be on the second redistribution level layer RDL2. The second redistribution pad 32 and the laser mark metal layer 34 may include, for example, nickel (Ni), aluminum (Al), iron (Fe), copper (Cu), titanium (Ti), chromium (Cr), gold (Au), silver (Ag), palladium (Pd), platinum (Pt), or a combination thereof.

[0043] The second redistribution pad 32 may include a metal pad. The second redistribution pad 32 may include a joint pad electrically coupled to an external semiconductor package. In an embodiment of the present inventive concept, the second redistribution pad 32 may be arranged in the fan-in region FI and the fan-out region FO. In an embodiment of the present inventive concept, the second redistribution pad 32 may not be arranged in the fan-in region FI but may be arranged only in the fan-out region FO.

[0044] The second redistribution pad 32 may be electrically connected to the second redistribution layer 30. The second redistribution pad 32 may be arranged on the second redistribution level layer RDL2 and spaced apart from the laser mark metal layer 34. The second redistribution pad 32 may include a metal layer, for example, a copper (Cu) layer or an aluminum (Al) layer. Solder balls may be formed on the second redistribution pad 32, and an external semiconductor package may be mounted thereon. To be described with reference to FIG. 16, a second semiconductor package PK6 may be mounted on the second redistribution pad 32 through a second solder ball 72.

[0045] The laser mark metal layer 34 may be on the second redistribution level layer RDL2. For example, the laser mark metal layer 34 may be arranged on a partial region (i.e., a portion) of the entire surface (e.g., top surface) of the second redistribution level layer RDL2. The laser mark metal layer 34 may be arranged on the second redistribution level layer RDL2 of the fan-in region FI, apart from the second redistribution pad 32. For example, the laser mark metal layer 34 may be arranged on a portion of an entire surface (e.g., top surface) of the second redistribution level layer RDL2 of the fan-in region FI. The laser mark metal layer 34 may be over the semiconductor chip 22, for example, over a center portion of the semiconductor chip 22. For example, the laser mark metal layer 34 may overlap the center portion of the semiconductor chip 22 in the Z direction.

[0046] The laser mark metal layer 34 may be arranged in a region where the second redistribution pad 32 is not formed. The laser mark metal layer 34 may include a dummy metal layer that is not electrically connected to the second redistribution pad 32.

[0047] Inside the laser mark metal layer 34, a laser mark (36 of FIG. 3A) formed by laser as described below may be located. The laser mark (36 of FIG. 3A) may include letters, numbers, figures, symbols, and recognition codes indicating various pieces of information of the semiconductor package PK1 to be used to track the semiconductor package PK1.

[0048] As the laser mark (36 of FIG. 3A) is formed inside the laser mark metal layer 34 on the second redistribution level layer RDL2, damage to the second redistribution level layer RDL2 may be reduced. For example, during the formation of a laser mark with a laser incident on the second redistribution level layer RDL2, heat may be generated, and may damage the second redistribution level layer RDL2. Also, forming a laser mark on the second redistribution level layer RDL2 may be difficult, because a laser transmits therethrough or a reflectance of the laser is high, and visibility of the laser mark is relatively low. However, in the semiconductor package PK1 according to the present inventive concept, the laser mark (36 in FIG. 3A) may be easily formed inside the laser mark metal layer 34, and also, the visibility of the laser mark may be enhanced. Also, since the laser mark (36 in FIG. 3A) is formed inside the laser mark metal layer 34, the laser may be prevented from reaching the second redistribution insulating layer 28 to cause damage to the second redistribution level layer RDL2. The laser mark metal layer 34 and the laser mark formed inside the laser mark metal layer 34 are described in further detail below.

[0049] FIG. 2 is a top plan view of the semiconductor package of FIG. 1.

[0050] Like reference numerals in FIG. 2 as those of FIG. 1 may denote like elements. FIG. 2 illustrating the semiconductor package PK1 may be a plan view in XY direction (e.g., XY plane), that is, the X-direction and a Y-direction. The semiconductor package PK1 may have lengths LX1 and LY1 in the X- and Y-directions, respectively. In an embodiment of the present inventive concept, the lengths LX1 and LY1 may be between about 10 mm and about 60 mm. FIG. 2 illustrates that the length LX1 is greater than the length LY1, but the present inventive concept is not limited thereto. For example, the lengths LX1 and LY1 may be the same or the length LX1 may be smaller than the length LY1. The term "about" as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ± 30%, 20%, 10%, 5% of the stated value.

[0051] The semiconductor package PK1 may include the semiconductor chip 22. The semiconductor chip 22 may have lengths LX2 and LY2 in the X- and Y-directions, respectively. In an embodiment of the present inventive concept, the lengths LX2 and LY2 may be between about 2 mm and about 55 mm. In an embodiment of the present inventive concept, a planar area (e.g., on the XY plane) of the semiconductor chip 22 may be about 4 % to about 84 % of a planar area of the semiconductor package PK1.

[0052] The semiconductor package PK1 may include the laser mark metal layer 34. The laser mark metal layer 34 may be in a central region of the semiconductor package PK1. The laser mark metal layer 34 may be in a central region on the semiconductor chip 22. The laser mark metal layer 34 may be on a central region of the second redistribution insulating layer 28 constituting the second redistribution level layer (RDL2 of FIG. 1).

[0053] The second redistribution pad 32 may be in a peripheral region of the second redistribution insulating layer 28 constituting the second redistribution level layer (RDL2 OF FIG. 1). In other words, the laser mark metal layer 34 may be over a region of the second redistribution insulating layer 28 constituting the second redistribution level layer (RDL2 OF FIG. 1), wherein the second redistribution pad 32 is not formed over the above region. For example, the second redistribution pad 32 may be arranged on the second redistribution level layer (RDL2 OF FIG. 1), and may be spaced apart from the laser mark metal layer 34 on a level the same as that of the laser mark metal layer 34.

[0054] The laser mark metal layer 34 may have lengths LX3 and LY3 in the X- and Y-directions, respectively. In an embodiment of the present inventive concept, the lengths LX3 and LY3 may be between about 1 mm and about 50 mm. In an embodiment of the present inventive concept, a planar area of the laser mark metal layer 34 may be about 1 % to about 69 % of the planar area of the semiconductor package PK1. For example, the laser mark metal layer 34 may be arranged in a portion, which is about 1% to about 69%, of an entire surface (e.g., top surface) of the second redistribution level layer (RDL2 OF FIG. 1).

[0055] A laser mark 36 may be located in the laser mark metal layer 34 inside the semiconductor package PK1. The laser mark 36 is described in further detail below.

[0056] FIG. 3A is an enlarged cross-sectional view for describing the laser mark 36 formed in the laser mark metal layer 34 of the semiconductor package PK1 of FIGS. 1 and 2, and FIG. 3B is a plan view for describing the laser mark 36 of FIG. 3A. The laser mark 36 may be an air gap or an air space formed by laser. However, the present inventive concept is not limited thereto. For example, the laser mark 36 may be an air gap or an air space formed by laser then filled with a suitable material to have good visibility to be easily recognized by a user.

[0057] In the semiconductor package PK1, the laser mark metal layer 34 may be on the second redistribution insulating layer 28 constituting the second redistribution level layer (RDL2 OF FIG. 1). As described above, the laser mark metal layer 34 may be selected from, for example, nickel (Ni), aluminum (Al), iron (Fe), copper (Cu), titanium (Ti), chromium (Cr), gold (Au), silver (Ag), palladium (Pd), platinum (Pt) and alloy thereof. The second redistribution insulating layer 28 may have a first thickness T1. The first thickness T1 may be several micrometers (mm). The first thickness T1 may be about 1 mm to about 7 mm.

[0058] The laser mark metal layer 34 may include a plurality of sub-metal layers 34a, 34b, and 34c in a cross-section. The laser mark metal layer 34 may include a first sub-metal layer 34a, a second sub-metal layer 34b, and a third sub-metal layer 34c sequentially stacked on the second redistribution insulating layer 28. In an embodiment of the present inventive concept, the first sub-metal layer 34a, the second sub-metal layer 34b, and the third sub-metal layer 34c may be a copper (Cu) layer, a nickel (Ni) layer, and a gold (Au) layer, respectively. However, the present inventive concept is not limited thereto.

[0059] The first sub-metal layer 34a may have a second thickness T2. The second thickness T2 may be about 1 mm to about 5 mm. The second sub-metal layer 34b may have a third thickness T3. The third thickness T3 of the second sub-metal layer 34b may be smaller than the second thickness T2 of the first sub-metal layer 34a. The third thickness T3 may be about 1 mm to about 5 mm.

[0060] The third sub-metal layer 34c may have a fourth thickness T4. The fourth thickness T4 of the third sub-metal layer 34c may be smaller than the second thickness T2 of the first sub-metal layer 34a and the third thickness T3 of the second sub-metal layer 34b. The fourth thickness T4 may be about 0.1 mm to about 1 mm.

[0061] The laser mark metal layer 34 including the first sub-metal layer 34a, the second sub-metal layer 34b, and the third sub-metal layer 34c may have a fifth thickness T5. The fifth thickness T5 may be several micrometers (mm). The fifth thickness T5 may be about 3 mm to about 10 mm.

[0062] The laser mark 36 may be provided inside the laser mark metal layer 34. The laser mark 36 may include a circular laser pattern 38 in a cross-section (cross-sectional view), formed by ablation generated by applying laser to the laser mark metal layer 34. In other words, the laser mark 36 may be the circular laser pattern 38 in a cross-section, which is obtained as a portion of the laser mark metal layer 34 is melted and evaporated by laser applied to the laser mark metal layer 34. For example, at the portion of the laser mark metal layer 34 irradiated by the laser beam, the material of the laser mark metal layer 34 may be heated by the absorbed laser energy and may evaporate or sublimate to form an air space having the circular laser pattern 38 as the laser mark 36.

[0063] The circular laser pattern 38 in a cross-section, constituting the laser mark 36, may have a depth D1. The bottom of the circular laser pattern 38 in a cross-section may be located inside the first sub-metal layer 34a. For example, the bottom of the circular laser pattern 38 in a cross-section may be located between the top surface and the bottom surface of the first sub-metal layer 34a. The depth D1 of the circular laser pattern 38 may be several micrometers (mm). In other words, the laser mark 36 may have the depth D1 of several micrometers (mm) into the laser mark metal layer 34 in a cross-section. For example, the depth D1 of the circular laser pattern 38 in a cross-section may be about 0.1 mm to about 5 mm.

[0064] In FIG. 3A, only one circular laser pattern 38 formed inside the laser mark metal layer 34 in a cross section is illustrated, but the present inventive concept is not limited thereto. For example, a plurality of circular laser patterns may also be formed in the laser mark metal layer 34 in a cross section to form the laser mark 36. As the depth D1 of the circular laser pattern 38 constituting the laser mark 36 is several micrometers (mm), the laser mark 36 may be easily formed by using a laser mark forming apparatus (50 in FIG. 14) described later by using low energy, for example, several Watts. For example, the depth D1 of the circular laser pattern 38 constituting the laser mark 36 may be precisely controlled by adjusting the applied energy of the laser beam incident onto the laser mark metal layer 34 using the laser mark forming apparatus (50 in FIG. 14) to be described.

[0065] The laser mark 36 may include, as illustrated in FIG. 3B, letters, numbers, figures, symbols, and recognition codes indicating various pieces of information of the semiconductor package PK1. The letters may include a product logo or serial number, for example, for identifying the product. The recognition codes may include a two dimensional (2D) bar code and a quick response (QR) code.

[0066] FIGS. 4A and 4B are plan views for describing various arrangement examples of the laser mark of FIGS. 3A and 3B.

[0067] As illustrated in FIG. 4A, a plurality of, for example, first to third laser marks 36a, 36b, and 36c may be formed in the laser mark metal layer 34 in the semiconductor package PK1. The first to third laser marks 36a, 36b, and 36c may be formed in first to third laser mark forming regions 36r1, 36r2, and 36r3, respectively.

[0068] The first to third laser mark forming regions 36r1, 36r2, and 36r3 may be referred to as laser pattern forming regions. The first to third laser mark forming regions 36r1, 36r2, and 36r3 are spaced apart from each other and may have various sizes in the X- and Y-directions.

[0069] In the first and second laser mark forming regions 36r1 and 36r2, letters or numbers may be formed, and in the third laser mark forming region 36r3, a recognition code, for example, a 2D bar code and a QR code may be formed. QR code may also be a 2D bar code, or may be a three dimensional (3D) bar code. Examples of the letters, numbers, 2D bar code and QR code included in the first to third laser marks 36a, 36b, and 36c formed in the first to third laser mark forming regions 36r1, 36r2, and 36r3, respectively, may be found in or referred to FIG. 3B as viewed in a plan view in the XY direction (e.g., XY plane).

[0070] As illustrated in FIG. 4B, in the semiconductor package PK1, a plurality of, for example, fourth to sixth laser marks 36d, 36e, and 36f may be formed in the laser mark metal layer 34. The fourth to sixth laser marks 36d, 36e, and 36f may be formed in the fourth to sixth laser mark forming regions 36r4, 36r5, and 36r6, respectively. The fourth to sixth laser mark forming regions 36r4, 36r5, and 36r6 may be referred to as laser pattern forming regions.

[0071] The fourth laser mark forming region 36r4 may include a plurality of, for example, first to fifth sub-laser mark forming regions 36r4a, 36r4b, 36r4c, 36r4d, and 36r4e that are spaced apart from each other. The fifth laser mark forming region 36r5 may include a plurality of, for example, sixth to eighth sub laser mark forming regions 36r5a, 36r5b, and 36r5c that are spaced apart from each other. Letters or numbers may be formed in the fourth and fifth laser mark forming regions 36r4 and 36r5. In some instances, symbols or figures may also be formed in the fourth and fifth laser mark forming regions 36r4 and 36r5.

[0072] The sixth laser mark forming region 36r6 may include a plurality of, for example, ninth and tenth sub laser mark forming regions 36r6a and 36r6b that are spaced apart from each other. In the sixth laser mark forming region 36r6, a recognition code, for example, a bar code and a QR code may be formed. Examples of the letters, numbers, bar code and QR code included in the fourth to sixth laser marks 36d, 36e, and 36f formed in the fourth to sixth laser mark forming regions 36r4, 36r5, and 36r6, respectively, may be found in or referred to FIG. 3B as viewed in a plan view in the XY direction (e.g., XY plane). As described above, in the semiconductor package PK1, the plurality of laser marks 36a to 36f of various shapes may be formed in the laser mark metal layer 34. Also, various laser marks having various shapes besides the laser marks 36a to 36 F shown in FIGS. 4A and 4B may also be formed in laser pattern forming regions in the laser mark metal layer 34 for the semiconductor package PK1.

[0073] FIGS. 5A and 5B are enlarged cross-sectional views for describing a laser mark formed in a laser mark metal layer of a semiconductor package, according to an embodiment of the present inventive concept.

[0074] Semiconductor packages PK2a and PK2b of FIGS. 5A and 5B, respectively, may be identical to the semiconductor package PK1 of FIGS. 1, 2, 3A, 3B, 4A and 4B except for laser marks 36-1 and 36-2.

[0075] The semiconductor packages PK2a and PK2b of FIGS. 5A and 5B may be identical to the semiconductor package PK1 of FIG. 3A except for a difference in depths D2 and D3 of circular laser patterns 38-1 and 38-2 constituting the laser marks 36-1 and 36-2, respectively, in a cross-section.

[0076] In FIGS. 5A and 5B, the same reference numerals as those of FIGS. 1, 2, 3A, 3B, 4A and 4B denote the same elements. In FIGS. 5A and 5B, for convenience, the circular laser patterns 38-1 and 38-2 in a cross-section, constituting the laser marks 36-1 and 36-2 are described, but the present inventive concept is not limited thereto. For example, they may be formed also as an elliptical laser pattern.

[0077] In the semiconductor packages PK2a and PK2b, the laser mark metal layer 34 may be on the second redistribution insulating layer 28 constituting the second redistribution level layer (RDL2 OF FIG. 1). The laser mark metal layer 34 may include the plurality of sub-metal layers 34a, 34b, and 34c. The laser mark metal layer 34 may include the first sub-metal layer 34a, the second sub-metal layer 34b, and the third sub-metal layer 34c sequentially stacked on the second redistribution insulating layer 28.

[0078] In the semiconductor package PK2a of FIG. 5A, the laser mark 36-1 may be provided inside the laser mark metal layer 34. The laser mark 36-1 may be the circular laser pattern 38-1 in a cross-section, formed by ablation generated by applying laser to the laser mark metal layer 34. For example, at a portion of the laser mark metal layer 34 irradiated by the laser beam, the material of the laser mark metal layer 34 may be heated by the absorbed laser energy and may evaporate or sublimate to form an air space having the circular laser pattern 38-1 in a cross-section as the laser mark 36-1.

[0079] The circular laser pattern 38-1 in a cross-section, constituting the laser mark 36-1 may have the depth D2. The bottom of the circular laser pattern 38-1 in a cross-section may be located on a surface (e.g., top surface) of the first sub-metal layer 34a. Since the laser mark 36-1 penetrates the third sub-metal layer 34c and the second sub-metal layer 34b and stops at the top surface of the first sub-metal layer 34a, the laser may be prevented from reaching the second redistribution insulating layer 28 to cause damage to the second redistribution level layer RDL2. The depth D2 of the circular laser pattern 38-1 in a cross-section may be several micrometers (mm). For example, the depth D2 of the circular laser pattern 38-1 in a cross-section may be about 0.1 mm to about 5 mm. For example, the depth D2 of the circular laser pattern 38-1 constituting the laser mark 36-1 may be precisely controlled by adjusting the applied energy of the laser beam incident onto the laser mark metal layer 34 using the laser mark forming apparatus (50 in FIG. 14) to be described.

[0080] In the semiconductor package PK2b of FIG. 5B, the laser mark 36-2 may be provided inside the laser mark metal layer 34. The laser mark 36-2 may be the circular laser pattern 38-2 in a cross-section, formed by ablation generated by applying laser to the laser mark metal layer 34. For example, at a portion of the laser mark metal layer 34 irradiated by the laser beam, the material of the laser mark metal layer 34 may be heated by the absorbed laser energy and may evaporate or sublimate to form an air space having the circular laser pattern 38-2 in a cross-section as the laser mark 36-2. 

[0081] The circular laser pattern 38-2 in a cross-section, constituting the laser mark 36-2 may have the depth D3. The bottom of the circular laser pattern 38-2 may be located on a surface (e.g., top surface) of the second sub-metal layer 34b. Since the laser mark 36-2 penetrates the third sub-metal layer 34c and stops at the top surface of the second sub-metal layer 34b, the laser may be prevented from reaching the second redistribution insulating layer 28 to cause damage to the second redistribution level layer RDL2. The depth D3 of the circular laser pattern 38-2 in a cross-section may be smaller than 1 micrometer (mm). For example, the depth D3 of the circular laser pattern 38-2 in a cross-section may be about 0.1 mm to about 3 mm. For example, the depth D3 of the circular laser pattern 38-2 constituting the laser mark 36-2 may be precisely controlled by adjusting the applied energy of the laser beam incident onto the laser mark metal layer 34 using the laser mark forming apparatus (50 in FIG. 14) to be described.

[0082] FIGS. 6A and 6B are enlarged cross-sectional views for describing a laser mark formed in a laser mark metal layer of a semiconductor package, according to an embodiment of the present inventive concept.

[0083] Semiconductor packages PK3a and PK3b of FIGS. 6A and 6B, respectively, may be identical to the semiconductor package PK1 of FIGS. 1, 2, 3A, 3B, 4A and 4B except for laser marks 36-3 and 36-4.

[0084] The semiconductor packages PK3a and PK3b of FIGS. 6A and 6B, respectively, may be identical to the semiconductor package PK1 of FIG. 3A except that triangular and quadrangular laser patterns 38-3 and 38-4 respectively constituting the laser marks 36-3 and 36-4 in a cross-section are included.

[0085] In FIGS. 6A and 6B, the same reference numerals as those of FIGS. 1, 2, 3A, 3B, 4A and 4B denote the same elements. In FIGS. 6A and 6B, for convenience, the triangular and quadrangular laser patterns 38-3 and 38-4 which are in a cross-section and respectively constitute the laser marks 36-3 and 36-4 are described, but the present inventive concept is not limited thereto. For example, they may also be formed as a polygonal laser pattern other than triangular and quadrangular laser patterns in a cross-section.

[0086] In the semiconductor packages PK3a and PK3b, the laser mark metal layer 34 may be on the second redistribution insulating layer 28 constituting the second redistribution level layer (RDL2 OF FIG. 1). The laser mark metal layer 34 may include the plurality of sub-metal layers 34a, 34b, and 34c. The laser mark metal layer 34 may include the first sub-metal layer 34a, the second sub-metal layer 34b, and the third sub-metal layer 34c sequentially stacked on the second redistribution insulating layer 28.

[0087] In the semiconductor package PK3a of FIG. 6A, the laser mark 36-3 may be provided inside the laser mark metal layer 34. The laser mark 36-3 may be the triangular laser pattern 38-3 in a cross-section, formed by ablation generated by applying laser to the laser mark metal layer 34. For example, at a portion of the laser mark metal layer 34 irradiated by the laser beam, the material of the laser mark metal layer 34 may be heated by the absorbed laser energy and may evaporate or sublimate to form an air space having the triangular laser pattern 38-3 as the laser mark 36-3.

[0088] The triangular laser pattern 38-3 constituting the laser mark 36-3 may have a depth D4. The bottom of the triangular laser pattern 38-3 may be located inside the first sub-metal layer 34a. For example, the bottom of the triangular laser pattern 38-3 in a cross-section may be located between the top surface and the bottom surface of the first sub-metal layer 34a. The depth D4 of the triangular laser pattern 38-3 may be several micrometers (mm). For example, the depth D4 of the triangular laser pattern 38-3 may be about 2 mm to about 5 mm. For example, the depth D4 of the circular laser pattern 38-3 constituting the laser mark 36-3 may be precisely controlled by adjusting the applied energy of the laser beam incident onto the laser mark metal layer 34 using the laser mark forming apparatus (50 in FIG. 14) to be described.

[0089] In the semiconductor package PK3b of FIG. 6B, the laser mark 36-4 may be provided inside the laser mark metal layer 34. The laser mark 36-4 may be the quadrangular laser pattern 38-4 in a cross-section, formed by ablation generated by applying laser to the laser mark metal layer 34. For example, at a portion of the laser mark metal layer 34 irradiated by the laser beam, the material of the laser mark metal layer 34 may be heated by the absorbed laser energy and may evaporate or sublimate to form an air space having the quadrangular laser pattern 38-4 as the laser mark 36-4.

[0090] The quadrangular laser pattern 38-4 in a cross-section, constituting the laser mark 36-4 may have a depth D5. The bottom of the quadrangular laser pattern 38-4 in a cross-section may be located inside the first sub-metal layer 34a. For example, the bottom of the quadrangular laser pattern 38-4 in a cross-section may be located between the top surface and the bottom surface of the first sub-metal layer 34a. The depth D5 of the quadrangular laser pattern 38-4 in a cross-section may be several micrometers (mm). For example, the depth D5 of the quadrangular laser pattern 38-4 in a cross-section may be about 2 mm to about 5 mm. For example, the depth D5 of the quadrangular laser pattern 38-4 constituting the laser mark 36-4 may be precisely controlled by adjusting the applied energy of the laser beam incident onto the laser mark metal layer 34 using the laser mark forming apparatus (50 in FIG. 14) to be described.

[0091] FIG. 7 is an enlarged cross-sectional view for describing a laser mark formed in a laser mark metal layer of a semiconductor package, according to an embodiment of the present inventive concept.

[0092] The semiconductor package PK4 of FIG. 7 may be identical to the semiconductor package PK1 of FIGS. 1, 2, 3A, 3B, 4A, and 4B, except for a laser mark metal layer 34-1 and a laser mark 36-5. For example, the semiconductor package PK4 of FIG. 7 may be identical to the semiconductor package PK1 of FIG. 3A except that the laser mark metal layer 34-1 and the laser mark 36-5 are included.

[0093] In FIG. 7, the same reference numerals as those of FIGS. 1, 2, 3A, 3B, 4A, and 4B,denote the same elements. While, for convenience, the laser mark 36-5 formed as the circular laser pattern 38-5 in a cross-section is described with reference to FIG. 7, but the present inventive concept is not limited thereto. For example, the laser mark 36-5 may also be formed as an elliptical laser pattern in a cross-section.

[0094] In the semiconductor package PK4, the laser mark metal layer 34-1 may be on the second redistribution insulating layer 28 constituting the second redistribution level layer (RDL2 OF FIG. 1). In an embodiment of the present inventive concept, the laser mark metal layer 34-1 may be selected from, for example, nickel (Ni), aluminum (Al), iron (Fe), copper (Cu), titanium (Ti), chromium (Cr), gold (Au), silver (Ag), palladium (Pd), platinum (Pt) and an alloy thereof.

[0095] The laser mark metal layer 34-1 may include a plurality of sub-metal layers 34d and 34e. The laser mark metal layer 34-1 may include a first sub-metal layer 34d and a second sub-metal layer 34e sequentially stacked on the second redistribution insulating layer 28. The first sub-metal layer 34d and the second sub-metal layer 34e may be a nickel (Ni) layer and a gold (Au) layer, respectively. However, the present inventive concept is not limited thereto.

[0096] The first sub-metal layer 34d may have a second thickness T2-1. The second thickness T2-1 may be about 1 mm to about 5 mm. The second sub-metal layer 34e may have a third thickness T3-1. The third thickness T3-1 of the second sub-metal layer 34e may be smaller than the second thickness T2-1 of the first sub-metal layer 34d. The third thickness T3-1 may be about 0.1 mm to about 3 mm.

[0097] The laser mark metal layer 34-1 including the first sub-metal layer 34d and the second sub-metal layer 34e may have a fifth thickness T5-1. The fifth thickness T5-1 may several micrometers (mm). The fifth thickness T5-1 may be about 1 mm to about 7 mm.

[0098] The laser mark 36-5 may be provided inside the laser mark metal layer 34-1. The laser mark 36-5 may be a circular laser pattern 38-5 in a cross-section, formed by ablation generated by applying laser to the laser mark metal layer 34-1. For example, at a portion of the laser mark metal layer 34 irradiated by the laser beam, the material of the laser mark metal layer 34-1 may be heated by the absorbed laser energy and may evaporate or sublimate to form an air space having the circular laser pattern 38-5 as the laser mark 36-5.

[0099] The circular laser pattern 38-5 in a cross-section, constituting the laser mark 36-5 may have a depth D6. The bottom of the circular laser pattern 38-5 in a cross-section may be located inside the first sub-metal layer 34d. For example, the bottom of the quadrangular laser pattern 38-5 in a cross-section may be located between the top surface and the bottom surface of the first sub-metal layer 34d. The depth D6 of the circular laser pattern 38-5 may be several micrometers (mm). For example, the depth D6 of the circular laser pattern 38-5 in a cross-section may be about 0.1 mm to about 3 mm. For example, the depth D6 of the circular laser pattern 38-5 constituting the laser mark 36-5 may be precisely controlled by adjusting the applied energy of the laser beam incident onto the laser mark metal layer 34-1 using the laser mark forming apparatus (50 in FIG. 14) to be described.

[0100] FIG. 8 is a cross-sectional view of a semiconductor package according to an embodiment of the present inventive concept.

[0101] A semiconductor package PK5 of FIG. 8 may be identical to the semiconductor package PK1 of FIGS. 1, 2, 3A, 3B, 4A and 4B, except for a difference in a package element FE2.

[0102] The semiconductor package PK5 of FIG. 8 may be almost identical to the semiconductor package PK1 of FIG. 1 except that the package element FE2 includes a wiring substrate 2 and inner wiring layers 4a, 4b, 6, and 8. In FIG. 8, the same reference numerals as those of FIGS. 1, 2, 3A, 3B, 4A, and 4B,denote the same elements.

[0103] The semiconductor package PK5 may be a fan-out semiconductor package. The semiconductor package PK5 may be a fan-out panel level package (FOPLP) type. The semiconductor package PK5 may include the fan-in region FI in which the semiconductor chip 22 is located and a fan-out region FO on both sides of the fan-in region FI.

[0104] The fan-out region FO may surround the fan-in region FI on a plane. While the semiconductor chip 22 is described as a single chip in FIG. 8, but the present inventive concept is not limited thereto. For example, the semiconductor chip 22 may include a plurality of stacked chips. The semiconductor chip 22 may include the front surface 22a and the rear surface 22b positioned opposite to the front surface 22a. The front surface 22a may be an active surface, and the rear surface 22b may be a non-active surface. The chip solder ball 24 is arranged on the front surface 22a, and may include a chip connection ball or a chip connection bump. For example, the chip solder ball 24 may include a solder material, such as one or more of, for example, tin (Sn), silver (Ag), zinc (Zn), lead (Pb), and any alloy thereof.

[0105] The fan-out region FO may include the package element FE2 including the wiring substrate 2 and the inner wiring layers 4a, 4b, 6, and 8. The wiring substrate 2 may be an insulating substrate. For example, the wiring substrate 2 may be a printed circuit board. The wiring substrate 2 may be referred to as a frame substrate. A through hole TH1 may be in the wiring substrate 2. The semiconductor chip 22 may be in the through hole TH1.

[0106] The inner wiring layers 4a, 4b, 6, and 8 may include an inner metal layer 6, a metal via layer 8, a lower metal pad layer 4a, and an upper metal pad layer 4b, which are formed in the wiring substrate 2. The semiconductor chip 22 of the fan-in region FI may be sealed by a fan-in encapsulation layer 26b-1. The fan-in encapsulation layer 26b-1 may include an EMC, but the material of the fan-in encapsulation layer 26b-1 is not particularly limited. For example, any other suitable thermosetting resin or thermoplastic resin may be used as the fan-in encapsulation layer 26b-1.

[0107] The semiconductor chip 22 in the fan-in region FI, the fan-in encapsulation layer 26b-1 sealing the semiconductor chip 22 in the fan-in region FI, and the package element FE2 including the wiring substrate 2, and the inner wiring layers 4a, 4b, 6, and 8 in the fan-out region FO may constitute a package body level layer FBD2.

[0108] The semiconductor package PK5 may include a first redistribution level layer RDL1 and a second redistribution level layer RDL2. As the first redistribution level layer RDL1 is formed on the front surface 22a of the semiconductor chip 22, first redistribution level layer RDL1 may be referred to as a front surface redistribution level layer. As the second redistribution level layer RDL2 is formed on the rear surface 22b of the semiconductor chip 22, the second redistribution level layer RDL2 may be referred to as a rear surface redistribution level layer. The second redistribution level layer RDL2 may not be directly in physical contact with the rear surface 22b of the semiconductor chip 22, but the present inventive concept is not limited thereto. For example, the second redistribution level layer RDL2 may be directly in physical contact with a top surface of the wiring substrate 2 and the rear surface 22b of the semiconductor chip 22.

[0109] The first redistribution level layer RDL1 and the second redistribution level layer RDL2 are described above, and thus are described briefly here. The first redistribution level layer RDL1 may be arranged on a lower surface of the package body level layer FBD2 and include the first redistribution layer 12 extending from the fan-in region FI to the fan-out region FO, and the first redistribution insulating layer 10 that insulates the first redistribution layer 12.

[0110] The first redistribution level layer RDL1 may include, on a lower side thereof, the first redistribution pad 14 electrically connected to the first redistribution layer 12. The first solder ball 16 may be arranged on the first redistribution pad 14. The first redistribution level layer RDL1 may include, on an upper side thereof, the chip connection pad 18 electrically connected to the first redistribution layer 12. The chip connection pad 18 may be electrically connected to the chip solder ball 24 of the semiconductor chip 22.

[0111] The second redistribution level layer RDL2 may be arranged on an upper surface of the package body level layer FBD2 and include a second redistribution layer 30 extending from the fan-in region FI to the fan-out region FO, and a second redistribution insulating layer 28 that insulates the second redistribution layer 30.

[0112] The semiconductor package PK5 may include the second redistribution pad 32 and the laser mark metal layer 34. The second redistribution pad 32 and the laser mark metal layer 34 are described above, and thus are briefly described here. The laser mark metal layer 34 may be on the second redistribution level layer RDL2.

[0113] Inside the laser mark metal layer 34, a laser mark formed by laser may be located as described above. As the laser mark is formed inside the laser mark metal layer 34 on the second redistribution level layer RDL2, damage to the second redistribution level layer RDL2 may be reduced. For example, during the formation of a laser mark with a laser incident on the second redistribution level layer RDL2, heat may be generated, and may damage the second redistribution level layer RDL2. Also, forming a laser mark on the second redistribution level layer RDL2 may be difficult, because a laser transmits therethrough or a reflectance of the laser is high, and visibility of the laser mark is relatively low. However, in the semiconductor package PK5 according to the present inventive concept, a laser mark may be easily formed inside the laser mark metal layer 34, and also, the visibility of the laser mark may be enhanced. Also, since the laser mark (36 in FIG. 3A) is formed inside the laser mark metal layer 34, the laser may be prevented from reaching the second redistribution insulating layer 28 to cause damage to the second redistribution level layer RDL2.

[0114] FIGS. 9 through 15 are cross-sectional views for describing a method of manufacturing a semiconductor package, according to an embodiment of the present inventive concept.

[0115] In detail, FIGS. 9 to 15 are diagrams for describing the method of manufacturing the semiconductor package PK1 of FIGS. 1, 2, 3A, 3B, 4A, and 4B,. In particular, FIGS. 9 to 15 are diagrams for describing the semiconductor package PK1 of FIG. 1. In FIGS. 9 to 15, the same reference numerals as those of FIGS. 1, 2, 3A, 3B, 4A and 4B denote the same elements.

[0116] Referring to FIG. 9, the first redistribution level layer RDL1 is formed on a first carrier substrate 42 with an adhesive layer 43 interposed therebetween. The first carrier substrate 42 may include an insulating substrate or a semiconductor substrate. In an embodiment of the present inventive concept, the first carrier substrate 42 may include a glass substrate (or a glass wafer). In an embodiment of the present inventive concept, the first carrier substrate 42 may include a silicon (Si) substrate (or a silicon (Si) wafer).

[0117] The first redistribution level layer RDL1 may include the first redistribution layer 12 extending from the fan-in region FI to the fan-out region FO and the first redistribution insulating layer 10 insulating the first redistribution layer 12. The first redistribution level layer RDL1 may include, on the lower side thereof, the first redistribution pad 14 electrically connected to the first redistribution layer 12. The chip connection pad 18 electrically connected to the first redistribution layer 12 may be formed on the upper side of the first redistribution level layer RDL1 in the fan-in region FI.

[0118] The post connection pad 19 is formed on the first redistribution level layer RDL1 in the fan-out region FO. The chip connection pad 18 and the post connection pad 19 may be formed in a same process.

[0119] Referring to FIG. 10, the inner wiring layer 20 is formed on the post connection pad 19. In an embodiment of the present inventive concept, the inner wiring layer 20 of the fan-out region FO is formed by forming a metal material layer on the post connection pad 19 over the first redistribution level layer RDL1 and then selectively patterning the metal material layer by a photolithography process. In an embodiment of the present inventive concept, the post connection pad 19 and the inner wiring layer 20 may be formed at once on the first redistribution level layer RDL1 by using a damascene process.

[0120] The inner wiring layer 20 may include a metal post layer, for example, a copper (Cu) post layer. In an embodiment of the present inventive concept, the inner wiring layer 20 may have a pillar shape, and may include metal, such as one or more of, for example, copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), and any alloy thereof. The inner wiring layer 20 may include a metal via layer. The inner wiring layer 20 may be the package element FE1 of the fan-out region FO.

[0121] Referring to FIG. 11, the semiconductor chip 22 is mounted in the fan-in region FI. The chip solder ball 24 of the semiconductor chip 22 is electrically connected to the chip connection pad 18 on the first redistribution level layer RDL1.

[0122] Next, fan-in and fan-out encapsulation layers 26a and 26b for sealing the semiconductor chip 22 and the inner wiring layer 20 by a sufficient thickness are formed on the first redistribution level layer RDL1. When necessary, the encapsulation layers 26a and 26b may be formed to have the same plane as the inner wiring layer 20 by using a planarization process. For example, top surfaces of the inner wiring layer 20, the fan-in encapsulation layer 26a and the fan-out encapsulation layer 26b are coplanar with each other.

[0123] The encapsulation layers 26a and 26b may include the fan-in encapsulation layer 26a sealing the semiconductor chip 22 in the fan-in region FI and the fan-out encapsulation layer 26b sealing the inner wiring layer 20 in the fan-out region FO. The fan-out encapsulation layer 26b sealing the inner wiring layer 20 may be the package element FE1 of the fan-out region FO.

[0124] The semiconductor chip 22 in the fan-in region FI, the fan-in encapsulation layer 26a sealing the semiconductor chip 22 in the fan-in region FI, and the package element FE1 including the inner wiring layer 20 and the fan-out encapsulation layer 26b in the fan-out region FO may form the package body level layer FBD1. The chip connection pad 18 and the post connection pad 19 may also be included in the package body level layer FBD1.

[0125] Referring to FIG. 12, the second redistribution level layer RDL2 is formed on the fan-in and fan-out encapsulation layers 26a and 26b and the inner wiring layer 20. The second redistribution level layer RDL2 may be arranged on the upper surface of the package body level layer FBD1 and include the second redistribution layer 30 extending from the fan-in region FI to the fan-out region FO, and the second redistribution insulating layer 28 that insulates the second redistribution layer 30.

[0126] Referring to FIG. 13, the second redistribution pad 32 and the laser mark metal layer 34 are formed on the second redistribution level layer RDL2. After forming a metal material layer on the second redistribution level layer RDL2, the metal material layer is patterned by a photolithography process to form the second redistribution pad 32 and the laser mark metal layer 34.

[0127] The laser mark metal layer 34 may be arranged on the second redistribution level layer RDL2 of the fan-in region FI, and spaced apart from the second redistribution pad 32. The second redistribution pad 32 may include a joint pad electrically coupled to an external semiconductor package. The laser mark metal layer 34 may be a dummy metal layer that is not electrically connected to the second redistribution pad 32.

[0128] Referring to FIG. 14, a laser mark (36 in FIG. 3A) is formed in the laser mark metal layer 34 by using a laser mark forming apparatus 50. The laser mark forming apparatus 50 includes a control unit 52 and a laser source unit 54. The laser source unit 54 is controlled by the control unit 52 to generate laser 56. The control unit 52 may adjust the wavelength or energy of the laser 56.

[0129] In an embodiment of the present inventive concept, the laser 56 may include visible light laser. The laser 56 may be a green laser having a wavelength of about 495 nm to about 570 nm. The laser 56 may be a green laser having a wavelength of 532 nm. In an embodiment of the present inventive concept, the laser 56 may be an ultraviolet laser between about 100 nm and about 400 nm, for example, 355 nm. In an embodiment of the present inventive concept, the laser 56 may have an energy of several Watts.

[0130] The laser 56 generated by the laser source unit 54 is applied to the laser mark metal layer 34 while controlling the wavelength or energy thereof, to form a laser mark (36 in FIG. 3A). The laser mark forming apparatus 50 may be moved in the X-direction and the Y-direction to form the laser mark (36 in FIG. 3A) in the plurality of laser mark forming regions (36r1 to 36r6 in FIGS. 4A and 4B) provided in the laser mark metal layer 34.

[0131] As described above, as the depth of the circular laser pattern (38 in FIG. 3A) constituting the laser mark 36 is several micrometers (mm), the laser mark 36 may be easily formed by using the laser mark forming apparatus 50 and using a small amount of energy, for example, several Watts. For example, the depth (D1 in FIG. 3A) of the circular laser pattern (38 in FIG. 3A) constituting the laser mark 36 may be precisely controlled by adjusting the applied energy (e.g., adjusting wavelength and/or energy of the laser 56 by the control unit 52) of the laser beam incident onto the laser mark metal layer 34 using the laser mark forming apparatus 50, which includes the control unit 52 and the laser source unit 54.

[0132] As described above, the laser mark (36 in FIG. 3A) may include letters, numbers, figures, symbols, recognition codes, etc. indicating various pieces of information of the semiconductor package (PK1 in FIG. 1). As the laser mark 36 of FIG. 3A is formed inside the laser mark metal layer 34 on the second redistribution level layer RDL2, damage to the second redistribution level layer RDL2 may be reduced.

[0133] Forming a laser mark on the second redistribution level layer RDL2 may be difficult, because a laser transmits therethrough or a reflectance of the laser is high, and visibility of the laser mark is relatively low. However, in the semiconductor package PK1 (FIG. 1) according to the present inventive concept, the laser mark (36 in FIG. 3A) may be easily formed inside the laser mark metal layer 34, and also, the visibility of the laser mark may be enhanced. Since the laser mark (36 in FIG. 3A) is formed inside the laser mark metal layer 34, the laser may be prevented from reaching the second redistribution insulating layer 28 to cause damage to the second redistribution level layer RDL2.

[0134] Referring to FIG. 15, after removing the first carrier substrate 42, a second carrier substrate 44 is attached to the second redistribution level layer RDL2 by including an adhesive layer 46 therebetween. In an embodiment of the present inventive concept, the second carrier substrate 44 may include a glass substrate (or glass wafer). In an embodiment of the present inventive concept, the second carrier substrate 44 may include a silicon (Si) substrate (or silicon (Si) wafer).

[0135] Next, the first solder ball 16 is formed on the first redistribution pad 14 in a lower portion of the first redistribution level layer RDL1. The first solder ball 16 may include an external connection terminal for connection to an external device. Further, after removing the adhesive layer 46 and the second carrier substrate 44, individual semiconductor packages may be manufactured through a dicing process.

[0136] FIG. 16 is a cross-sectional view of a semiconductor package according to an embodiment of the present inventive concept.

[0137] A semiconductor package PK7 of FIG. 16 may be identical to the semiconductor package PK1 of FIGS. 1, 2, 3A, 3B, 4A, and 4B,except that a second semiconductor package PK6 is further stacked therein. In FIG. 16, the same reference numerals as those of FIGS. 1, 2, 3A, 3B, 4A, and 4B, denote the same elements.

[0138] The semiconductor package PK7 includes the semiconductor package PK1, which may also be referred to as a first semiconductor package, and the second semiconductor package PK6 stacked on the semiconductor package PK1. The semiconductor package PK7 may include a package-on-package (POP)-type package in which a package is stacked on another package. The semiconductor package PK1 is described above, and thus, is briefly described or omitted here.

[0139] As described above, in the semiconductor package PK1, the second redistribution pad 32 and the laser mark metal layer 34 are formed on the second redistribution level layer RDL2. Inside the laser mark metal layer 34, a laser mark (36 in FIG. 3A) having information of the semiconductor package PK1 is formed. When manufacturing a POP-type package, a semiconductor package having certain information may be easily selected from among various packages.

[0140] The second semiconductor package PK6 is stacked on the second redistribution pad 32 of the semiconductor package PK1. The second semiconductor package PK6 may include a second solder ball 72 formed under a second wiring substrate 70, a second semiconductor chip 74 formed on the second wiring substrate 70, a bonding wire 76 connecting the second semiconductor chip 74 to the second wiring substrate 70, and a second encapsulation layer 78 sealing the second semiconductor chip 74 on the second wiring substrate 70.

[0141] The second wiring substrate 70 may include a printed circuit board. The second semiconductor chip 74 may be the same as the semiconductor chip 22 described above. For example, the second semiconductor chip 74 may include, for example, a logic chip, a PMIC chip, or a memory chip.

[0142] The second solder ball 72 of the second semiconductor package PK6 may be electrically connected to the second redistribution pad 32. The laser mark metal layer 34 is not electrically connected to the second semiconductor package PK6. 

[0143] FIG. 17 is a schematic block diagram illustrating an example of a memory system having a semiconductor package, according to an embodiment of the present inventive concept.

[0144] Referring to FIG. 17, a memory system 100 may be applied to, for example, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card, or any device capable of transmitting and/or receiving information in a wireless environment.

[0145] The memory system 100 includes a controller 111, an input/output device 112 such as, for example, a keypad, a keyboard, or a display, a memory device (or memory chip) 113, an interface 114, and a bus 115. The memory device 113 and the interface 114 communicate with each other via a bus 115.

[0146] The controller 111 includes at least one microprocessor, a digital signal processor, a microcontroller, or other processing devices similar thereto. The memory device 113 may be used to store a command executed by the controller 111. The input/output device 112 may receive data or signals from outside the memory system 100 or may output data or signals to the outside of the memory system 100. For example, the input/output (I/O) device 112 may include, for example, a keyboard, a keypad, or a display device.

[0147] The memory device 113 and the controller 111 may include the semiconductor packages PK1 to PK7 according to the embodiments of the present inventive concept. The memory device 113 may further include other types of memories, volatile memories that can be accessed at any time, and other various types of memories. The interface 114 has a function of transmitting data to a communication network or receive data from a communication network.

[0148] FIG. 18 is a schematic block diagram illustrating an example of an information processing system having a semiconductor package, according to an embodiment of the present inventive concept.

[0149] Referring to FIG. 18, an information processing system 200 may be used in, for example, a mobile device or a desktop computer. The information processing system 200 may include a memory system 231 including a memory controller 231a and a memory device 231b.

[0150] Information processing system 200 includes the memory system 231, a modem 232 (MOdulator and DEModulator: MODEM), a CPU 233, a RAM 234, and a user interface 235 that are electrically connected to a system bus 236. Data processed by the CPU 233 or data input from the outside is stored in the memory system 231.

[0151] The memory system 231 including the memory controller 231a and the memory device 231b, the modem 232, the central processing unit 233, and the RAM 234 may include the semiconductor packages PK1 to PK7 according to the embodiments of the present inventive concept.

[0152] The memory system 231 may be configured as a solid state drive, and in this case, the information processing system 200 may stably store a large amount of data in the memory system 231. In addition, as reliability of the memory system 231 increases, the memory system 231 may have reduced resources required for error correction, thereby providing a high-speed data exchange function to the information processing system 200.

[0153] The information processing system 200 may further include an application chipset, a camera image signal processor (ISP), an input/output device, and/or the like.

[0154] While the present inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept as defined in the appended claims.