PACKAGING STRUCTURE, PACKAGING METHOD, CHIP STACKING STRUCTURE AND ELECTRONIC DEVICE

[0001] The present application claims priority to and benefits of Chinese Patent Application Serial No. 202510099235.9, filed on Jan. 21, 2025, the entire content of which is incorporated herein by reference.

[0002] The disclosure relates to the technical field of semiconductors, in particular to a packaging structure, a packaging method, a chip stacking structure, and an electronic device.

[0003] Three-dimensional stacking chips can not only realize high-density vertical interconnections between chips via hybrid bonding and other means to improve an equivalent two-dimensional integration density of chips, but also integrate a heterogeneous and heterotypic integration across different process nodes to enhance the functional density of a system, in order to meet an increasing demand for computing power.

[0004] According to a first aspect of the disclosure, a packaging structure

• • [0005] includes: a first chip and a second chip stacked with the first chip, and the first chip has a first element. An active surface of the second chip is arranged opposite to an active surface of the first chip. The second chip includes a shielding element. The shielding element is arranged on one side of the second chip close to the first chip, and is configured for reducing signal interference from the second chip to the first element.

[0006] According to a second aspect of the disclosure, a packaging method

• • [0007] is used for forming the packaging structure described above. The packaging method includes:
  • [0008] providing a first chip having a first element;
  • [0009] providing a second chip having a shielding element; and
  • [0010] stacking the first chip and the second chip, in which the shielding element is arranged on one side of the second chip close to the first chip, an active surface of the second chip is arranged opposite to an active surface of the first chip, and the shielding element is configured to reduce signal interference from the second chip to the first element.

[0011] According to a third aspect of the disclosure, a chip stacking structure

• • [0012] includes a substrate and a packaging structure arranged on the substrate. The packaging structure is the packaging structure described above.

[0013] According to a fourth aspect of the disclosure, an electronic device

• • [0014] includes a printed circuit board and the packaging structure according to any one of the above embodiments, and the printed circuit board is connected with the packaging structure.

[0027] Embodiments will be described in detail below, examples of which are illustrated in the accompanying drawings. The embodiments described below by referring to the accompanying drawings are exemplary and are intended to explain the disclosure, and should not be construed as limiting the disclosure.

[0028] FIG. 1 and FIG. 2 illustrate a packaging structure 100 disclosed by an embodiment. In the examples of FIG. 1 and FIG. 2, the inductor element 1003 needs to be provided with a clearance region of a certain size to prevent other wires from affecting a Q value and an inductance value of the inductor element 1003. Because an active surface of a first chip 1001 and an active surface of a second chip 1002 in the packaging structure 100 are connected by means of hybrid bonding, a spacing L between the first chip 1001 and the second chip 1002 is only a few microns. The inductor element 1003 of the first chip 1001 cannot have a clearance region that meets requirements. A circuit 1004 on the second chip 1002 may interfere with the inductor element 1003 of the first chip 1001, which may reduce a signal quality of the inductor element 1003 and further affects operations of the first chip 1001. Especially in high-rate scenarios, when a transmission speed reaches 10 BPS or higher, the inductor element 1003 is more susceptible to the influence of the second chip 1002. Therefore, how to improve the signal quality of the inductor element 1003 in the first chip 1001 is a technical problem to be solved urgently.

[0029] As illustrated in FIG. 3 and FIG. 4, a packaging structure 10 of an embodiment of the disclosure includes a first chip 1 and a second chip 2. The second chip 2 is stacked with the first chip 1, and an active surface of the second chip 2 is arranged opposite to an active surface of the first chip 1. The first chip 1 includes a first element 11, and the second chip 2 includes a shielding element 21. The shielding element 21 is arranged on one side of the second chip 2 close to the first chip 1, and is configured to reduce signal interference from the second chip 2 to the first element 11.

[0030] The shielding element 21 is arranged on one side of the second chip 2 close to the first chip 1, i.e., the second chip 2 has a first side facing the first chip 1 and a second side facing away from the first chip 1, and the shielding element 21 is arranged on the first side.

[0031] It should be noted that the chip in embodiments may be a die (also referred to as particle or bare chip) or a chip wafer. It may be understood that after an epitaxial layer is grown on a wafer, the chip wafer is formed, and a bare chip (die) is obtained by cutting the chip wafer. Die-to-die (D2D) bonding may be performed between dies. Chip wafer bonding is referred to as wafer-to-wafer (W2W) bonding. A structure where a plurality of dies are stacked on the wafer may be referred to as die-to-wafer (D2W) bonding. The packaging in the disclosure may also be at least one of a chip-to-Wafer (C2W) bonding, a die-to-wafer (D2C) bonding and a chip-to-chip (C2C) bonding.

[0032] A number of chips stacked in a chip stacking structure is not limited by the disclosure, and may be set according to application requirements. In addition, the above chip may be a memory chip, a logic chip, or other functional chips.

[0033] In the packaging structure 10 of embodiments, the second chip 2 has the shielding element 21, and the shielding element 21 is arranged on the side of the second chip 2 close to the first chip 1. The signal interference from the second chip 2 to the first element 11 may be reduced or even avoided by the usage of the shielding element 21, which improves a signal quality of the first element 11, thereby improving a signal quality of the packaging structure 10.

[0034] In an embodiment, the first chip 1 includes a logic chip and the second chip 2 includes a storage chip. Alternatively, the first chip 1 and the second chip 2 are both logic chips.

[0035] The logic chip may be an application chip, and the memory chip may be a dynamic random memory (DRAM) chip.

[0036] The first element include an element for realizing a specific function, which may be refer to as a functional element.

[0037] In an embodiment, the first element 11 includes an inductor. It may be understood that the first element may be other functional components under the influence of the second chip, such as a sensor, a capacitor, etc.

[0038] In the disclosure, the inductor element is highly susceptible to the influence of the second chip 2, and the solution may be applicable to scenarios where the first element 11 is an inductor.

[0039] By arranging the shielding element 21, the signal interference from the second chip 2 to the inductor, the sensor or the capacitor may be reduced or even avoided, thereby improving the signal quality of the packaging structure 10.

[0040] In order to facilitate understanding the technical solution of the disclosure, the technical solution of the disclosure will be further described by taking a thickness direction of the packaging structure 10 being consistent with an up-down direction as an example. The up-down direction is as shown in FIGS. 3 and 4.

[0041] For example, the first chip 1 is arranged on a lower side of the second chip 2, the first element 11 is arranged on a lower side of the shielding element 21, and the shielding element 21 is arranged on a lower side of the second chip 2.

[0042] In an embodiment, the second chip 2 includes a first circuit, and the first circuit 22 is arranged on one side of the shielding element 21 away from the first element 11 in the thickness direction of the packaging structure 10.

[0043] For example, the first element 11 is arranged on the lower side of the shielding element 21, and the first circuit 22 is arranged on an upper side of the shielding element 21.

[0044] By arranging the first circuit 22 on the side of the shielding element 21 away from the first element 11, the shielding element 21 is enabled to provide signal shielding for the first element 11, so as to reduce or even avoid the signal interference from the first circuit 22 to the first element 11, thereby improving the signal quality of the packaging structure 10.

[0045] In an embodiment, as illustrated in FIGS. 3 and 4, the first chip 1 includes a plurality of first wiring layers 101 arranged along the thickness direction of the packaging structure 10. At least one of the first wiring layers 101 is a first top layer 1011, and the first top layer 1011 is arranged closer to the second chip 2 than other first wiring layers 101 in the thickness direction of the packaging structure 10. The first element 11 is at least partially arranged on the first top layer 1011.

[0046] The first element 11 is at least partially arranged on the first top layer 1011, i.e., a part of the first element 11 is arranged on the first top layer 1011, and the remaining part of the first element 11 is arranged on other first wiring layers 101; or, the entire first element 11 is arranged on the first top layer 1011.

[0047] For example, a plurality of first wiring layers 101 are arranged in the up-down direction. One of the first wiring layers 101 is the first top layer 1011, and the first top layer 1011 among the plurality of first wiring layers 101 is located on the uppermost side.

[0048] In embodiments, among the plurality of first wiring layers 101, the closer the first wiring layer 101 is to the second chip 2, the greater its thickness and the smaller its resistance.

[0049] By arranging at least a part of the first element 11 on the first top layer 1011, a parasitic resistance of the first element 11 may be reduced, thereby improving the Q value of the first element 11, further improving the signal quality of the first element 11, and improving the signal quality of the packaging structure 10.

[0050] In an embodiment, as illustrated in FIG. 3, the first chip 1 further includes a second circuit 12 arranged on at least one side of the first element 11 in a preset direction, in which the preset direction is perpendicular to the thickness direction of the packaging structure 10.

[0051] In order to facilitate understanding the technical solution of the disclosure, the technical solution of the disclosure will be further described by taking the preset direction as a left-right direction as an example. The left-right direction is as shown in FIGS. 3 and 4.

[0052] For example, the second circuit 12 is located on left and right sides of the first element 11 in the left-right direction.

[0053] Compared with arranging the second circuit 12 on the side of the first element 11 away from the shielding element 21 in the preset direction, arranging the second circuit 12 on at least one side of the first element 11 in the preset direction may reduce an interference from the second circuit 12 to the first element 11, which further improves the signal quality of the first element 11, and improving the signal quality of the packaging structure 10.

[0054] In an embodiment, as illustrated in FIG. 3, the second chip 2 includes a plurality of second wiring layers 201 arranged along the thickness direction of the packaging structure 10. At least one of the second wiring layers 201 is a second top layer 2011, and the second top layer 2011 is arranged closer to the first chip 1 than other second wiring layers 201 in the thickness direction of the packaging structure 10. The shielding element 21 is arranged on the second top layer 2011.

[0055] For example, the plurality of second wiring layers 201 are arranged in the up-down direction. One of the second wiring layers 201 is the second top layer 2011. The second top layer 2011 among the plurality of the second wiring layers 201 is located on the uppermost side.

[0056] It is understood that among the plurality of second wiring layers 201, the closer the second wiring layer 201 is to the first chip 1, the greater of a thickness of the second wiring layer 201.

[0057] By arranging the shielding element 21 on the second top layer 2011, on the one hand, a signal shielding effect of the shielding element 21 may be enhanced, thereby further improving the signal quality of the first element 11, and improving the signal quality of the packaging structure 10; on the other hand, the remaining second wiring layers 201 far away from the first element 11 may be used as the first circuit 22, which improves an integration of the second chip 2, thus improving an integration of the packaging structure 10.

[0058] In an embodiment, as illustrated in FIG. 3, the second chip 2 further includes a third circuit 23 arranged on at least one side of the shielding element 21 in the preset direction, in which the preset direction is perpendicular to the thickness direction of the packaging structure 10.

[0059] For example, the third circuit 23 is located on left and right sides of the shielding element 21 in the left-right direction.

[0060] By arranging the third circuit 23 on at least one side of the shielding element 21 in the preset direction, the integration of the second chip 2 may be further improved, thereby improving the integration of the packaging structure 10.

[0061] In an embodiment, as illustrated in FIGS. 3 and 4, the first chip 1 has a plurality of first electrical connectors 13, and the second chip 2 has h a plurality of second electrical connectors 24. The second electrical connectors are interconnected with the first electrical connectors, respectively. The first chip 1 includes the first wiring layer 101, and the shielding element 21 is electrically connected with the first wiring layer 101 via the second electrical connector 24 and the first electrical connector 13.

[0062] As illustrated in FIG. 3, the first chip 1 has a first through hole 14, and the first electrical connector 13 passes through the first through hole 14 to reach a circuit of the first chip 1. The second chip 2 has a second through hole 25, and the second electrical connector 24 passes through the second through hole 25 to reach a circuit of the second chip 2. That is, the first chip 1 and the second chip 2 are connected by means of hybrid bonding.

[0063] The shielding element 21 is electrically connected with the first wiring layer 101 via the second electrical connector 24 and the first electrical connector 13.

[0064] In an embodiment, the shielding element 21 includes a shielding layer made of electromagnetic shielding material.

[0065] In an embodiment, the shielding element 21 includes a metal layer.

[0066] It is understood that the shielding element 21 in the disclosure is not limited to a metal layer or an electromagnetic shielding layer, but also other elements with an electromagnetic shielding function.

[0067] By configuring the shielding element 21 to include the metal layer, a signal shielding effect of the shielding element 21 may be enhanced, which further improves the signal quality of the first element 11 and improves the signal quality of the packaging structure 10.

[0068] In an embodiment, a metal density of a region where the metal layer is located is 30% to 50%.

[0069] For example, as illustrated in FIG. 5, a region within a dashed frame is the region where the metal layer is located, and a ratio of an area of the metal layer to an area of the dashed frame is a metal density of the region where the metal layer is located.

[0070] By setting the metal density of the region where the metal layer is located to 30% to 50%, an amount of metal in the shielding element 21 may be reduced while ensuring the shielding effect of the shielding element 21, so as to reduce a cost of the packaging structure 10. In an embodiment, the shielding element 21 is grounded or connected to a power supply.

[0071] For example, the shielding element 21 is electrically connected with the first wiring layer 101, and the first wiring layer 101 is grounded or connected to a power supply, thereby enabling the shielding element 21 to be grounded or connected to the power supply.

[0072] By grounding the shielding element 21, the signal shielding effect of the shielding element 21 may be improved, and the signal interference from the second chip 2 to the first element 11 may be reduces, thus further improving the signal quality of the packaging structure 10.

[0073] In an embodiment, as illustrated in FIGS. 5-7, the shielding element 21 includes at least one shielding part 213, and the shielding part 213 is comb-shaped.

[0074] For example, as illustrated in FIGS. 5-6, the shielding element 21 includes two shielding parts 213, both of the two shielding parts 213 are comb-shaped.

[0075] By configuring the shielding part 213 of the shielding element 21 into a comb shape, the signal shielding effect of the shielding element 21 may be effectively improved, which reduces the signal interference to the first element 11, and further improves the signal quality of the packaging structure 10.

[0076] In an embodiment, as illustrated in FIGS. 5-6, the shielding element 21 includes a plurality of shielding parts 213. At least one of the shielding parts 213 is a first shielding part 211, and at least one of the shielding parts 213 is a second shielding part 212. The first shielding part 211 includes a plurality of first metal strips 2111 arranged side by side, and the second shielding part includes a plurality of second metal strips 2121 arranged side by side. The first metal strips and the second metal strips are arranged alternately at intervals in sequence.

[0077] For example, as illustrated in FIGS. 5-6, the first shielding part 211 is arranged in a front side of the second shielding part 212, and the plurality of first metal strips 2111 and the plurality of second metal strips 2121 are arranged alternately at intervals along the left-right direction. The front-back direction and the left-right direction are shown in FIGS. 5 and 6.

[0078] By configuring the shielding element 21 to the above structure, the signal shielding effect of the shielding element 21 may be effectively improved, the signal interference to the first element 11 may be reduced, further improving the signal quality of the first element 11 and improving the signal quality of the packaging structure 10.

[0079] In an embodiment, as illustrated in FIGS. 5-6, a width of the first metal strip 2111 is 0.4 μm to 12.5 μm. A width of the second metal strip 2121 is 0.4 μm-12.5 μm

[0080] For example, as illustrated in FIG. 5, the width of both the first metal strip 2111 and the second metal strip 2121 is K1, where K1 is 1.8 μm.

[0081] By setting the width of the first metal strip 2111 and the second metal strip 2121 to 0.4 μm to 12.5 μm, it is convenient for manufacturing the shielding element 21, which thus facilitates manufacturing of the packaging structure 10, thereby reducing the cost of the packaging structure 10.

[0082] In an embodiment, as illustrated in FIGS. 5-6, a spacing between the first metal strip 2111 and the adjacent second metal strip 2121 is 0.4 μm to 25 μm.

[0083] For example, as illustrated in FIG. 5, the spacing between the first metal strip 2111 and the second metal strip 2121 is K2, where K2 is 2.7 μm.

[0084] By setting the spacing between the first metal strip 2111 and the second metal strip 2121 to 0.4 μm to 25 μm, it is convenient for manufacturing the shielding element 21, which thus facilitates manufacturing of the packaging structure 10, thereby reducing the cost of the packaging structure 10.

[0085] In an embodiment, as illustrated in FIG. 8, the shielding element 21 includes a plurality of shielding parts 213, and the plurality of shielding parts 213 are uniformly arranged along a circumferential direction of a preset rectangular frame. The shielding part 213 include a plurality of V-shaped metal strips 2131. The plurality of metal strips 2131 of the same shielding part 213 are arranged at intervals along an inward-outward direction, and a length of the metal strip 2131 located on an outer side is smaller than a length of the metal strip 2131 located on an inner side. A dashed frame in FIG. 8 is the preset rectangular frame.

[0086] Herein, “inward” may be understood as: a direction approaching a center of the rectangular frame in a plane where the shielding element 21 is located; “outward” may be understood as: a direction away from the center of the rectangular frame in the plane where the shielding element 21 is located.

[0087] By configuring the shielding element 21 to the above structure, the signal shielding effect of the shielding element 21 may be improved effectively, which reduces the signal interference to the first element 11 and improves the signal quality of the first element 11, thus improving the signal quality of the packaging structure 10.

[0088] In an embodiment, as illustrated in FIG. 8, there are four shielding parts 213, and an included angle of the metal strip 2131 is 90°.

[0089] By configuring four shielding parts 213 and configuring the inner included angle of the metal strip 2131 to 90°, it is convenient to manufacture the shielding element 21, which facilitates manufacturing of the packaging structure 10, thus reducing the cost of the packaging structure 10.

[0090] In an embodiment, as illustrated in FIG. 9, the shielding element 21 is in a shape of a rectangular pulse signal waveform.

[0091] By configuring the shielding element 21 to the above structure, the signal shielding effect of the shielding element 21 is effectively improved, which reduces the signal interference to the first element 11 and improves the signal quality of the first element 11, thus improving the signal quality of the packaging structure 10. In addition, configuring the shielding element 21 into the shape of the rectangular pulse signal waveform may facilitate the manufacturing of the shielding element 21, which thus facilitates the manufacturing of the packaging structure 10, thereby reducing the cost of the packaging structure 10.

[0092] In an embodiment, as illustrated in FIG. 6, an orthographic projection of the shielding element 21 in a direction towards the first chip 1 at least partially covers the first element 11.

[0093] The statement that “he orthographic projection of the shielding element 21 in the direction towards the first chip 1 at least partially covers the first element 11” may be understood as: the orthographic projection of the shielding element 21 in the direction towards the first chip 1 entirely covers the first element 11; or, a part of the orthographic projection of the shielding element 21 in the direction toward the first chip 1 covers the first element 11, and the remaining orthographic projection of the shielding element 21 in the direction toward the first chip 1 does not cover the first element 11.

[0094] By configuring the orthographic projection of the shielding element 21 in the direction toward the first chip 1 to at least partially cover the first element 11, the signal shielding effect of the shielding element 21 may be improved, which further improves the signal quality of the first element 11, and improves the signal quality of the packaging structure 10.

[0095] In an embodiment, as illustrated in FIG. 6, an area of the orthographic projection of the shielding element 21 in the direction toward the first chip 1 is larger than an area of a region where the first element 11 is located. That is, the orthographic projection of the shielding element 21 in the direction toward the first chip 1 not only covers the first element 11, but also covers an edge of the first element 11, so as to cover more signals generated by the first element 11.

[0096] By setting the area of the orthographic projection of the shielding element 21 in the direction toward the first chip 1 to be larger than the area of the region where the first element 11 is located, the signal shielding effect of the shielding element 21 may be further improved, which further improves the signal quality of the first element 11, and improves the signal quality of the packaging structure 10.

[0097] In an embodiment, as illustrated in FIGS. 3 and 11, an electrical connection region 102 and a clearance region 103 are arranged between the first chip 1 and the second chip 2. The first electrical connectors 13 and the second electrical connectors 24 are arranged in the electrical connection region 102, and an orthographic projection of the clearance region 103 in a direction towards the first element 11 covers the first element 11.

[0098] It is understood that both the first electrical connector 13 and the second electrical connector 24 are conductive parts that may also cause interference to the first element 11.

[0099] By setting the orthographic projection of the clearance region 103 in the direction towards the first element 11 to cover the first element 11, the orthographic projections of the first electrical connector 13 and the second electrical connector 24 in the direction towards the first element 11 thus does not cover the first element 11, so that the interference from the first electrical connector 13 and the second electrical connector 24 to the first element 11 may be reduced, which further improves the signal quality of the first element 11, and improves the signal quality of the packaging structure 10.

[0100] In an embodiment, a minimum distance between an edge of the orthographic projection of the clearance region in the direction towards the first element 11 and the first element 11 is greater than or equal to 5 μm.

[0101] In the disclosure, the minimum distance between the edge of the orthographic projection of the clearance region 103 in the direction towards the first element 11 and the first element 11 means a shortest straight-line distance between the orthographic projections of the clearance region 103 and the first element 11 on the plane where the first element 11 is located. As illustrated in FIG. 11, the shortest distance J between the first element 11 and the clearance region 103 is 5 μm.

[0102] Taking the first element 11 being an inductor element as an example, the distance between the edge of the orthographic projection of the clearance region 103 on the first element 11 and the first element 11 will affect an inductance value (L value) and Q value of the inductor element. As illustrated in FIG. 12, the horizontal coordinate represents the minimum distance between the edge of the orthographic projection of the clearance region 103 on the first element 11 and the first element 11, and the vertical coordinate represents the inductance value (L value) of the inductor element. As illustrated in FIG. 13, the horizontal coordinate represents the shortest straight-line distance between the orthographic projections of the clearance region 103 and the first element 11 on the plane where the first element 11 is located, and the vertical coordinate represents the Q value of the inductor element. It may be seen that when the minimum distance between the edge of the orthographic projection of the clearance region 103 on the first element 11 and the first element 11 is greater than 5 μm, the signal from the second chip 2 may be well reduced, and the performance of the first element 11 may be ensured.

[0103] In an embodiment, as illustrated in FIG. 10 and FIG. 11, there are a plurality of first elements 11 and a plurality of clearance regions 103, and the clearance region 103 is arranged corresponding to at least one first element 11.

[0104] For example, as illustrated in FIG. 11, there are nine first elements 11 and five clearance regions 103. Some of the clearance regions 103 are arranged corresponding to two first elements 11, and some of the clearance regions 103 are arranged corresponding to one first element 11.

[0105] By providing the plurality of first elements 11 and the plurality of clearance regions 103, the plurality of the first elements 11 may be integrated on the same first chip 1, to improve the integration of the packaging structure 10.

[0106] In an embodiment, as illustrated in FIG. 10, an orthographic projection of the first element 11 in a direction toward the second chip 2 is polygonal, and a shape of the clearance region 103 is also polygonal.

[0107] For example, as illustrated in FIG. 11, when the orthographic projection of the first element 11 in the direction toward the second chip 2 is rectangular, the shape of the corresponding clearance region 103 is also rectangular. When the orthographic projection of the first element 11 in the direction toward the second chip 2 is octagonal, the shape of the corresponding clearance region 103 is also octagonal.

[0108] It is understood that no first electrical connector 13 or second electrical connector 24 are arranged in the clearance region 103, so that in the clearance region 103, the first chip 1 and the second chip 2 cannot be connected via the first electrical connector 13 and the second electrical connector 24, which reduces a connection area between the first chip 1 and the second chip 2, and reduces a connection stability between the first chip 1 and the second chip 2.

[0109] By configuring both the orthographic projection of the first element 11 in the direction towards the second chip 2 and the shape of the clearance region 103 as polygonal, the orthographic projection may cover the corresponding first element 11 even when the area of the clearance region 103 is small, thereby improving the connection stability between the first chip 1 and the second chip 2, and improving a reliability of the packaging structure 10.

[0110] In an embodiment, as illustrated in FIG. 11, an area of the orthographic projection of the clearance region 103 in the direction towards the first element 11 is larger than an area of a region where the first element 11 is located.

[0111] By setting the area of the orthographic projection of the clearance region 103 in the direction towards the first element 11 to be larger than the area of the region where the first element 11 is located, the signal shielding effect of the shielding element 21 may be improved, and the signal quality of the first element 11 may be further improved, thus improving the signal quality of the packaging structure 10.

[0112] In an embodiment, as illustrated in FIG. 10, a distance D between two adjacent clearance regions 103 is greater than or equal to 20 μm.

[0113] As mentioned above, neither first electrical connector 13 nor second electrical connector 24 is located in the clearance region 103, so that the connection area between the first chip 1 and the second chip 2 in the clearance region 103 is reduced, thus reducing the connection stability between the first chip 1 and the second chip 2.

[0114] By setting the distance between two adjacent clearance regions 103 to be greater than or equal to 20 μm, e.g., 100 μm, it is possible to avoid an excessive density of the clearance regions 103, which may affect the connection stability between the first chip 1 and the second chip 2, thereby improving the reliability of the packaging structure 10.

[0115] In an embodiment, an area of the clearance region 103 is less than or equal to 0.08 mm². The area of the clearance region 103 maybe 0.0625 mm². When the clearance region 103 is smaller than the value described in the embodiment, the connection stability between the first chip 1 and the second chip 2 may be better ensured.

[0116] As mentioned above, no first electrical connector 13 or second electrical connector 24 are arranged in the clearance region 103, so that the first chip 1 and the second chip 2 cannot be connected by means of hybrid bonding in the clearance region 103, which affects the connection stability between the first chip 1 and the second chip 2.

[0117] By setting the area of the clearance region 103 to be less than or equal to 0.08 mm², an area of a region where the first chip 1 and the second chip 2 are not connected with each other may be reduced, which improves the connection stability between the first chip 1 and the second chip 2, thereby improving the reliability of the packaging structure 10.

[0118] According to the packaging structure 10 of embodiments, the first element 11 is arranged on the first chip 1, and the shielding element 21 is arranged on the second chip 2. The first circuit 22 of the second chip 2 is arranged on the side of the shielding element 21 away from the first element 11, so as to reduce the signal interference from the first circuit 22 of the second chip 2 to the first element 11 and reduce the interference from the first element 11 to the first circuit 22, which improves the signal quality of the first element 11, thereby improving the signal quality of the packaging structure 10.

[0119] A packaging method of an embodiment of the disclosure is used to form the packaging structure 10 described in any of the above embodiments.

[0120] The packaging method of the embodiment includes:

• • [0121] providing the first chip 1 having the first element 11;
  • [0122] providing the second chip 2 having the shielding element 21; and
  • [0123] stacking the first chip 1 and the second chip 2, in which the shielding element 21 is arranged on one side of the second chip 2 close to the first chip 1, the active surface of the second chip 2 is arranged opposite to the active surface of the first chip 1, and the shielding element 21 is configured to reduce signal interference from the second chip 2 to the first element 11.

[0124] In some embodiments, providing the first chip 1 having the first element 11, includes:

• • [0125] forming one or more first wiring layers 101 on the active surface of the first chip 1, in which the first wiring layers 101 are arranged along the thickness direction of the packaging structure 10; and
  • [0126] forming the first element 11 via at least one of the first wiring layers 101.

[0127] A chip stacking structure according to an embodiment includes: a substrate and a packaging structure 10 arranged on the substrate, and the packaging structure 10 is the packaging structure 10 according to any of the above embodiments.

[0128] In some embodiments, in the packaging method,

• • [0129] at least one of the first wiring layers 101 is the first top layer 1011, in which the first top layer 1011 is arranged closer to the second chip 2 than other first wiring layers in the thickness direction of the packaging structure 10, and the first element 11 is at least partially arranged on the first top layer 1011.

[0130] In some embodiments, providing the second chip 2 having the shielding element 21, includes:

• • [0131] forming one or more second wiring layers 201 on the active surface of the second chip 2, in which the second wiring layers 201 are arranged along the thickness direction of the packaging structure 10; and
  • [0132] forming the shielding element 21 via at least one of the second wiring layers 201.

[0133] In some embodiments, at least one of the second wiring layers 201 is the second top layer 2011, in which the second top layer 2011 is arranged closer to the first chip 1 than other second wiring layers 201 in the thickness direction of the packaging structure 10, and the shielding element 21 is arranged on the second top layer 2011.

[0134] The chip stacking structure according to embodiments includes: the substrate and the packaging structure 10 arranged on the substrate, and the packaging structure is the packaging structure 10 described in any of the above embodiments.

[0135] An electronic device according to embodiments includes a printed circuit board and the packaging structure 10. The packaging structure 10 is the packaging structure 10 described in any of the above embodiments, and the printed circuit board is connected with the packaging structure 10. Herein, it is to be understood that, orientations and positional relationships indicated by terms such as “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “in”, “out”, “clockwise”, “counterclockwise”, “axial”, “radial” and “circumference” are orientations and positional relationships shown based on the accompany drawings, which are only for the convenience of describing the disclosure and simplifying the description, and do not indicate or imply that the referred devices or elements must have a specific orientation, or be constructed or operated in a specific orientation, so it cannot be understood as limiting the disclosure.

[0136] In addition, terms such as “first” and “second” are used herein for purposes of description and are not intended to indicate or imply relative importance or implicitly specify the number of technical features indicated. Furthermore, the feature defined as “first” or “second” may expressly or implicitly include at least one of those features. Herein, “a plurality of” means at least two, such as two or three, unless specified otherwise.

[0137] In the disclosure, unless specified or limited otherwise, the terms “mounted”, “connected”, “coupled” and “fixed” are understood broadly, such as fixed, detachable couplings or integrated, and can be mechanical or electrical couplings, and also can be direct and via media indirect couplings, and further can be inner couplings of two components or interaction relations between two components, which can be understood by those skilled in the art according to specific situations.

[0138] In the disclosure, unless otherwise expressly specified and limited, a first feature “above” or “below” a second feature means that the first feature and the second feature are in direct contact, or the first feature and the second feature are in indirect contact through an intermediate medium. Moreover, the first feature is “above”, “over” and “on top of” the second feature means that the first feature is directly above or diagonally above the second feature, or simply indicates that the first feature is horizontally higher above the second feature. The first feature is “below”, “under”, and “beneath” the second feature means that the first feature is directly below or diagonally below the second feature, or simply indicates that the horizontal height of the first feature is lower than that of the second feature.

[0139] In the disclosure, the terms “an embodiment”, “some embodiments”, “examples”, “specific examples” or “some examples” etc. mean that a specific feature, structure, material, or characteristic described in combination with the embodiment or example is included in at least one embodiment or example of the disclosure. In the specification, the schematic expressions of the above terms are not necessarily aimed at the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and integrate different embodiments or examples and features of different embodiments or examples described in the specification without conflict.

[0140] Although embodiments have been shown and described above, it is understood that the above embodiments are exemplary and cannot be understood as limitations of the disclosure, and changes, modifications, substitutions, and variations made to the above embodiments by those skilled in the art are within the protection scope of the disclosure.