SANDWICH STRUCTURE FOR VIA AND INTERCONNECT

[0001] The present invention generally relates to the field of microelectronic devices, and more particularly to forming interconnects.

[0002] Nanosheet is the lead device architecture in continuing CMOS scaling are fabricated on the same chip/wafer as MRAM. Interconnects provide connections to different layers of the device where the manufacturing process can lead to variations of the height.

[0003] Additional aspects and/or advantages will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the invention.

[0004] An interconnect includes an underling layer. A first metal line located on top of the underlying layer. A first via is located on top of the first metal line. At least one line divot is located adjacent to the first via and the at least one-line divot extends downwards into the first metal line. A second metal line located on top of the underlying layer. A second via located on top of the second metal line and a sandwich layer is located between the second via and the second metal line.

[0005] An interconnect includes an underling layer. A first metal line located on top of the underlying layer. A first via is located on top of the first metal line. At least one line divot is located adjacent to the first via and the at least one-line divot extends downwards into the first metal line. A second metal line located on top of the underlying layer. A second via located on top of the second metal line and a first sandwich layer is located between the second via and the second metal line. The first sandwich layer is comprised of a first layer and a second layer.

[0006] A method includes the steps of forming a Mx metal layer on an underlying layer. Forming a sandwich layer on top of the Mx metal layer and forming a trench within the sandwich layer, where the trench exposes a top surface of the Mx metal layer. Forming a top metal layer on top of the sandwich layer and the top metal layer fills the trench. Etching the top metal layer, the first layer, and the Mx metal layer to form a plurality of lines. Subtractively etching the top metal layer to remove it from most locations. Where the subtractive etching of the top metal layer forms a first via aligned with location of the trench on one of the plurality of lines. The dimensions of the first via differ from the dimensions of the trench, such that line divots are formed in the Mx metal layer from the subtractive etching process. The subtractive etching of the top metal layer forms a second via located on top of the sandwich layer on one of the plurality of lines.

[0018] The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of exemplary embodiments of the invention as defined by the claims and their equivalents. It includes various specific details to assist in that understanding but these are to be regarded as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the invention. In addition, descriptions of well-known functions and constructions may be omitted for clarity and conciseness.

[0019] The terms and the words used in the following description and the claims are not limited to the bibliographical meanings but are merely used to enable a clear and consistent understanding of the invention. Accordingly, it should be apparent to those skilled in the art that the following description of exemplary embodiments of the present invention is provided for illustration purpose only and not for the purpose of limiting the invention as defined by the appended claims and their equivalents.

[0020] It is understood that the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a component surface” includes reference to one or more of such surfaces unless the context clearly dictates otherwise.

[0021] Detailed embodiments of the claimed structures and the methods are disclosed herein: however, it can be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this invention to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the present embodiments.

[0022] References in the specification to “one embodiment,” “an embodiment,” an example embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one of ordinary skill in the art o affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0023] For purpose of the description hereinafter, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and derivatives thereof shall relate to the disclosed structures and methods, as orientated in the drawing figures. The terms “overlying,” “atop,” “on top,” “positioned on,” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, where intervening elements, such as an interface structure may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating, or semiconductor layer at the interface of the two elements.

[0024] In the interest of not obscuring the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations that are known in the art may have been combined for presentation and for illustrative purposes and in some instance may have not been described in detail. In other instances, some processing steps or operations that are known in the art may not be described at all. It should be understood that the following description is rather focused on the distinctive features or elements of various embodiments of the present invention.

[0025] Various embodiments of the present invention are described herein with reference to the related drawings. Alternative embodiments can be devised without departing from the scope of this invention. It is noted that various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present invention is not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or indirect coupling, and a positional relationship between entities can be direct or indirect positional relationship. As an example of indirect positional relationship, references in the present description to forming layer “A” over layer “B” includes situations in which one or more intermediate layers (e.g., layer “C”) is between layer “A” and layer “B” as long as the relevant characteristics and functionalities of layer “A” and layer “B” are not substantially changed by the intermediate layer(s).

[0026] The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains,” or “containing” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other element not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0027] Additionally, the term “exemplary” is used herein to mean “serving as an example, instance or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiment or designs. The terms “at least one” and “one or more” can be understood to include any integer number greater than or equal to one, i.e., one, two, three, four, etc. The terms “a plurality” can be understood to include any integer number greater than or equal to two, i.e., two, three, four, five, etc. The term “connection” can include both indirect “connection” and a direct “connection.”

[0028] As used herein, the term “about” modifying the quantity of an ingredient, component, or reactant of the invention employed refers to variation in the numerical quantity that can occur, for example, through typical measuring and liquid handling procedures used for making concentrations or solutions. Furthermore, variation can occur from inadvertent error in measuring procedures, differences in manufacture, source, or purity of the ingredients employed to make the compositions or carry out the methods, and the like. The terms “about” or “substantially” are intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of the filing of the application. For example, about can include a range of ±8%, or 5%, or 2% of a given value. In another aspect, the term “about” means within 5% of the reported numerical value. In another aspect, the term “about” means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported numerical value.

[0029] Various processes are used to form a micro-chip that will be packaged into an integrated circuit (IC) fall in four general categories, namely, film deposition, removal/etching, semiconductor doping and patterning/lithography. Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD) among others. Removal/etching is any process that removes material from the wafer. Examples include etching process (either wet or dry), reactive ion etching (RIE), and chemical-mechanical planarization (CMP), and the like. Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or by rapid thermal annealing (RTA). Annealing serves to activate the implant dopants. Films of both conductors (e.g., aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate electrical components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to be changed with the application of voltage.

[0030] Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, where like reference numerals refer to like elements throughout. A subtractive interconnect that was formed using a top via patterning method has a challenge of maintaining uniform height across the chip and wafer as the line height is controlled by top via etch uniformity. One solution is to use an etch stop layer between a metal line and via, but this creates an interface between top via and the metal line which leads to an increase in the contact resistance.

[0031] The present invention is directed towards the formation of interconnects, more specifically forming a via that will be connected to a Mx metal line while the height of the adjacent Mx metal lines are maintained. The present invention provides novel interconnect structure that was formed by a subtractive etching process where the top via is connected to metal line and the height of adjacent metal lines remains constant across chip/wafer. This can be scaled to smaller dimensions for 1 nm technology node and beyond.

[0032] The interconnect structure has vias with and without a sandwich layer located between the via and an underlying metal lines (e.g., Mx metal layer). Recess or divots can be formed in the metal line that contains a via (i.e., a via without a sandwich layer), where the divots are located adjacent to the via. The material (sandwich layer) located between the metal line and the via can be comprised of a material that has anti-fusing properties, for example, SiN, SiO_x, SiC, HfO_x, ZrO_x, Al_xO_x, AlN, etc., or it can be comprised of a material that can form a blocking boundary. Additionally, the middle layer can be comprised of a phase change material, or the middle layer can be comprised of multiple layers

[0033] Referring now to FIGS. 1A and 1B, a structure is shown of an interconnect during an intermediate step of forming the initial structure. FIGS. 1A and 1B illustrate an underlying layer 105, a Mx metal layer 110, and a first layer 115. The underlying layer 105 can be a logic device, a passive device, another electronic structure/device, or a substrate. When the underlying layer 105 is a substrate, then the substrate can be, for example, a material including, but not necessarily limited to, silicon (Si), silicon germanium (SiGe), Si:C (carbon doped silicon), carbon doped silicon germanium (SiGe:C), III-V, II-V compound semiconductor or another like semiconductor. In addition, multiple layers of semiconductor materials can be used as the semiconductor material of the substrate. In some embodiments, substrate includes both semiconductor materials and dielectric materials. The semiconductor substrate may also comprise an organic semiconductor or a layered semiconductor such as, for example, Si/SiGe, a silicon-on-insulator or a SiGe-on-insulator. A portion or the entire semiconductor substrate may also be comprised of an amorphous, polycrystalline, or monocrystalline. The semiconductor substrate may be doped, undoped or contain doped regions and undoped regions therein.

[0034] The Mx metal layer 110 is formed on top of the underlying layer 105. The Mx metal layer 110 can be comprised of Ruthenium (Ru), Copper (Cu), a conductive metal, a conductive alloy, or a combination thereof. The individual metal lines will be subtractively formed from the Mx metal layer 110. The first layer 115 is formed on top of the Mx metal layer 110. The first layer 115 can be comprised of a material that has anti-fusing properties, for example, SiN, SiO_x, SiC, HfO_x, ZrO_x, Al_xO_x, AlN, etc., or the first layer 115 can material that can form a blocking boundary, for example, TaN, TiN, Ta, W, Co, or a similar material. A blocking boundary is a material the prevents the transport or movement of atoms from the Mx metal layer 110 to the via (i.e., the second via 160) that is located on top of the first layer 115. Additionally, the first layer 115 can be comprised of a phase change material or the first layer 115 can be comprised of multiple layers which will be described in further details below (see, for example, FIGS. 9A to 10E). The first layer 115 can have a thickness in the range of about 1 to 15 nanometers.

[0035] FIGS. 2A and 2B illustrate the processing stage after formation of a lithography stack 120 and forming of an initial via locations 125. A lithography stack 120 is formed on top of the first layer 115. The lithography stack 120 can be comprised of one or more layers. FIGS. 2A and 2B illustrate that the lithography stack 120 is comprised of three layers. The number of layers of the lithography stack 120 is not meant to be limiting, the use of three layers in the lithography stack 120 is for illustrative purposes only. The lithography stack 120 is patterned to form initial via locations 125, where the initial via locations 125 are the location where a via 150 will be formed to one of the metal lines.

[0036] FIGS. 3A and 3B illustrate the processing stage after transferring the initial via locations 125 into the first layer 115 and the removal of the lithography stack 120. The initial via locations 125 is transferred into the first layer 115 to form the via trench 130. The via trench 130 exposes a top surface of the Mx metal layer 110. The via trench 130 extends in multiple dimensions (along the X-axis, the Y-axis, and the Z-axis).

[0037] FIGS. 4A and 4B illustrate the processing stage after the formation of the top metal layer 135. A top metal layer 135 is formed on top of the first layer 115 and fills the via trench 130 with material. The filled via trench 130 will be referred to as the connection area 133. Therefore, the top metal layer 135 is connected to the Mx metal layer 110 via connection area 133. The top metal layer 135 can be comprised of Ruthenium (Ru), Copper (Cu), a conductive metal, a conductive alloy, or a combination thereof. The top metal layer 135 can be comprised of the same material as the Mx metal layer 110 or it can be comprised of a different material.

[0038] FIGS. 5A and 5B illustrate the processing stage after the pattering of the interconnect to form a plurality of lines, lines A, B, and C. A lithography layer or lithography stack (not shown) is formed on top of the top metal layer 135. The lithography layer or lithography stack (not shown) and the underlying layers are etched to form a plurality of lines. FIGS. 5A and 5B illustrate the formation of line A, line B, and line C. The number of lines form is not meant to be limiting, but at least two or more lines are formed. The connection area 133 is located on one of the lines, the illustrative example has the connection area located in line B. The line that contains the connection area 133 is not meant to be limiting. The connection area 133 could have been located in either line A or line C, or there could have been multiple connection areas 133, where a connection area 133 can be located in a plurality of different lines. For example, line A and line B could have connections areas 133, where the connection areas 133 are aligned with each other or they can be offset from each other. Alternatively, line A and line C could have connections areas 133, where the connection areas 133 are aligned with each other or they can be offset from each other. The connection area 133 is only illustrated in line B to simplify the illustrations and it is not meant to be limiting in any way. Furthermore, a second via 160 is formed, where the second via 160 comprises a sandwich layer (i.e., a portion of the first layer 115) located between the second via 160 and the Mx metal layer 110. Any location scenario above for connection area 133 can also include a second via 160 type. The second via 160 will be described in further detail below.

[0039] FIGS. 6A and 6B illustrate the processing stage after the formation of a second lithography stack 140. The second lithography stack 140 is formed on top of and around each of the plurality of lines (line A, line B, line C). The second lithography stack 140 can be comprised of one or more layers. FIGS. 6A and 6B illustrate that the second lithography stack 140 is comprised of three layers, where the second lithography stack 140 includes a mask layer 140M. The number of layers of the second lithography stack 140 is not meant to be limiting, the use of three layers in the second lithography stack 140 is for illustrative purposes only. The mask layer 140M is patterned for the formation of vias, where the mask layer 140M remains will be the location of the different vias. One of the remaining mask layers 140M is located over the connection area 133 (i.e., the opening area that was formed in the first layer 115). One of the remaining mask layers 140M is located on top of a section of line A. The dimensions of the connection are 133 and the mask layer 140M are not perfectly aligned. The dimensions of the mask layer 140M is smaller than the dimensions of the connection area 133 to prevent the formation of an overlap area (e.g., an area where the via 150 will overlap the top surface of the first layer 115).

[0040] FIGS. 7A, 7B, 7C, and 7D illustrate the processing stage after a subtractive etching process was utilized on the top metal layer 135. The subtractive etching process removes most of the top metal layer 135 located on top of the first layer 115 on each of the lines A, B, C. The mask layer 140M prevents some of the material of the top metal layer 135 from being removed. This remining portion of the top metal layer 135 will now be referred to as first via 150 and second via 160. The first via 150 is connected to the underlying Mx metal layer 110 of line B via connection area 133. FIG. 7D illustrates a cross section along Line B, that illustrates the effects of the different dimensions of the connection area 133 and mask layer 140M. The dimensions of the mask layer 140M do not perfectly match to the connection area 133 (which corresponds to via trench 130). The differences in the dimensions will cause the subtractive etching process to remove some of the Mx metal layer 110 around the connection area 133 to form line divots 155. The line divots 155 are located adjacent to the connection area 133 and the first via 150. The first layer 115 prevents the substrative etching processing from etching the Mx metal layer 110 of lines A, B, and C, except for the above-mentioned line divots 155. Therefore, the first layer 115 prevents height variations in the Mx metal layer 110 in each of the lines A, B, C. For example, Mx metal layer 110 of line A has a first height or first dimension D1 and the Mx metal layer 110 of Line C has a second height or second dimension D2. The first dimension D1, and the second dimension D2 are substantially equal to each other.

[0041] The second via 160 is located on top of a section of line A, see, for example, FIG. 7C. A portion of the first layer 115 (will also be referred to as sandwich layer 115) is located between the Mx metal layer 110 and the second via 160 of line A. The combined height of the Mx metal layer 110, the first layer 115, and the second via 160 of line A has a height or third dimension D3. The combined height of the Mx metal layer 110, the connection area 133, and the first via 150 of line B has a height or fourth dimension D4. The third dimension D3 is substantially equal to the fourth dimension D4.

[0042] FIGS. 8A, 8B, 8C, and 8D illustrate the processing stage after the removal of most of the first layer 115. The exposed first layer 115 is etched to expose the Mx metal layer 115 of lines A, B, and C. The first layer 115 or sandwich layer 115 that is located between the Mx metal layer 110 and the second via 160 is not removed, see, for example, FIGS. 8B and 8C. The remaining first layer 115 is sandwiched between the second via 160 and the Mx metal layer 110 of Line A. The removal of the first layer 115 located on Line A does not cause the formation of line divots. The sandwiched first layer 115 can act as an anti-fusing layer or as a blocking boundary based on the type of material used for the first layer 115. FIG. 8D illustrates the line divots 155 that extend downwards into the Mx metal layer 110 of Line B. The interconnect undergoes further processing (not shown) to surround each of the plurality of metal lines A, B, C, with a dielectric material (not shown) and electrical contacts (not shown) are formed to connect to the first via 150, and the second via 160.

[0043] FIGS. 9A, 9B, 9C, 9D and 9E illustrate the processing stage after a subtractive etching process was utilized on the top metal layer 135 in the scenario where a second layer 165 was located on top of the first layer 115. Prior to the formation of the top metal layer 135 a second layer 165 can be formed on top of the first layer 115. The second layer 165 can be comprised of, for example, SiN, SiO_x, SiC, HfO_x, ZrO_x, Al_xO_x, AlN, etc.

[0044] The second layer 165 can be etched to remove it from some locations while it remains in other locations (see, for example, FIGS. 9B and 9E). FIGS. 9A, 9B, 9C, 9D and 9E illustrate the situation where an additional line (i.e., Line D) is formed. Line D includes a third via 170. The first layer 115 and the second layer 165 are located between the Mx metal layer 110 of Line D and the third via 170. The combined height of the Mx metal layer 110, the first layer 115, the second layer 165, and the third via 170 of line D has a height or fifth dimension D5. The fifth dimension D5 is substantially equal to the fourth dimension D4 and the third dimension D3. Mx metal layer 110 of line D has a sixth height or sixth dimension D6. The sixth dimension D6 is substantially equal to the second dimension D2 and the first dimension D1.

[0045] FIGS. 9A, 9B, 9C, and 9D illustrate where the dual layer (i.e., the first layer 115, and the second layer 160) is located in line D, while only the first layer 115 is located in Line A. This arrangement is for example, purposes only, Line A can comprise the dual layer sandwich layer instead of only having the first layer 115. Having the dual sandwich layer (i.e., the first layer 115, and the second layer 160) between the Mx metal layer 110 of Line A and Line D and the second and third vias 160, 170, respectively, can form multiple voltage Anti-Fuse memory elements. It can also act as a capacitor between a via and the line below.

[0046] FIGS. 10A, 10B, 10C, 10D and 10E illustrate the processing stage after the removal of most of the first layer 115 and the second layer 165, in the scenario where a second layer 165 was located on top of the first layer 115. The exposed first layer 115 and the second layer 165 are etched to expose the Mx metal layer 115 of lines A, B, C, and D. The first layer 115 that is located between the Mx metal layer 110 and the second via 160 is not removed, see, for example, FIGS. 10B and 10C. The remaining first layer 115 is sandwiched between the second via 160 and the Mx metal layer 115. The removal of the first layer 115 located on Line A does not cause the formation of line divots. The sandwiched first layer 115 can act as an anti-fusing layer or as a blocking boundary based on the type of material used for the first layer 115. FIG. 10D illustrates the line divots 155 that extend downwards into the Mx metal layer 110 of Line B. FIG. 10E illustrates the first layer 115 and the second layer 165 that is located between the Mx metal layer 110 and the third via 170 are not removed, see, for example, FIG. 10E. The remaining portions of the first layer 115 and the second layer 165 that are sandwiched between the third via 170 and the Mx metal layer 110. The removal of the first layer 115 and the second layer 165 located on Line D does not cause the formation of line divots in Line D. The sandwiched first layer 115 and the second layer 165 can act as an anti-fusing layer or as a blocking boundary based on the type of materials used for the first layer 115 and the second layer 165. The interconnect undergoes additional processing (not shown) to surround each of the plurality of metal lines A, B, C, D with a dielectric material (not shown) and electrical contacts (not shown) are formed to connect to first via 150, the second via 160, and the third via 170.

[0047] An interconnect includes an underling layer 105. A first metal line (Line B) located on top of the underlying layer 105. A first via 150 is located on top of the first metal line (Mx metal layer 110 of Line B). At least one line divot 155 is located adjacent to the first via 150 and the at least one-line divot 155 extends downwards into the first metal line (Mx metal layer 110 of Line B). A second metal line (Line A) located on top of the underlying layer 105. A second via 160 located on top of the second metal line (Mx metal layer 110 of Line A) and a sandwich layer 115 is located between the second via 160 and the second metal line (Mx metal layer 110 of Line A).

[0048] The second metal line (Line A) has a first height dimension D1 when measured from a bottom surface of the second metal line (Mx metal layer 110 of Line A) to a bottom surface of the sandwich layer 115. A third metal line (Line C) located on top of the underlying layer 105 and the third metal line (Line C) is located adjacent to the first metal line (Line B). The third metal line (Line C) has a second height dimension D2 and the first height dimension D1 is substantially equal to the second height dimension D2.

[0049] A first combined height dimension D4 is the sum of the height of the first metal line (Mx metal layer 110 of Line B) and the first via 150. A second combined height dimension D3 is a sum of the height of the second metal line (Mx metal layer 110 of Line A), the sandwich layer 115, and the second via 160. The combined first height dimension D4 is substantially equal to the second combined height dimension D3.

[0050] The sandwich layer 115 is comprised of an anti-fusing material. The anti-fusing material is selected from a list consisting of SiN, SiOx, SiC, HfOx, ZrOx, AlxOx, AlN, or a similar material.

[0051] The sandwich layer 115 is comprised of a blocking boundary material. The blocking boundary material is selected from a list consisting of TaN, TiN, Ta, W, Co, or a similar material.

[0052] An interconnect includes an underling layer 105. A first metal line (Line B) located on top of the underlying layer 105. A first via 150 is located on top of the first metal line (Mx metal layer 110 of Line B). At least one line divot 155 is located adjacent to the first via 150 and the at least one-line divot 155 extends downwards into the first metal line (Mx metal layer 110 of Line B). A second metal line (Line D) located on top of the underlying layer 105. A second via 170 located on top of the second metal line (Mx metal layer 110 of Line D) and a first sandwich layer 115, 165 is located between the second via 170 and the second metal line (Mx metal layer 110 of Line D). The first sandwich layer 115, 165 is comprised of a first layer 115 and a second layer 165.

[0053] The second metal line (Line D) has a first height dimension D6 when measured from a bottom surface of the second metal line (Mx metal layer 110 of Line D) to a bottom surface of the sandwich layer 115, 165.

[0054] A third metal line (Line A) located on top of the underlying layer 105 and the third metal line (Line A) is located adjacent to the first metal line (Line B). A third via 160 located on top of the third metal line (Mx metal layer 110 of Line A) and a second sandwich layer 115 is located between the third via 160 and the third metal line (Mx metal layer 110 of Line A).

[0055] The third metal line (Line A) has a second height dimension D1 and the first height dimension D6 is substantially equal to the second height dimension D1.

[0056] A first combined height dimension D4 is the sum of the height of the first metal line (Mx metal layer 110 of Line B) and the first via 150. A second combined height dimension D5 is a sum of the height of the second metal line (Mx metal layer 110 of Line D), the first sandwich layer (first layer 115, and second layer 165), and the second via 170. A third combined height dimension D3 is a sum of the height of the third metal line (Mx metal layer 110 of Line A), the second sandwich layer 115, and the third via 160. The combined first height dimension D4 is substantially equal to the second combined height dimension D5.

[0057] A method includes the steps of forming a Mx metal layer 110 on an underlying layer 105. Forming a sandwich layer 115 on top of the Mx metal layer 110 and forming a trench 130 within the sandwich layer 115, where the trench 130 exposes a top surface of the Mx metal layer 110. Forming a top metal layer 135 on top of the sandwich layer 115 and the top metal layer 135 fills the trench 130. Etching the top metal layer 135, the first layer 115, and the Mx metal layer 110 to form a plurality of lines (line A, line B, line C, etc.). Subtractively etching the top metal layer 135 to remove it from most locations. Where the subtractive etching of the top metal layer 135 forms a first via 150 aligned with location of the trench 130 on one of the plurality of lines (line B). The dimensions of the first via 150 differ from the dimensions of the trench 130, such that line divots 155 are formed in the Mx metal layer 110 from the subtractive etching process. The subtractive etching of the top metal layer 135 forms a second via 160 located on top of the sandwich layer 115 on one of the plurality of lines (line A).

[0058] The sandwich layer 115 is comprised of an anti-fusing material.

[0059] The sandwich layer 115 is comprised of a blocking boundary material.

[0060] While the invention has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims and their equivalents.

[0061] The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the one or more embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.