PATTERNING MATERIAL INCLUDING CARBON-CONTAINING LAYER ANDMETHOD FOR SEMICONDUCTOR DEVICE FABRICATION

[0001] This application is a continuation of U.S. patent application Ser. No. 17/301,071 filed Mar. 24, 2021, which claims priority to provisional application 63/198,136, filed Sep. 30, 2020, which are hereby incorporated by reference in their entireties.

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.

[0003] As semiconductor fabrication processes desire smaller process windows, the spacing desired between elements (i.e., the pitch) of a device decreases and becomes more and more difficult to achieve using traditional optical masks and photolithography equipment. Advancements in photolithography tools can assist in meeting the scaled down processes. For example, extreme ultraviolet (EUV) lithography and immersion lithography have been utilized to support critical dimension (CD) requirements of smaller devices. Additionally, patterning methods themselves have developed to drive formation of features of the desired CD below that of the capability of the lithography equipment itself. While the lithography equipment and patterning advances have been suitable in many respects, further advancements are desirable.

[0011] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

[0012] Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0013] As the pitch of elements of semiconductor devices continue to decrease and dimensions of features continue to shrink, improvements in patterning methods and materials are desired for providing high quality, increased pattern density, and decreased critical dimension (CD) devices. The present disclosure provides for material compositions, material stacks, and methods of implementing said compositions and stacks that can, in some implementations, improve patterning metrics including line width roughness (LWR) and local critical dimension uniformity (LCDU). In some embodiments, the improvements drive the formation of materials using compositions and/or deposition methods that produce high density materials, increased hardness of materials, improved elastic modulus of materials, and/or high etch selectivity of materials that are used in one or more aspects of patterning. These properties alone or in combination can improve LWR and LCDU.

[0014] One feature of semiconductor devices for which aggressive dimension and pitch requirements are being implemented is the back-end-of-the-line (BEOL) features. The BEOL features include those wiring or metallization layers providing an interconnection between individual devices of a substrate. In some embodiments, trenches or via openings are patterned into a dielectric layer. By controlling the configuration of the trenches and via openings, a routing of the interconnection of devices is provided when the trenches or openings are subsequently filled with conductive material.

[0015] Referring to FIG. 1, illustrated is a method 100 of patterning a layer. The method 100 may be used to pattern a layer of a semiconductor device. The semiconductor device may include SRAM and/or other logic circuits, passive components or active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal-oxide semiconductor field effect transistors (MOSFETs), CMOS transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. Exemplary NFETs and PFETs include multi-gate devices such as fin type field effect transistors (FinFET), gate-all-around (GAA) devices, and/or other suitable device types. The semiconductor device can be included in a microprocessor, a memory, and/or other IC device. In some embodiments, the semiconductor device is a portion of an IC chip, a system on chip (SoC), or portion thereof.

[0016] The method 100 may be implemented, in whole or in part, by a system employing deep ultraviolet (DUV) lithography, extreme ultraviolet (EUV) lithography, electron beam (e-beam) lithography, x-ray lithography, and other lithography processes to improve pattern dimension accuracy. Additional operations can be provided before, during, and after the method 100, and some operations described can be replaced, eliminated, or moved around for additional embodiments of the method. The method 100 is an example and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. The method 100 is described below in conjunction with FIGS. 2-16.

[0017] The method 100 begins at block 102 where a target layer or layers are provided for patterning. The target layer is any layer or layers for which patterning is desired. By patterning the target layer(s), the target layer(s) are configured into a plurality of features, comprised of the target layer, having openings interposing the features. The pattern may be directed to various semiconductor device features such as interconnect lines, gate structures, isolation structures, active regions, and the like. In some embodiments, the target layer pattern is provided below the resolution limit of the lithography equipment due to the patterning methods such as multiple-patterning techniques.

[0018] In some implementations, the target layer(s) is provided over a semiconductor structure. The semiconductor structure includes a semiconductor substrate and in some implementations various layers or features disposed on the semiconductor substrate. In an embodiment, the semiconductor substrate includes silicon. Alternatively or additionally, substrate includes another elementary semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Alternatively, substrate is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates can be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods. Within or upon the substrate, there may be various features associated with the semiconductor devices. The features may include transistor features such as gate structures and source/drain regions; isolation features; interconnect features such as metallization layers and vias; and/or other features.

[0019] As but one example, a semiconductor structure 202 is illustrated in FIG. 2. The semiconductor structure 202 includes a base substrate 201 having a plurality of active devices 203 formed thereon. The devices as illustrated include gate structures 205 and source/drain features 207 having interposing isolation features 209. A multi-layer interconnect (MLI) 213 is formed over the devices 203. The MLI 213 may include a dielectric layer 211 formed over the devices and an illustrative contact 215 extending to the source/drain feature 207. The MLI 213 includes various other metallization layers, vertically extending vias, and interposing isolation layers that connect various features of the devices 203 as discussed below.

[0020] The gate 205 is configured to achieve desired functionality according to design requirements of associated device, for example, providing a p-type work function or n-type work function. The gate 205 may include a gate dielectric layer and a gate electrode (for example, a work function layer and a bulk conductive layer). Gate structures 205 may include numerous other layers, for example, capping layers, interface layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof.

[0021] Gate dielectric layer(s) of the gate structure may include a high-k dielectric layer, which includes a high-k dielectric material, which refers to a dielectric material having a dielectric constant that is greater than that of silicon dioxide (k≈3.9). For example, the high-k dielectric layer includes HfO₂, HfSiO, HfSiO₄, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlOx, ZrO, ZrO₂, ZrSiO₂, AlO, AlSiO, Al₂O₃, TIO, TiO₂, LaO, LaSiO, Ta₂O₃, Ta₂O₅, Y₂O₃, SrTiO₃, BaZrO, BaTiO₃ (BTO), (Ba, Sr) TiO₃ (BST), Si₃N₄, hafnium dioxide-alumina (HfO₂—Al₂O₃) alloy, other suitable high-k dielectric material for metal gate stacks, or combinations thereof. The high-k dielectric layer is formed by any of the processes described herein, such as ALD, CVD, PVD, oxidation-based deposition process, other suitable process, or combinations thereof. Gate electrode layer(s) of the gate structure are formed over gate dielectric; gate electrodes includes a conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, molybdenum, cobalt, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAIN, TaCN, TaC, TaSiN, other conductive material, or combinations thereof. In some embodiments, a gate electrode includes a work function layer and a bulk conductive layer. The work function layer is a conductive layer tuned to have a desired work function (e.g., an n-type work function or a p-type work function), and the conductive bulk layer is a conductive layer formed over the work function layer. In some embodiments, the work function layer includes n-type work function materials, such as Ti, silver, manganese, zirconium, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, other suitable n-type work function materials, or combinations thereof. In some embodiments, the work function layer includes a p-type work function material, such as ruthenium, Mo, Al, TiN, TaN, WN, ZrSi₂, MoSi₂, TaSi₂, NiSi₂, WN, other suitable p-type work function materials, or combinations thereof. The bulk (or fill) conductive layer includes a suitable conductive material, such as Al, W, Ti, Ta, polysilicon, Cu, metal alloys, other suitable materials, or combinations thereof. A gate electrode is formed by any of the processes described herein, such as ALD, CVD, PVD, plating, other suitable process, or combinations thereof.

[0022] The source/drain features 207 include doped regions—e.g., n-type dopants and/or p-type dopants—suitable for providing features of the semiconductor device. In some embodiments, the source/drain features 207 comprise epitaxial material. An epitaxy process can use CVD deposition techniques (for example, LPCVD, VPE, and/or UHV-CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. In some embodiments, for the n-type transistors, epitaxial source/drain features include silicon, which can be doped with carbon, phosphorous, arsenic, other n-type dopant, or combinations thereof (for example, forming Si:C epitaxial source/drain features, Si:P epitaxial source/drain features, or Si:C:P epitaxial source/drain features). In some embodiments, for the p-type transistors, epitaxial source/drain features include silicon germanium or germanium, which can be doped with boron, other p-type dopant, or combinations thereof (for example, forming Si:Ge:B epitaxial source/drain features).

[0023] In some implementations, the isolation features 209 are shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, local oxidation of silicon (LOCOS) structures, other suitable isolation structures, or combinations thereof. The isolation features 209 may include a multi-layer structure of suitable dielectrics such as oxides.

[0024] The dielectric layer 211 may be an interlayer dielectric (ILD) part of an MLI. The dielectric layer 211 may include a dielectric material including, for example, silicon oxide, carbon doped silicon oxide, silicon nitride, silicon oxynitride, TEOS-formed oxide, PSG, BSG, BPSG, FSG, xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB-based dielectric material, polyimide, other suitable dielectric material, or combinations thereof. In some embodiments, dielectric layer 211 includes a dielectric material having a dielectric constant that is less than a dielectric constant of silicon dioxide (e.g., k<3.9). In some embodiments, dielectric layer 211 includes a dielectric material having a dielectric constant that is less than about 2.5 (i.e., an extreme low-k (ELK) dielectric material), such as silicon dioxide (SiO₂) (for example, porous silicon dioxide), silicon carbide (SiC), and/or carbon-doped oxide (for example, a SiCOH-based material (having, for example, Si—CH₃ bonds)), each of which is tuned/configured to exhibit a dielectric constant less than about 2.5. The dielectric layer 211 can include a multilayer structure having multiple dielectric materials.

[0025] As introduced above, the MLI 213 includes insulating layers and conductive layers. MLI 213 electrically couples various devices (for example, p-type transistors and/or n-type transistors, resistors, capacitors, and/or inductors) and/or components (for example, gate electrodes and/or epitaxial source/drain features of p-type transistors and/or n-type transistors) disposed on the semiconductor structure 202, such that the various devices and/or components can operate as specified by design requirements of semiconductor device. MLI 213 includes a combination of dielectric layers and electrically conductive layers (e.g., metal layers) configured to form various interconnect structures. The conductive layers are configured to form vertical interconnect features, such as device-level contacts and/or vias, and/or horizontal interconnect features, such as conductive lines. Vertical interconnect features typically connect horizontal interconnect features in different layers (or different planes) of MLI 213. During operation, the interconnect features are configured to route signals between the devices and/or the components of devices and/or distribute signals (for example, clock signals, voltage signals, and/or ground signals) to the devices and/or the components of devices.

[0026] In some embodiments, other features are present on the semiconductor structure 202 including other portions of active or passive devices and interconnections thereof. In other embodiments, various ones or all of the features or devices discussed above are omitted. For example, in an embodiment, the semiconductor structure 202 includes a substrate 201 such as a silicon substrate and the substrate itself is the target layer to be patterned.

[0027] In some implementations, block 102 includes forming a target layer or target layers over the semiconductor structure. In an embodiment, the target layer is an interlayer dielectric (ILD) of a multi-layer interconnect (MLI) such as the ILD layer discussed above. The target layer may be an ILD layer of a higher MLI layer, such as ILD-1, ILD-3 and the like, the numerical designation providing the number of layers above the semiconductor devices. Semiconductor devices can have any number of metallization/ILD layers, in many implementations over 5 or 10 layers. Other examples of target layers may also be possible including a semiconductor substrate, other dielectric layers, semiconductor layers, conductive layers, and/or other suitable layers implemented in semiconductor fabrication.

[0028] Referring to the example of FIG. 3, a target layer 302 is provided on a semiconductor structure 202. In an embodiment, the target layer 302 is an interlayer dielectric (ILD) part of an MLI. A deposition process (such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, FCVD, HARP, HDP, other suitable methods, or combinations thereof) may be used to provide the target layer.

[0029] In an embodiment, the target layer 302 is an ILD layer including a dielectric material including, for example, silicon oxide, carbon doped silicon oxide, silicon nitride, silicon oxynitride, TEOS-formed oxide, PSG, BSG, BPSG, FSG, xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB-based dielectric material, polyimide, other suitable dielectric material, or combinations thereof. In some embodiments, ILD layer includes a dielectric material having a low-k dielectric or an ELK dielectric. The target layer 302 can include a multilayer structure having multiple dielectric materials.

[0030] In other implementations, the target layer 302 may be another dielectric layer, a conductive layer (e.g., interconnection, plate of capacitor, electrode of memory cell, etc.), and/or a semiconductor layer (e.g., gate feature, fin structure, epitaxial layer, etc.) In an implementation, the target layer 302 is a portion of a semiconductor substrate, such as substrate 201. In an embodiment, semiconductor structure 202 includes only substrate 201 such that the target layer is formed directly on substrate 201. Alternatively, the target layer 302 is a portion of the substrate 201, such that no additional features of semiconductor structure 202 (e.g., 203-215 are omitted).

[0031] The method 100 then proceeds to block 104 where a masking layer(s) is formed over the target layer. The masking layer may include a hard mask material. In some embodiments, the masking layer may be a sacrificial layer used for patterning and/or protection of underlying layers. In some embodiments, the masking layer may be a multi-layer structure. In a further embodiment, the masking layer is a tri-layer structure including a hard mask layer (e.g., metal-containing, organic) between dielectric material layers. The masking layer may include anti-reflective coating layer(s).

[0032] Referring to the example of FIG. 3, a masking layer 304 is formed over the target layer 302. In an embodiment, the masking layer 304 includes a first layer 304A, a second layer 304B, and a third layer 304C. In some implementations, the first layer 304A and the third layer 304C include silicon oxide or another dielectric material. In some implementations, the second layer 304B includes a hard mask material such as a metal hard mask material. In an embodiment, the metal hard mask material is TiN. Other exemplary metal hard mask materials include Ti, Ta, W, TaN, WN, and/or other suitable compositions. In other embodiments, the second layer 304B is an organic hard mask. In other embodiments, the hard mask layer is differently configured based upon the lithography needs.

[0033] In some implementations, the thickness of the first layer 304A and/or the third layer 304C are between approximately 100 Å and 500 Å. In a further embodiment, the thickness of the first layer 304A and/or the third layer 304C are between approximately 200 Å and 300 Å. In some implementations, the thickness of the second layer 304B is between approximately 100 Å and 500 Å. In a further embodiment, the thickness of the second layer 304B is between approximately 200 Å and 300 Å. The selected thickness depends upon the etch film selectivity and the etch process parameters. For example, the closer the etch selectivity between materials, an increased thickness may be beneficial. In an embodiment, the masking layer of block 104 is omitted.

[0034] The method 100 then proceeds to block 106 where a first layer of a multi-layer patterning stack is deposited. In some implementations, the multi-layer patterning stack may include three-layers as discussed below. For example, the three layers may include a top or image layer, a middle or transfer layer, and a bottom or base layer. These layers are discussed in the order of deposition, i.e., from bottom to top with respect to blocks 106, 108 and 110 of the method 100. In some embodiments, the multi-layer patterning stack provides an organic/inorganic/organic stack of layers.

[0035] In an embodiment, block 106 deposits the first layer (e.g., base or bottom layer) of a multi-layer patterning stack as a carbon-containing layer. The first layer may comprise a carbon-based material having a carbon (C) composition greater than fifty (50) atomic percent %. Other components of the carbon-containing layer include hydrogen (e.g., amorphous hydrogenated carbon). In an embodiment, the carbon-based layer is amorphous carbon (a-Carbon). In some embodiments, no other atomic components are purposefully deposited in forming the carbon-containing layer, e.g., other than carbon and hydrogen. For example, the atomic percent of carbon may be between approximately 50 and 75% and the remaining 50 to 25 atomic % may be hydrogen. In a further embodiment, the atomic percent of carbon is approximately 65 atomic % and the atomic percent of hydrogen is approximately 35 atomic %. In some implementations, the first layer of carbon-containing material is deposited by chemical vapor deposition (CVD) process such as plasma-enhanced CVD (PECVD). Other CVD processes include high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), sub-atmospheric vapor deposition (SAVCD), or other suitable methods. In an embodiment, the first layer of carbon-containing material is deposited by physical vapor deposition (PVD) such as plasma enhanced (PE) PVD. Other PVD processes include sputtering, electron beam, thermal evaporation, or other suitable methods. In an embodiment, the first layer of carbon-containing material is deposited by atomic layer deposition (ALD) such as plasma-enhanced (PE) ALD.

[0036] The deposition of the carbon-containing layer (e.g., PVD, ALD, CVD processes) can be characterized as using process(es) where molecules of chemical compounds serving as precursors are delivered to the target surface and chemically modified to obtain the desired film. These depositions processes are in contrast to spin-coating or dip-coating processes. In an embodiment, the precursors to forming the carbon-containing layer are delivered in a gaseous form. The following table provides an exemplary, normalized comparison of a spin-on bottom anti-reflective coating layer in comparison to an a-carbon layer that may, for example have been deposited by CVD, ALD or PVD processes.

	Spin-on BARC	a-Carbon
Process temp.	Bake Temperature (BT) ° C.	BT + 30-50% BT ° C.
Stress	“n” MPa	n*(−150) to n *(−75)
		MPa
Hardness	“n” GPa	n*10-n*20 GPa
Modulus	“n” GPa	n*5-n*10 GPa
Density (g/cm3)	“n”	n*1.05-n*1.5
Composition	79.2/20/0.8	65/35/0
(C/H/O)
inspection step	“n”	0.9*n-0.8*n
image waviness

[0037] In some implementations, the deposition of the carbon-containing layer by the methods discussed above includes providing a precursor reactive gas and an inert gas. Example precursors include carbon-containing compounds. In an embodiment, the precursor includes at least one of methane (CH₄), acetylene (C₂H₂), or propylene (C₃H₆). Example inert gases include nitrogen, argon, helium, xenon, other suitable carrier gas constituent, or combinations thereof. In an embodiment, the inert gas includes at least one of argon (Ar) or helium (He). The carbon-containing layer may be deposited by introduction of gaseous precursors (with inert gases) to a chamber, where a heated semiconductor structure is disposed. Reactions between the precursors (and/or between precursors and the surface of the semiconductor structure) creates a solid film layer of carbon-containing material on the semiconductor structure. This process may be performed by the tool illustrated in FIG. 30, discussed below.

[0038] The deposition process of the carbon-containing first layer of a multi-layer patterning stack may include a process temperature of between room temperature (RT) to 600 degrees Celsius. The deposition process of the carbon-containing first layer of a multi-layer patterning stack may include a process pressure of between approximately zero (0) and 100 torr. The pressure and/or temperature are selected to control the disassociation the precursors and the excitement of the carbon atoms. In an embodiment, the process temperature is a temperature of the wafer and/or the process chamber. The power of the deposition (e.g., plasma creation) may be between approximately 10 and 25 MHz. The power is selected to provide provision of plasma and suitable disassociation and reaction of the precursors. The greater the power the higher the disassociation but may risk arcing or other issues in tool performance.

[0039] In some implementations, the carbon-containing first layer is deposited to a thickness of less than 1000 Angstroms (Å). In a further embodiment, the thickness of the carbon-containing film is between approximately 50 and 500 Å. In an embodiment, the thickness of the carbon-containing film is between approximately 100 and 200 Å. The thickness of the carbon-containing layer may be selected based on the etch selectivity to surrounding layers, the tuning of the etching process, the underlying topography, and/or other criteria. For example, a topography underlying the carbon-containing first layer having a high-aspect ratio may demand an increased thickness to suitably cover the topography. In an embodiment, the etch selectivity between the carbon-containing layer and the underlying layer (e.g., masking layer, target layer, intervening layer) may impact the thickness, for example, a greater thickness may be required for a decreased selectivity between the carbon-containing layer and the target layer.

[0040] In some embodiments, prior to forming the carbon-containing layer, another layer is formed between the hard mask and the carbon-containing layer. In certain implementations, this layer is a mandrel layer, such as a layer used to form mandrels in a double patterning process. In other embodiments, the carbon-containing layer is deposited directly on the masking layer (e.g., 304C), such as in the single patterning process.

[0041] Referring to the example of FIG. 4, a bottom layer 402 is formed over the semiconductor structure 202. The bottom layer 402 may be a carbon-containing layer as discussed above. For example, in some embodiments, the bottom layer 402 is amorphous carbon. The bottom layer 402 may be deposited as discussed above by one of PVD, ALD, or CVD processes.

[0042] The method 100 then proceeds to block 108 where a second layer of a multi-layer patterning stack is deposited. The second layer of a multi-layer patterning stack may be a silicon-containing layer. In some embodiments, the second layer of the multi-layer patterning is a silicon-containing hard mask layer. In an embodiment, the second layer is a spin-on glass layer (SOG). In some embodiments, the second layer is a silicon-based material as discussed in the following paragraph(s).

[0043] In some embodiments, the second layer may comprise a silicon-based material having a silicon (Si) composition greater than fifty (50) atomic percent %. Other components of the silicon-containing layer include hydrogen. In an embodiment, the silicon-containing second layer is amorphous silicon. In some implementations, the second layer of silicon-containing material is deposited by chemical vapor deposition (CVD) process such as plasma-enhanced CVD (PECVD). Other CVD processes include high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), sub-atmospheric vapor deposition (SAVCD), other suitable methods. In an embodiment, the second layer of silicon-containing material is deposited by physical vapor deposition (PVD) such as plasma enhanced (PE) PVD. Other PVD processes include sputtering, electron beam, thermal evaporation. In an embodiment, the second layer of silicon-containing material is deposited by atomic layer deposition (ALD) such as plasma-enhanced (PE) ALD. The deposition of the silicon-containing layer (e.g., PVD, ALD, CVD processes) can be characterized as using process(es) where molecules of chemical compounds serving as precursors are delivered to the substrate surface and chemically modified to obtain the desired film. These depositions processes are in contrast to spin-coating or dip-coating processes.

[0044] In some implementations, the deposition of the silicon-containing layer by the methods discussed above includes providing a precursor reactive gas and an inert gas. Example precursors include silicon-containing compounds. Example inert gases include nitrogen, argon, helium, xenon, other suitable carrier gas constituent, or combinations thereof. In an embodiment, the precursor includes at least one of silane (SiH4) or disilane (Si2H6). In an embodiment, the inert gas includes at least one of argon (Ar) or helium (He). The silicon-containing layer may be deposited by introduction of gases precursors (with inert gases) to a chamber, where a heated semiconductor structure is disposed. Reactions between the precursors (and/or surface of the semiconductor structure) creates a solid film layer of silicon-containing material on the semiconductor structure. This process may be performed by the tool illustrated in FIG. 30, discussed below.

[0045] The deposition process of the silicon-containing first layer of a multi-layer patterning stack may include a process temperature of between room temperature (RT) to 600 degrees Celsius. The deposition process of the silicon-containing first layer of a multi-layer patterning stack may include a process pressure of between approximately zero (0) and 100 torr. In an embodiment, the temperature and/or pressure are determined to provide suitable dissociation of the precursors and/or excitability of the silicon atoms. In an embodiment, the process temperature is a temperature of the wafer and/or the process chamber. The power of the deposition may be between approximately 10 and 25 MHz. The power is selected to provide suitable disassociation and reaction of the precursors. The greater the power the higher the disassociation but may risk arcing or other issues in tool performance.

[0046] In some implementations, the silicon-containing second layer is deposited to a thickness of less than 1000 Angstroms (Å). In a further embodiment, the thickness of the silicon-containing film is between approximately 50 and 500 Å. In an embodiment, the thickness of the silicon-containing film is between approximately 100 and 200 Å. The thickness of the silicon-containing layer may be selected based on the etch selectivity to surrounding layers and the tuning of the etching process to provide suitable pattern transfer performance.

[0047] In some embodiments, the silicon-containing layer is deposited directly on the carbon-containing layer. Thus, in some implementations, an amorphous carbon layer is directly interfacing an amorphous silicon layer to provide the base layer and the middle layer of a tri-layer stack. In some implementations, these depositions of block 106 and 108 are performed in-situ for example, in a tool such as illustrated in FIG. 30 below. In some embodiments, block 106 is provided in a tool such as illustrated in FIG. 30, while block 108 includes spin-on coating the silicon-containing layer.

[0048] In an embodiment, the interface between the silicon-containing layer and the carbon-containing layer may be a discrete interface transitioning from a-C to a-Si. In some embodiments, a structure is formed with a continuous variation in the C to Si ratio.

[0049] In some implementations of the method 100, the silicon-containing layer is deposited as amorphous silicon through, for example, CVD, PVD, or ALD processes. In some embodiments, the a-Si material is subsequently modified. For example, during a subsequent patterning step, an etching process may alter this composition (a-Si) in whole or in part. For example, when implementing an oxygen-comprising etch gas (for example, O₂), the silicon-containing layer may getter oxygen atoms. Further, when an etching process (e.g., comprising an oxygen-comprising etch gas) etches the underlying carbon-containing layer, the silicon-containing layer may getter oxygen and/or carbon that converts some or all of the deposited a-Si material to an SiO₂ polymer composition.

[0050] Referring to the example of FIG. 5, a middle layer 502 is formed over the semiconductor structure 202. In an embodiment, the middle layer 502 includes silicon. In a further embodiment, the middle layer 502 is a SOG material. In other embodiments, the middle layer 502 is a silicon-containing layer as discussed above including over 50 atomic % of Si and being deposited by at least one of PVD, ALD, or CVD. For example, in some embodiments, the middle layer 502 is amorphous silicon.

[0051] The method 100 then proceeds to block 110 where a photosensitive layer of the multi-layer patterning stack is deposited. The photosensitive layer may also be referred to as a photoresist or simply resist. The resist layer may be deposited by spin coating process. For example, the spin-coating may include applying a liquid polymeric material onto the semiconductor structure 202 (e.g., the middle layer 502). In an embodiment, the resist layer is a radiation sensitive material to the desired wavelength, such as a photoresist including an I-line resist, a DUV resist including a krypton fluoride (KrF) resist and argon fluoride (ArF) resist, a EUV resist, an electron beam (e-beam) resist, and an ion beam resist. In a further embodiment, the resist is a 193-nm resist. In a further embodiment, the resist is an EUV resist sensitive to the 13.5 nm wavelength exposure of an EUV lithography process. In an embodiment, the resist is sensitive to EUV radiation and is further for negative-tone development (NTD), i.e., its solubility in a NTD developer decreases upon EUV radiation.

[0052] The resist layer may include a polymer back-bone and one or more photosensitive components targeted to the radiation wavelength to be used to pattern the resist layer. The wavelengths include those associated with lithography processes such as deep ultraviolet (DUV) lithography, extreme ultraviolet (EUV) lithography, electron beam (e-beam) lithography, x-ray lithography, and/or other lithography processes. In an embodiment, the resist that employs the chemical amplification is generally referred to as a “chemically amplified resist (CAR)”. The photoresist includes a polymer that resists to etching or ion implantation; an acid generating compound (e.g., photo acid generator (PAG)); and a solvent. In some examples, the polymer also includes at least one acid labile group (ALG) that responds to acid. In some embodiments, the resist includes polymeric chemically amplified for example by polyhydroxystyrene (PHS) group providing sensitivity to EUV lithography for example. In some implementations, non-chemically amplified resist is provided such as polymethylmethacrylate (PMMA) resists. While many resist options are organic, inorganic resists are also possible.

[0053] In some embodiments, the resist layer is formed directly on the middle layer (e.g., a-Si). In some embodiments, a small amount of silicon oxide (e.g., native SiO₂) is formed on the top of the a-Si layer and the resist layer is formed thereon. In other embodiments, such as discussed below, an adhesion layer interposes the resist layer and the middle layer.

[0054] Referring to the example of FIG. 6, a resist layer 602 is deposited. The resist layer 602, the middle layer 502 and the bottom layer 402 provide the multi-layer patterning stack 604, in particular, a tri-layer stack.

[0055] The method 100 then proceeds to block 112 where the photosensitive layer is patterned using a lithography technique. After deposition of the resist layer, which may be conformal, in some implementations the photolithography process includes performing a pre-exposure baking process, performing an exposure process using a mask, performing a post-exposure baking process, and performing a developing process. During the exposure process, the resist layer is exposed to radiation energy (such as ultraviolet (UV) light, deep UV (DUV) light, or extreme UV (EUV) light), where the mask blocks, transmits, and/or reflects radiation to the resist layer depending on a mask pattern of the mask and/or mask type (for example, binary mask, phase shift mask, or EUV mask), such that an image is projected onto the resist layer that corresponds with the mask pattern. In some implementations, the method includes using immersion lithography. Since the resist layer is sensitive to radiation energy as discussed above, exposed portions of the resist layer chemically change, and exposed (or non-exposed) portions of the resist layer are dissolved during the developing process depending on characteristics of the resist layer and characteristics of a developing solution used in the developing process. That is, in lithography patterning, after a resist film is exposed to a radiation, such as a EUV radiation (or alternatively other radiation, such as an electron beam), it is developed in a developer (a chemical solution). The developer removes portions (such as exposed portions as in a positive-tone photoresist or unexposed portions as in a negative-tone photoresist) of the resist film, thereby forming a resist pattern which may include line patterns and/or trench patterns. After development, the patterned resist layer includes a resist pattern that corresponds with the mask. It is noted that in some implementations, the carbon-containing layer and the silicon-containing layer are not affected (e.g., no chemical change) from the exposure or development.

[0056] Referring to the example of FIG. 7, the resist layer 602 is patterned to form a series of masking element features 602′ comprised of exposed and developed resist, and interposing openings. In an embodiment, the pattern is provided by an EUV lithography technique as discussed above.

[0057] The method 100 then proceeds to block 114 where the pattern of the photosensitive layer is etched into the remaining layers of the multi-layer patterning stack to form a masking element. FIGS. 8, 9, 10, and 11 exemplify the etching process(es) used to create the masking element by etching the pattern of the resist layer 602′ into the underlying middle layer 502 and bottom layer 402 of the tri-layer patterning stack 604. The etching process(es) may include a reactive ion etch or plasma etching system. The dry etching process may implement a hydrogen-comprising etch gas (e.g., H₂ and/or CH₄), a nitrogen-comprising etch gas (for example, N₂ and/or NH₃), a chlorine-comprising etch gas (for example, Cl₂, CHCl₃, CCl₄, and/or BCl₃), an oxygen-comprising etch gas (for example, O₂), a fluorine-comprising etch gas (for example, F₂, CH₃F, CH₂F₂, CHF₃, CF₄, C₂F₆, SF₆, and/or NF₃), a bromine-comprising etch gas (e.g., Br, HBr, CH₃Br, CH₂Br₂, and/or CHBr₃), an iodine-comprising etch gas, other suitable etch gas, or combinations thereof. In some embodiments, the dry etching process can use a carrier gas to deliver the etch gas. The carrier gas includes nitrogen, argon, helium, xenon, other suitable carrier gas constituent, or combinations thereof.

[0058] In some implementations, a first step of block 114 is a “descum process.” The descum process may remove (residual) portions of the resist from areas where they are not intended to be, for example if the fidelity to the intended pattern is not complete. This process removes the undesired residual resist material, while also decreasing the desired patterned resist in height. In some embodiments, the descum process may slightly etch the underlying middle layer of the multi-layer patterning stack. FIG. 8 is illustrative of the configuration of the multi-layer patterning stack after the descum process including slight etching into the middle layer 502. The height of the resist features 602′ has been decreased and in some implementations, the top surface rounded. A variety of etching conditions can be chosen for this descum step such as etching steps including an O2/Ar-based descum, a CF4/CHF3-based descum, and/or other suitable etchants.

[0059] Block 114 may proceed to include an etching process of the middle layer, or the silicon-containing layer. In an embodiment, this etching process provides an etch selective to the silicon-containing layer, such as selective to SOG or selective to amorphous silicon depending on the selected composition. The etching process patterns the silicon-containing middle layer according to the pattern of the resist. Referring to the example of FIG. 9, the middle layer 502 is etched providing a patterned middle layer 502′. The etching of the middle layer 502 may stop at a top surface of the bottom layer 402. In some implementations, the patterned middle layer 502′ includes tapered sidewalls, for example, due to the directional etching.

[0060] Block 114 may proceed to include an etching process of the bottom layer, or the carbon-containing layer. In an embodiment, this etching process provides an etch selective to the carbon-containing layer, such as selective to amorphous carbon. The etching process patterns the carbon-containing bottom layer according to the pattern of the resist and/or the patterned middle layer. In some implementations, the resist layer 602′ is removed during the etching process of the bottom layer 402. For example, if the compositions of bottom layer 402 and the resist layer 602 are similar (e.g., organic carbon-based), the etchant may remove both compositions. Referring to the example of FIG. 10, the bottom layer 402 is etched providing a patterned bottom layer 402′. The etching of the bottom layer 402 may stop at a top surface of the masking layer 304. The patterned bottom layer 402′, e.g., patterned a-carbon layer, may have an improved line edge roughness (LER) because of the beneficial properties achieved for its composition during the deposition step (e.g., density, modulus, hardness) as discussed above.

[0061] Another benefit of some embodiments of the method 100 is that after the etching process to pattern the bottom layer 402, there may be less loss of the patterned middle layer 502′. In some implementations, for example, not providing an a-Si deposited layer by ALD, PVD, or CVD as discussed above, the patterned middle layer 502′ (e.g., SOG) may be fully removed from the device. In an embodiment where a-Si is provided as a silicon-containing layer, at least at height h1 of 5 nm of the patterned middle layer 502′ may remain. In some embodiments, a height h1 of approximately 5-15 nm remain. See the remaining middle layer 502′ illustrated in FIG. 10. In an embodiment, a ratio of h1 to h2 is approximately 1:2.5 to 1:5. In an embodiment, a ratio of h1 to d1 is 2:1 to 10:1.

[0062] In some implementations of the method 100 and block 114, the resultant patterned carbon-containing layer and/or the resultant patterned silicon-containing layer may be trimmed, which refers to a reduction in width of the features. Referring to the example of FIG. 11, the patterned features 402′ are decreased in width (x-direction) to provide thinner features (w2). The overlying patterned silicon-containing layer 502′ may be similarly decreased in width. The trimming may be performed by suitable etching process such as an isotropic etch to achieve the desired dimension (e.g., critical dimension). In some implementations, the trimming process may reduce the dimension below the lithography limit of the process implemented in block 112. The trimming may decrease the width by, for example, 10-30%. It is noted that the if the resultant width w2 is too thin, the aspect ratio of the patterned features 402′ may risk collapse of the feature. In some embodiments, the trimmed patterned feature 402′ of the bottom layer of the multi-layer patterning stack is then used to pattern underlying layer(s).

[0063] The method 100 then proceeds to block 116 where the resultant patterned features of the multi-layer patterning stack are used as a masking element during the patterning of underlying layers such as masking layers. The patterning of the underlying layers is dependent on the patterning method being implemented by the method 100. In some embodiments, a target layer may be directly patterned using the masking element provided by the patterned multi-layer patterning stack and thus, block 116 omitted from the method 100. In some embodiments, other patterning layers such as the underlying masking layer(s) (e.g., metal hard mask) may be directly patterned using the masking element provided by the patterned multi-layer patterning stack, which in turn are used to pattern underlying layers. The etching process(es) may include a reactive ion etch or plasma etching system. The dry etching process may implement a hydrogen-comprising etch gas (e.g., H₂ and/or CH₄), a nitrogen-comprising etch gas (for example, N₂ and/or NH₃), a chlorine-comprising etch gas (for example, Cl₂, CHCl₃, CCl₄, and/or BCl₃), an oxygen-comprising etch gas (for example, O₂), a fluorine-comprising etch gas (for example, F₂, CH₃F, CH₂F₂, CHF₃, CF₄, C₂F₆, SF₆, and/or NF₃), a bromine-comprising etch gas (e.g., Br, HBr, CH₃Br, CH₂Br₂, and/or CHBr₃), an iodine-comprising etch gas, other suitable etch gas, or combinations thereof. In some embodiments, the dry etching process can use a carrier gas to deliver the etch gas. The carrier gas includes nitrogen, argon, helium, xenon, other suitable carrier gas constituent, or combinations thereof. The wet etching process may implement a wet etchant solution that includes H₂SO₄ (sulfuric acid), H₂O₂ (hydrogen peroxide), NH₄OH (ammonium hydroxide), HCl (hydrochloric acid), HF (hydrofluoric acid), DHF (diluted HF), HNO₃ (nitric acid), H₃PO₄ (phosphoric acid), H₂O (water) (which can be deionized water (DIW) or ozonated de-ionized water (DIWO₃)), ozone (O₃), other suitable chemicals, or combinations thereof.

[0064] Referring to the example of FIG. 12, the patterned bottom layer 402′ is used as a masking element while etching the masking layer 304 and in particular the dielectric layer 304C to form patterned layer 304C′. In an embodiment, the etching process is selective to the composition of the dielectric layer 304C, such as selective to silicon oxide. In some embodiments, the silicon-containing layer 502′ is removed during the etching of the dielectric layer 304C. In some embodiments, the etching process stops at the hard mask layer 304B, for example, a metal hard mask composition. The etching process may provide for a rounded top surface of the patterned carbon-containing layer 402′.

[0065] Referring to the example of FIG. 13, the patterned bottom layer 402′ (and the patterned dielectric layer 304C′) may be used as an etching mask during the etching of the masking layer 304 and in particular the metal hard mask layer 304B to form the patterned hard mask layer 304B′. In some implementations, etching the metal hard mask layer 304B includes an over-etch that extends into the underlying dielectric layer 304A (e.g., silicon oxide). Generally, the etchant however may be selective to the hard mask layer 304B′ material.

[0066] After the etching of the metal hard mask layer 304B, a flush or clean process may be performed. In some implementations, the flush process may remove the patterned carbon-containing layer 402′ as illustrated in FIG. 14. The patterned hard mask layer 304B′ generally is suitable to provide a masking element for patterning underlying target layer(s).

[0067] The method 100 then proceeds to block 118 where the masking element developed by the previous blocks is used during the etching of a target layer(s). Referring to the example of FIG. 15, the target layer 302 is patterned by an etching process, while the patterned metal hard mask layer 304B′ is used as a masking element defining the pattern to be formed. The patterned target layer 302′ is provided with the same pattern as defined in the overlying resist layer 602 (in some embodiments, having been further defined by a trim process). It is noted in this respect, the method 100 has been described as providing a single patterning process (1 photolithography process); however, other embodiments that apply the method 100 including those with multiple-photo and etch processes are possible. For example, double patterning lithography (DPL) process (for example, a lithography-etch-lithography-etch (LELE) process, a self-aligned double patterning (SADP) process, a spacer-is-dielectric (SID) SADP process, other double patterning process, or combinations thereof), a triple patterning process (for example, a lithography-etch-lithography-etch-lithography-etch (LELELE) process, a self-aligned triple patterning (SATP) process, other triple patterning process, or combinations thereof), other multiple patterning process (for example, self-aligned quadruple patterning (SAQP) process), or combinations thereof.

[0068] In some embodiments, the underlying layer 304A is a similar composition to that of the target layer 302 and thus also patterned during the etching process to form patterned layer 304A′. In other embodiments, the layer 304A is patterned separately to form patterned layer 304A′. In an embodiment, any remaining portion of the hard mask layer 304 may be stripped off after patterning the target layer 302.

[0069] In some embodiments, the target layer 302 is an ILD layer and the patterned target layer 302′ may define openings or trenches within which metallization of the MLI will be formed. In such an embodiment, the method 100 proceeds to filling the trenches with a conductive material, such as a metal; and polishing the conductive material using a process such as chemical mechanical planarization (CMP) to expose the patterned ILD layer, thereby forming the metal lines in the ILD layer. This is illustrated in the conductive features 1602 of FIG. 16, which may provide metal interconnect line.

[0070] In some embodiments, the target layer 302 is a conductive layer to be used for metal lines and is made of copper, aluminum, the like, or a combination thereof. In other embodiments, the target layer 302 is a dielectric layer, such as a low-k dielectric layer, a polymer layer, or the like. In another embodiment, the target layer is a material suitable for a gate structure forming a gate (or dummy gate structure) of a device, for example, polysilicon. In yet other embodiments, the target layer 302 is a substrate and is made of a semiconductor material such as silicon, germanium, diamond, or the like. In such an embodiment, the trenches formed in the target layer of the substrate may define isolation features between fin-like structures suitable for fabricating fin-type field effect transistors (FinFET). In an embodiment, the target layer 302 is a mandrel layer. The mandrel layer may be a masking material such as silicon nitride, an oxide, silicon, amorphous silicon, a combination thereof or any other material that may be patterned and selectively removed. The patterned mandrel layer is then used for further patterning processes for example to achieve smaller dimensions as part of a multi-patterning process such as applying the method 100 to a double patterning technique. The above are non-limiting examples of devices/structures that can be made and/or improved using the method 100 according to various aspects of the present disclosure.

[0071] In some embodiments, due to the properties of the patterning materials and/or steps discussed above, the patterned target layer has very smooth edges and sidewalls, therefore low line-edge roughness (LER) and line-width roughness (LWR) and/or improved local critical dimension uniformity (LCDU). In some embodiments, this is because the material and deposition process (e.g., ALD, CVD, PVD) forming the carbon-containing film and/or the silicon-containing film, provide for material layers that possess high density, improved hardness, desirable modulus, high etch selectivity and/or other benefits. In some implementations, the beneficial properties, such as high density, result because impurities and/or undesired bonding within the material layer can be dissociated by introduction of plasma in the deposition process. The film properties including density, modulus, hardness, etc may be modified through deposition processes knobs such as the gas flow (precursor, inert gases), power, process temperature, substrate temperature, and the like.

[0072] In an embodiment of the method 100, an additional block is provided in which an adhesion layer is formed in the multi-layer patterning stack. For example, in an embodiment, an adhesion layer may be formed between the middle layer (e.g., silicon-containing layer) and the overlying resist layer. The adhesion layer may include a material such as hexamethyldisilazane (HDMS) or a bottom antireflective coating (BARC). In some embodiments, the material of BARC is selected based on the lithography process to be formed such as to provide suitable anti-reflective properties depending on the wavelength of radiation. The thickness of the adhesion layer may be between approximately 0 and 100 Angstroms (Å). In the implementation of the adhesion layer being a surfactant, the thickness may be considered 0 Å due to its nature as a surface treatment. FIG. 17 is illustrative of an adhesion layer 1702 interposing the patterned resist 602′ and the middle layer 502, a silicon-containing layer. FIG. 17 is substantially similar to FIG. 7 and the method 100 progresses with the adhesion layer substantially similar as above. The adhesion layer may be patterned with the middle layer 502.

[0073] In an implementation of the method 100, a topographic structure, such as a patterned layer, may be disposed under the multi-layer patterning stack. Referring to the example of FIG. 18, the multi-layer patterning stack including resist layer 602, the middle layer 502 and the bottom layer 402 04 is disposed over a plurality of features 1802 that are disposed on the masking layer 306.

[0074] As illustrated in FIG. 18, the bottom layer 402, a carbon-containing layer-directly interfaces the plurality of features 1802 and fills the gap therebetween. In some embodiments, the bottom layer 402 is thicker than the plurality of features 1802 by 1.2-4 times the height of the plurality of features 1802. After deposition for example by CVD, PVD, or ALD as discussed above, the bottom layer 402 may be planarized by a suitable process such as chemical mechanical polish (CMP).

[0075] In an embodiment, the plurality of features 1802 are mandrels (e.g., silicon or other sacrificial material) to be used in a multi-patterning scheme such as in a double patterning technique. For example, the method 100 may be employed using a layer of target material that is designed to form the plurality of features 1802. A first multi-layer patterning stack is provided over the target material to pattern the plurality of features 1802. The method 100 may repeat, forming a second multi-layer patterning stack over the plurality of features 1802. The second multi-layer patterning stack may further alter the plurality of features 1802 and/or a pattern of features formed from said plurality of features (e.g., spacer elements formed on the sidewalls of the plurality of features 1802).

[0076] Referring now to FIGS. 19 through 29B, illustrated is an embodiment of the method 100 implemented in a multi-patterning scheme including multiple photolithography and etch processes to pattern a target layer. FIGS. 19 through 29B provide an example of patterning of a back-end-of the line (BEOL) features. In particular, a metallization layer of a multi-layer interconnect is patterned. The description of the method 100 above applies in full force to the description of the embodiment illustrated by FIGS. 19 through 29B.

[0077] FIG. 19 illustrates a device 1900 have a semiconductor structure 202 with a plurality of layers formed thereon. In an embodiment, the semiconductor structure 202 is substantially similar as discussed above, including for example, the presence of active devices such as transistors. Over the semiconductor structure 202 is formed a first ILD layer 1902 and a first metallization layer 1904 of an MLI that interconnects the active devices on the semiconductor structure 202. The ILD layer may include a dielectric material including, for example, silicon oxide, carbon doped silicon oxide, silicon nitride, silicon oxynitride, TEOS-formed oxide, PSG, BSG, BPSG, FSG, xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB-based dielectric material, polyimide, other suitable dielectric material, or combinations thereof. In some embodiments, ILD layer 1902 includes a dielectric material having a dielectric constant that is less than a dielectric constant of silicon dioxide (e.g., k<3.9). In some embodiments, ILD layer 1902 includes a dielectric material having a dielectric constant that is less than about 2.5 (i.e., an extreme low-k (ELK) dielectric material), such as silicon dioxide (SiO₂) (for example, porous silicon dioxide), silicon carbide (SiC), and/or carbon-doped oxide (for example, a SiCOH-based material (having, for example, Si—CH₃ bonds)), each of which is tuned/configured to exhibit a dielectric constant less than about 2.5. The dielectric layer 1902 can include a multilayer structure having multiple dielectric materials. The first metallization layer 1904 may be a conductive material such as copper, aluminum, tungsten, and/or other suitable materials. The first metallization layer 1904 may be a multi-layer structure including for example, liner layers, barrier layers, adhesion layers, and/or other suitable layers.

[0078] An etch stop layer 1906 is disposed over the ILD layer 1902 and the first metallization layer 1904. In an embodiment, the etch stop layer 1906 includes multiple layers. The etch stop 1906 may include SiC, SiN, TEOS, hard black diamond (HBD), or other suitable composition. Over the etch stop layer 1906, another ILD layer 1908 is disposed. The ILD layer 1908 may be the target layer for patterning. For example, in some implementations, trenches are to be patterned in the ILD layer 1908 within which conductive material (e.g., copper) will be deposited to form a metallization layer by a damascene or dual-damascene process. In some embodiments, if the first metallization layer 1904 is metallization layer M, the ILD layer 1908 and the metallization layer that is to be formed within said layer is metallization layer M+1. The ILD layer 1908 may be substantially similar to the first ILD layer 1902 and may include the same or different composition than that of the first ILD layer 1902.

[0079] Above the target ILD layer 1908, a hard mask layer 1910 is disposed. In some implementations, the hard mask layer 1910 is substantially similar to the masking layer 304. In an embodiment, the hard mask layer 1910 includes a first layer 1910A, a second layer 1910B, and a third layer 1910C. In an embodiment, the third layer 1910C is a dielectric layer such as TEOS. In an embodiment, the second layer 1910B is a metal hard mask layer such as TiN. Other exemplary metal hard mask materials include Ti, Ta, W, TaN, WN, and/or other suitable compositions. In an embodiment, the first layer 1910A is a nitrogen free anti-reflection layer (NFARL).

[0080] A mandrel layer 1912 is disposed over the hard mask layer 1910. In an embodiment, the mandrel layer 1912 is silicon such as amorphous silicon, polysilicon, etc. The mandrel layer 1912, when patterned, is used provide sacrificial features implemented to reduce the pitch of the patterned features by providing spacer material over the features/mandrels, providing spacer features on the sidewalls of the mandrels, and subsequently removing the mandrels to allow the spacer features to define a reduced pitch. The mandrel-spacer techniques include self-aligned double patterning (SADP) process which reduces the pitch of the exposed pattern by half, self-aligned quadruple patterning (SAQP) process which reduces the pitch of the exposed pattern by a quarter, and other spacer patterning processes.

[0081] Referring now to FIGS. 20A and 20B, a first photolithography process is performed. The first photolithography process may be referred to as a cut process providing in some embodiments to define a space between subsequently formed metallization features. FIG. 20A illustrates that the first lithography process includes forming a multi-layer patterning stack 604 over the mandrel layer 1912. The multi-layer patterning stack 604 includes a bottom layer (carbon-containing layer) 402, a middle layer (silicon-containing layer) 502, and a resist layer that is patterned by the first photolithography process to provide patterned resist layer 602″. The multi-layer patterning stack 604 is substantially similar to as discussed above including providing a carbon-containing layer 402 (e.g., a-C) deposited by at least one of CVD, ALD, or PVD processes. In an embodiment, the silicon-containing layer 502 (e.g., a-Si) is deposited by at least one of CVD, PVD, or ALD processes. In an embodiment, the patterned resist layer 602″ is formed by an EUV process. In other embodiments, other lithography techniques may be implemented.

[0082] FIGS. 21A and 21B illustrate the device 1800 after an etching process providing the pattern of FIGS. 20A and 20B. The etching process patterns the mandrel layer 1912 to form a patterned mandrel layer 1912′. The multi-layer patterning layer 604 is used as a masking element during the etching to form the patterned mandrel layer 1912′. After the etching process, the multi-layer patterning layer 604 may be removed.

[0083] Referring now to FIG. 22, a second photolithography process is performed. The second photolithography process may define portions of a metallization routing layout including a first set of metallization lines. FIG. 22 illustrates that the second lithography process includes forming another multi-layer patterning stack 604 over the mandrel layer 1912. The multi-layer patterning stack 604 includes a bottom layer (carbon-containing layer) 402, a middle layer (silicon-containing layer) 502, and a resist layer that is patterned by the second photolithography process to provide patterned resist layer 602″. The multi-layer patterning stack 604 is substantially similar to as discussed above including providing a carbon-containing layer 402 and/or a silicon-containing layer 502 deposited by at least one of CVD, ALD, or PVD processes. The multi-layer patterning stack 604 is formed over a topographically varying feature—the patterned mandrel layer 1912′. In an implementation, the carbon-containing layer 402 directly interfaces the patterned mandrel layer 1912′. In a further embodiment, the amorphous carbon composition of the carbon-containing layer 402 directly interfaces the patterned mandrel layer 1912′. In an embodiment, the patterned resist layer 602′″ is formed by an EUV process. In other embodiments, other lithography techniques may be implemented.

[0084] FIGS. 23A and 23B illustrate the device 1900 after an etching process providing the pattern of FIG. 22. The etching process patterns the mandrel layer 1912′ to form a patterned mandrel layer 1912″. The multi-layer patterning layer 604 of FIG. 21 is used as a masking element during the etching to form the patterned mandrel layer 1912″. After the etching process, the multi-layer patterning layer 604 may be removed.

[0085] Referring now to FIGS. 24A and 24B, a conformal spacer material layer 2402 is formed over the semiconductor structure 202 including the mandrels 1912″. The spacer material layer 2402 may include a dielectric material such as, titanium nitride, silicon nitride, silicon oxide, titanium oxide, and/or other suitable materials. The spacer material layer 2402 can be formed by various processes, including a deposition process by a CVD or PVD process.

[0086] Referring now to FIGS. 25A and 25B, the conformal spacer material layer 2402 of FIGS. 24A and 24B is etched back to form spacer elements 2502. The etching process may be an anisotropic etching process such as by plasma etching. The width of the spacing “s” may be reduced such that it is below the resolution of the lithography technique applied.

[0087] Referring now to FIGS. 26A and 26B, a third photolithography process is performed. The third photolithography process may define portions of a metallization routing layout including a second set of metallization lines. FIGS. 26A and 26B illustrate that the third lithography process includes forming another multi-layer patterning stack 604 over the patterned mandrel layer 1912″ and the spacer elements 2502. The multi-layer patterning stack 604 includes a bottom layer (carbon-containing layer) 402, a middle layer (silicon-containing layer) 502, and a resist layer that is patterned by the second photolithography process to provide patterned resist layer 602″ “. The multi-layer patterning stack 604 is substantially similar to as discussed above including providing a carbon-containing layer 402 and/or a silicon-containing layer 502 deposited by at least one of CVD, ALD, or PVD processes. The multi-layer patterning stack 604 is formed over a topographically varying feature—the patterned mandrel layer 1912” and spacer elements 2502. In an implementation, the carbon-containing layer 402 directly interfaces each of the patterned mandrel layer 1912″ and the spacer elements 2502. In a further embodiment, the amorphous carbon composition of the carbon-containing layer 402 directly interfaces each of the patterned mandrel layer 1912″ and the spacer elements 2502. In an embodiment, the patterned resist layer 602″″ is formed by an EUV process. In other embodiments, other lithography techniques may be implemented.

[0088] FIGS. 27A and 27B illustrate the device 1900 after an etching process providing the pattern of FIGS. 26A and 26B in combination with the previously formed patterned mandrel layer 1912″. Specifically, the resist 602″″ provides openings where certain portions of the patterned mandrel layer 1912″ are removed (e.g., between spacer elements 2502 at the center of the illustrated portion of device 1900). Afterward, the masking layer 1910 may be etched according to the pattern provided by the mandrel and spacer elements (i.e., the summation of the first, second and third lithography processes) thereby providing patterned masking layer 1910′. The patterned masking layer 1910′ includes patterning the hard mask layer 1910B. After patterning to for the patterned masking layer 1910′, the overlying layers may be removed.

[0089] FIGS. 28A and 28B illustrate a subsequent step of provide a pattern of trenches and via openings according to the pattern of the masking layer 1910′ into the target ILD layer 1908, thereby providing patterned target ILD layer 1908′. The trenches and via openings 2802 define the routing of the metallization layers and/or vias of a layer of the MLI structure of device 1900. Thus, the trenches and via openings 2802 are subsequently filled with conductive material to provide interconnects 2902 of FIGS. 29A and 29B. The interconnects 2902 may include copper, aluminum, alloys, and/or other suitable conductive materials. The interconnects 2902 may include a multi-layer structure includes barrier layers, seed layers, liner layers, and the like. Exemplary barrier layers include titanium, titanium nitride, tantalum, tantalum nitride, or other alternatives. After deposition of the conductive material, various processes such as a planarization process (e.g., CMP) may be formed.

[0090] Thus, the series of FIGS. 19-29B provide for an exemplary implementation of the method 100. As illustrated, the method 100 can be implemented multiple times in order to pattern a single target layer. The properties of the multi-layer patterning stack 604 can provide, in some implementations, an improvement of pattern quality. For example, LWR and/or LCDU may be improved for the patterned carbon-containing layer (and in some embodiments, the patterned silicon-containing layer), which allows for improved fidelity of the reproduction of the pattern in an underlying target layer. While not wanting to be constrained to any theory, it is believed that the deposition processes and/or material composition of the multi-layer patterning stack can provide for material properties that allow for improved performance in the patterning process such as increased density, hardness, desired modulus or high etch selectivity.

[0091] FIG. 30 illustrates a fabrication tool 3000 that may be used to perform one of more steps of the methods discussed herein. In an embodiment, the fabrication tool 3000 is a chemical vapor deposition tool. In an embodiment, the fabrication tool 3000 is an atomic layer deposition tool. In an embodiment, the fabrication tool 3000 is a physical vapor deposition tool. In particular, the fabrication tool 3000 may be used to deposit the carbon-containing layer as discussed above. In some embodiments, the fabrication tool 3000 may further be used to deposit the silicon-containing layer. In some implementations, precursors in gaseous form are provided to the chamber 3002. Between an upper cathode and a lower cathode, a semiconductor structure such as the semiconductor structure 202 is provided. The semiconductor structure 202 may be in the form of a wafer. An RF power is provided to the upper electrode. The heat, pressure and/or power or plasma-creation applied to the chamber 3002 may assist in the reaction of precursor gases. The reaction creates a layer on the structure 202. As discussed above, in some implementations, this layer is an amorphous carbon layer.

[0092] FIG. 30 illustrates an exemplary precursor to forming a carbon-containing layer including acetylene. This precursor enters the chamber as is disassociated into carbon and hydrogen, which are then either deposited or outgassed from the chamber 3002.

[0093] In one exemplary aspect, the present disclosure is directed to a method for lithography patterning including providing a substrate, forming a target layer over the substrate, and forming a patterning layer. Forming the patterning layer includes depositing a first layer having a composition including at least 50 atomic percentage carbon; depositing a second layer including silicon; and depositing a photosensitive layer on the second layer.

[0094] In a further embodiment, the target layer is an interlayer dielectric (ILD) layer formed over the substrate. In some implementations, patterning the photosensitive layer defines a metallization layer to be formed in the ILD layer. In an embodiment, depositing the first layer is performed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). In an embodiment, photosensitive layer is deposited by spin-on coating. In an embodiment, depositing the first layer includes forming an amorphous carbon layer. The depositing the composition includes depositing carbon and hydrogen by at least one of CVD, ALD, or PVD in some embodiments. In an embodiment, depositing the second layer including silicon includes depositing spin-on glass. In a further embodiment, depositing the second layer includes depositing amorphous silicon. In yet a further embodiment, the amorphous silicon is deposited by at least one of atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD). In an embodiment, the method also includes depositing an adhesion layer between the second layer and the photosensitive layer.

[0095] In another exemplary aspect, the present disclosure is directed a method for lithography patterning. The method includes providing a target layer and depositing a carbon-containing layer over the target layer using a deposition process providing of precursors delivered toward a surface and chemically modifying the precursors to obtain the carbon-containing layer on the surface. The carbon-containing layer has at least 50% carbon. A silicon-containing layer is formed on the carbon-containing layer. A resist layer is formed over the silicon-containing layer. A portion of the resist layer is exposed to a radiation to provide a patterned resist layer. A portion of the silicon-containing layer is etched to be uncovered by the patterned resist layer to form a patterned silicon-containing layer. After etching the portion of the silicon-containing layer, a portion of the carbon-containing layer uncovered by the patterned silicon-containing layer is etched to form a patterned carbon-containing layer. The patterned carbon-containing layer is used to define a pattern in the target layer.

[0096] In an embodiment, the deposition process is chemical vapor deposition (CVD) or physical vapor deposition. In an embodiment, the method further includes trimming the patterned carbon-containing layer prior to the using the patterned carbon-containing layer to define the pattern. In an embodiment, the deposition process is atomic layer deposition (ALD).

[0097] In another exemplary aspect, the present disclosure is directed to a method of patterning a semiconductor device. The method includes depositing an amorphous carbon layer over a substrate; depositing a silicon-containing layer directly on the amorphous carbon layer; and spin coating a photosensitive layer over the silicon-containing layer. The method continues to include using a lithography process (e.g., EUV) to pattern the photosensitive layer to provide a first opening. The silicon-containing layer is etched through the first opening. The etched silicon-containing layer is used as a masking element during an etching of the deposited amorphous carbon layer.

[0098] In an embodiment, the method includes depositing the silicon-containing layer includes forming amorphous silicon. In a further embodiment, depositing the amorphous carbon includes chemical vapor deposition, atomic layer deposition, or physical vapor deposition. In an embodiment, the etched amorphous carbon layer is used as a masking element to pattern a hard mask layer under the amorphous carbon layer. In a further embodiment, the patterned hard mask layer is used to define trenches in an interlayer dielectric layer on the substrate.

[0099] The foregoing outlines features of several embodiments so that those of ordinary skill in the art may better understand the aspects of the present disclosure. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.