DISPLAY PANEL WITH DEFECT DETECTION AND DISPLAY PANEL MOTHERBOARD

[0001] The present disclosure is a continuation application of US Patent Application No. 18/282,994, filed on September 19, 2023, which is a U.S. national phase application based on PCT/CN2022/103365, filed on July 1, 2022, and is claims priority to Chinese Patent Application No. 202110871538.X, filed on July 30, 2021, and entitled "DISPLAY PANEL AND DISPLAY PANEL MOTHERBOARD", all of which are hereby incorporated by reference in their entireties for all purposes.

[0002] The present disclosure relates to the field of display technologies, and in particular, relates to a display panel and a display panel motherboard.

[0003] A display panel motherboard may include a plurality of connected display panels, and the display panel motherboard may be cut to acquire separate display panels. At present, a peripheral circuit unit is usually provided in a peripheral region of a display panel to detect various circuits inside the display panel.

[0004] Embodiments of the present disclosure provide a display panel and a display panel motherboard. The technical solutions are as follows.

[0005] According to an aspect of the present disclosure, a display panel is provided. The display panel includes a driver circuit, at least one first line, and at least one second line in one-to-one correspondence with the at least one first line;

• • [0006] wherein a first line among the at least one first line includes a first sub-line and a second sub-line arranged separately from each other, wherein the first sub-line is electrically connected to the driver circuit and a second line corresponding to the first line respectively, one end of the second sub-line is electrically connected to the second line corresponding to the first line, and another end of the second sub-line is exposed out of an edge of the display panel;
  • [0007] and wherein the second sub-line is configured to be electrically connected to a peripheral circuit unit outside the display panel prior to cutting of a display panel motherboard including the display panel.

[0008] Optionally, the second line and the first sub-line are located at different layers, and the second line and the second sub-line are located at different layers.

[0009] Optionally, the display panel includes a base substrate and a first insulating layer disposed on the base substrate;

• • [0010] and the at least one first line includes a first to-be-detected line, the at least one second line includes a first conductive line, wherein the first to-be-detected line and the first conductive line are disposed on two sides of the first insulating layer respectively, a first sub-line and a second sub-line in the first to-be-detected line are located at a same layer, the first sub-line in the first to-be-detected line is electrically connected to the first conductive line through a first via hole in the first insulating layer, and the second sub-line in the first to-be-detected line is electrically connected to the first conductive line through a second via hole in the first insulating layer.

[0011] Optionally, the first to-be-detected line is disposed between the first insulating layer and the base substrate, and the first conductive line is disposed on one side, distal from the base substrate, of the first insulating layer.

[0012] Optionally, the display panel further includes a second insulating layer, wherein the second insulating layer is disposed between the first insulating layer and the base substrate;

• • [0013] the at least one first line further includes a second to-be-detected line, wherein the second to-be-detected line is disposed between the second insulating layer and the base substrate; and
  • [0014] a first sub-line and a second sub-line in the second to-be-detected line are located at a same layer, the first conductive line is electrically connected to the first sub-line in the second to-be-detected line through a third via hole in the first insulating layer and the second insulating layer, and the first conductive line is electrically connected to the second sub-line in the second to-be-detected line through a fourth via hole in the first insulating layer and the second insulating layer.

[0015] Optionally, the display panel further includes a second insulating layer, wherein the second insulating layer is disposed between the first insulating layer and the base substrate; the at least one first line further includes a second to-be-detected line, wherein the second to-be-detected line is disposed between the second insulating layer and the base substrate, a first sub-line and a second sub-line in the second to-be-detected line are located at a same layer;

• • [0016] the first line further includes a first transfer line, wherein the first transfer line is disposed between the first insulating layer and the second insulating layer, the first transfer line is electrically connected to the first sub-line in the second to-be-detected line through a fifth via hole in the second insulating layer, and the first transfer line is electrically connected to the first conductive line through a sixth via hole in the first insulating layer;
  • [0017] and the at least one first line further includes a second transfer line, wherein the second transfer line is electrically connected to the second sub-line in the second to-be-detected line through a seventh via hole in the second insulating layer, and the second transfer line is electrically connected to the first conductive line through an eighth via hole in the first insulating layer.

[0018] Optionally, the display panel further includes a second insulating layer, wherein the second insulating layer is disposed between the first insulating layer and the base substrate; the at least one first line further includes a second to-be-detected line, wherein the second to-be-detected line is disposed between the second insulating layer and the base substrate, and a first sub-line and a second sub-line in the second to-be-detected line are located at a same layer;

• • [0019] and the at least one second line further includes a second conductive line, wherein the second conductive line is disposed on one side, distal from the base substrate, of the second insulating layer, and
  • [0020] the second conductive line is electrically connected to the first sub-line in the second to-be-detected line through a ninth via hole in the second insulating layer and is also electrically connected to the second sub-line in the second to-be-detected line through a tenth via hole in the second insulating layer.

[0021] Optionally, the first conductive line is electrically connected to the first sub-line in the first to-be-detected line through at least two via holes in the first insulating layer.

[0022] Optionally, a material of the first conductive line includes a transparent non-metallic conductive material.

[0023] Optionally, the display panel includes a pixel electrode, wherein the first conductive line and the pixel electrode are located at a same layer.

[0024] According to another aspect of the present disclosure, a display panel motherboard is provided. The display panel motherboard includes at least one display panel and a redundant substrate disposed outside the display panel; wherein

• • [0025] the display panel includes a driver circuit, at least one first line, and at least one second line in one-to-one correspondence with the at least one first line; a first line among the at least one first line includes a first sub-line and a second sub-line arranged separately from each other, wherein
  • [0026] the first sub-line is electrically connected to the driver circuit and the second line corresponding to the first line respectively, and one end of the second sub-line is electrically connected to the second line corresponding to the first line;
  • [0027] and the redundant substrate is provided with a peripheral circuit unit and at least one extension line electrically connected to the peripheral circuit unit, wherein the at least one extension line is in one-to-one correspondence with the at least one first line, and another end of the second sub-line is electrically connected to an extension line corresponding to the first line.

[0028] Optionally, the display panel includes a base substrate and a first insulating layer disposed on the base substrate;

• • [0029] the at least one first line includes a first to-be-detected line, the at least one conductive line includes a first conductive line, wherein the first to-be-detected line and the first conductive line are disposed on two sides of the first insulating layer respectively, a first sub-line and a second sub-line in the first to-be-detected line are located at a same layer, the first sub-line in the first to-be-detected line is electrically connected to the first conductive line through a first via hole in the first insulating layer,
  • [0030] and the second sub-line in the first to-be-detected line is electrically connected to the first conductive line through a second via hole in the first insulating layer;
  • [0031] the at least one extension line includes a first extension line, wherein the first extension line corresponds to the first to-be-detected line, and the first to-be-detected line includes a first signal line; and the display panel motherboard further includes a control unit, wherein the first extension line is electrically connected to the control unit, and the control unit is electrically connected to the peripheral circuit unit.

[0032] Optionally, the display panel further includes a second insulating layer, wherein the second insulating layer is disposed between the first insulating layer and the base substrate;

• • [0033] the at least one first line further includes a second to-be-detected line, wherein the second to-be-detected line is disposed between the second insulating layer and the base substrate;
  • [0034] a first sub-line and a second sub-line in the second to-be-detected line are located at a same layer, the first conductive line is electrically connected to the first sub-line in the second to-be-detected line through a third via hole in the first insulating layer and the second insulating layer, and the first conductive line is electrically connected to the second sub-line in the second to-be-detected line through a fourth via hole in the first insulating layer and the second insulating layer;
  • [0035] the at least one extension line includes a second extension line, wherein the second extension line corresponds to the second to-be-detected line, and the second to-be-detected line includes a second signal line; and
  • [0036] the second extension line is electrically connected to the peripheral circuit unit.

[0037] Optionally, the control unit is disposed in the redundant substrate.

[0038] Optionally, the display panel is provided with an active area and a peripheral region surrounding the active area, and a fanout region is provided in the peripheral region between a first edge of the active area and a second edge of the display panel; and

• • [0039] the control unit and the peripheral circuit unit are disposed in the redundant substrate outside a third edge of the display panel, wherein the third edge is an edge opposite to the second edge;

[0040] Optionally, the display panel is provided with an active area and a peripheral region surrounding the active area, and a fanout region is provided in the peripheral region between a first edge of the active area and a second edge of the display panel; and the control unit and the peripheral circuit unit are disposed in the redundant substrate outside the second edge of the display panel.

[0041] Optionally, the display panel is provided with an active area and a peripheral region surrounding the active area, wherein the peripheral region outside a first edge of the active area is provided with a fanout region, the control unit is disposed in the peripheral region outside a fourth edge of the active area, wherein the fourth edge is an edge opposite to the first edge.

[0042] Optionally, the display panel is provided with an active area and a peripheral region surrounding the active area, and a fanout region is provided in the peripheral region between a first edge of the active area and a second edge of the display panel; the peripheral circuit unit includes two peripheral circuit sub-units, wherein the two peripheral circuit sub-units are respectively disposed in the redundant substrate outside two ends of a second edge.

[0060] For clearer descriptions of the objects, technical solutions, and advantages of the present disclosure, the implementations of the present disclosure are further described in detail below with reference to the drawings.

[0061] FIG. 1 is a schematic structural diagram of a display panel motherboard. As shown in FIG. 1, the display panel motherboard includes a display panel. The display panel motherboard 10 includes the display panel 11 and a to-be-cut plate 12 disposed at the periphery of the display panel 11, and a plurality of display panels 11 may be simultaneously manufactured on the display panel motherboard. The display panel 11 includes an active area (AA) 111 and a peripheral region 112 surrounding the active area 111. The peripheral region 112 includes a data line 1125 and a gate control signal line 1126 which are disposed on a fanout region. The peripheral region 112 further includes an integrated circuit (IC) chip region 1121 disposed on one side of the fanout region, an outer lead bonding (OLB) 1122, and two flexible printed circuits (FPC) 1123, and the two flexible printed circuits 1123 are respectively disposed on two sides of the IC chip region 1121. The IC chip region 1121 is configured for the subsequent placement of the IC chip.

[0062] The peripheral region 112 further includes gate drivers on array (GOA) 1124 on two sides of the active area 111.

[0063] In the related art, upon manufacturing of the display panel motherboard, defect detection needs to be performed on the display panel motherboard, and the defect detection includes an electric test (ET). Then the display panel motherboard is cut to be manufactured into the display panel. Detection units are usually disposed on two sides of the IC chip region 1121 on the display panel 11.

[0064] However, the display panel 11 in the display panel motherboard 10 may be a special-shaped screen. The special-shaped screen is different from the appearance of a rectangular screen of a conventional display panel. The special-shaped screens may include polygonal screens with large chamfers and circular screens. The peripheral region of the special-shaped screen is generally narrow.

[0065] As an area of the fanout region side of the peripheral region 112 is small, the display panel 11 cannot set a position for placing the detection unit, and thus defect detection cannot be performed on the display panel motherboard in the manufacturing process.

[0066] Alternatively, the data line and the gate control signal line in the display panel are directly connected to an external detection unit in the manufacturing process to perform detection. However, upon the display panel motherboard being cut into the display panel, the data line and the gate control signal line are exposed out of the edge of the display panel and then are easily corroded by external environments, and corrosion on the data line and the gate control signal line extends into the display panel along the to-be-detected line, causing the poor display effect of the display panel.

[0067] Embodiments of the present disclosure provide a display panel and a display panel motherboard, which can solve the problems in the related art described above.

[0068] FIG. 2 is a schematic structural diagram of a display panel according to some embodiments of the present disclosure. FIG. 3 is a schematic cross-sectional diagram of the display panel shown in FIG. 2 along a connection line F1-F2. Referring to FIG. 2 and FIG. 3, the display panel 21 includes a driver circuit (not shown in FIG. 2), at least one first line 211, and at least one second line 212 in one-to-one correspondence with the at least one first line 211. The second line 212 may be an anti-corrosion second line. The display panel 21 is provided with an active area 214 and a peripheral region 213 surrounding the active area 214, and the driver circuit is disposed on the active area 214 and the peripheral region 213 of the display panel 21. The driver circuit may be a circuit structure in the display panel 21 electrically connected to a light-emitting device in the display panel 21 and used to drive the light-emitting device to emit light. Herein, the first line 211 may generally serve as an object to be detected, and the second line 212 may generally use for electrical conduction.

[0069] A first line 211 among the at least one first line 211 includes a first sub-line s1 and a second sub-line s2 arranged separately from each other. The first sub-line s1 and the second sub-line s2 may be spaced apart in an extension direction of either of the first sub-line s1 and the second sub-line s2, or alternatively, the first sub-line s1 and the second sub-line s2 may be disconnected. The first sub-line s1 is electrically connected to a second line 212 corresponding to the first line 211 and the driver circuit 215. One end s21 of the second sub-line s2 is electrically connected to the second line 212 corresponding to the first line 211.

[0070] The second sub-line s2 is configured to be electrically connected to a peripheral circuit unit outside the display panel 21 prior to cutting of the display panel motherboard. Herein, the peripheral circuit unit is used to detection, and is specifically used to perform defect detection on the display panel 21.

[0071] In the subsequent steps of manufacturing the display panel, the display panel may be cut out from the display panel motherboard to be acquired. Upon cutting of the display panel motherboard along the edge of the display panel, as another end s22 of the second sub-line s2 is electrically connected to the peripheral circuit unit outside the display panel, another end s22 of the second sub-line s2 is exposed at the edge of the display panel.

[0072] The second line 212 is not easy to corrode, such that corrosion caused by the second sub-line s2 exposed out of the edge of the display panel 21 can be prevented from extending to the inside of the display panel 21.

[0073] In summary, the display panel is provided in the embodiments of the present disclosure. The display panel includes the driver circuit, the at least one first line, and the at least one second line in one-to-one correspondence with the at least one first line. A first line among the at least one first line, the first line includes the first sub-line and the second sub-line arranged separately from each other, and another end of the second sub-line is exposed out of the edge of the display panel. The second sub-line is configured to be electrically connected to the peripheral circuit unit outside the display panel prior to cutting of the display panel motherboard. Therefore, the display panel is electrically connected to the peripheral circuit unit outside the display panel through the second sub-line, such that defect detection is performed on the display panel, and the first sub-line and the second sub-line in the first line are electrically connected through the second line. The second line can prevent corrosion of the second sub-line exposed out of the edge of the display panel from extending to the inside of the display panel. The problem that display panels with faults are difficult to detect in the related art can be solved, and the detection effect of the display panel is improved.

[0074] Optionally, as shown in FIG. 3, the second line 212 and the first sub-line s1 are located at different layers, and the second line 212 and the second sub-line s2 are located at different layers. The first sub-line s1 and the second sub-line s2 are further isolated by the cross-layer second line 212, and then the anti-corrosion performance can be further improved.

[0075] Further, FIG. 4 is a schematic structural diagram of a part 22A of the display panel shown in FIG. 2. As shown in FIG. 4, in the subsequent manufacturing process of the display panel, an IC chip is provided, and includes pins. The pins of the IC chip are matched with the second line (in order to clearly show), such that the IC chip is electrically connected to the first sub-line s1 in the first line 211 through the second line 212, and further electrically connected to the driver circuit. The first sub-line s1 in the to-be-detected line 211 is disposed in a gap between the pins of the IC chip, which can further save space on the display panel. In order to clearly show the structure of the first line 211, 212 is not shown in FIG. 4, which is not limited by embodiments of the present application.

[0076] In some alternative embodiments, as shown in FIG. 5, FIG. 5 is a schematic cross-sectional structural diagram of the display panel shown in FIG. 4 along a connection line A1-A2. The display panel includes a base substrate 24 and a first insulating layer 25 disposed on the base substrate 24. The first insulating layer 25 is a passivation layer (PVX).

[0077] The at least one first line includes a first to-be-detected line 2111, and the first to-be-detected line 2111 is a first signal line (Data) on the display panel, and configured to provide a data signal for the driver circuit on the display panel. The display panel further includes a source-drain (SD) metal pattern. The first to-be-detected line 2111 and the source-drain metal pattern are located at the same layer.

[0078] The at least one conductive line 212 includes a first conductive line 2121, the first to-be-detected line 2111 and the first conductive line 2121 are disposed on two sides of the first insulating layer 25 respectively, and a first sub-line s1 and a second sub-line s2 in the first to-be-detected line 2111 are located at the same layer. A first disconnection hole K1 is provided between the first sub-line s1 and the second sub-line s2 in the first to-be-detected line 2111.

[0079] The first sub-line s1 in the first to-be-detected line s1 is electrically connected to the first conductive line 2121 through a first via hole 251 in the first insulating layer 25. The second sub-line s2 is electrically connected to the first conductive line 2121 through a second via hole 252 in the first insulating layer 25. The first sub-line s1 in the first to-be-detected line 2111 is connected to the driver circuit. One end, distal from the first sub-line s1, of the second sub-line s2 is exposed out of an edge of the display panel, and the exposed portion is easy to corrode.

[0080] In this way, the first sub-line s1 and the second sub-line s2 in the first to-be-detected line 2111 are electrically connected through the first conductive line 2121. The first conductive line 2121 can prevent corrosion caused by the second sub-line s2 exposed out of the edge of the display panel from extending to the first sub-line s1, and can further prevent corrosion from extending to the driver circuit. In addition, the first conductive line 2121 can prevent static electricity attracted by the second sub-line s2 exposed out of the edge of the display panel from extending to the first sub-line s1, and can further prevent the static electricity from extending to the driver circuit.

[0081] In addition, an anisotropic conductive film (ACF) is provided between the first conductive line and the pins of the IC chip, and the anisotropic conductive film is a thin film in which conductive particles are dispersed in an insulating adhesive and is configured to electrically connect the pins of the IC chip to the first conductive line. Meanwhile, the anisotropic conductive film can protect the first conductive line, and can avoid corrosion caused by exposure of a via hole on one side, proximal to the base substrate, of the first conductive line.

[0082] In an alternative example, as shown in FIG. 5, the first to-be-detected line 2111 is disposed between the first insulating layer 25 and the base substrate 24, and the first conductive line 2121 is disposed on one side, distal from the base substrate 24, of the first insulating layer 25.

[0083] In addition, the first to-be-detected line may be disposed on one side, distal from the base substrate, of the first insulating layer, and the first conductive line may be disposed on one side, proximal to the base substrate, of the first insulating layer. The first sub-line in the first to-be-detected line is electrically connected to the first conductive line through the via hole in the first insulating layer. The second sub-line is electrically connected to the first conductive line through the via hole in the first insulating layer. This is not limited in the embodiments of the present disclosure herein.

[0084] In an alternative implementation, as shown in FIG. 6, FIG. 6 is a partial cross-sectional schematic structural diagram of another display panel according to some embodiments of the present disclosure. The display panel further includes a second insulating layer 26, and the second insulating layer 26 is disposed between the first insulating layer 25 and the base substrate 24. The second insulating layer 26 is a gate insulator (GI).

[0085] The at least one first line further includes a second to-be-detected line 2112. The second to-be-detected line 2112 is a second signal line, and the second signal line is connected to a gate driver on array on the display panel. The gate driver on array (GOA) includes a plurality of gate driver units, each gate driver unit includes a plurality of thin film transistors (TFTs), wherein each gate driver unit corresponds to one row of gate lines, that is, an output end of each gate driver unit is connected to one row of gate lines, the gate driver units provide a gate driver signal for the driver circuit on the display panel, and the GOA is electrically connected to the driver circuit.

[0086] The second to-be-detected line 2112 is disposed between the second insulating layer 26 and the base substrate 24. A first sub-line s1 and a second sub-line s2 in the second to-be-detected line 2112 are located at the same layer. The display panel further includes a gate metal pattern, and the first sub-line s1 and the second sub-line s2 in the second to-be-detected line 2112 and the gate metal pattern are located at the same layer.

[0087] A second disconnection hole K2 is provided between the first sub-line s1 and the second sub-line s2 in the second to-be-detected line 2112.

[0088] The first conductive line 2121 is electrically connected to the first sub-line s1 in the second to-be-detected line 2112 through a third via hole 263 in the first insulating layer 25 and the second insulating layer 26, and the first conductive line 2121 is electrically connected to the second sub-line s2 in the second to-be-detected line 2112 through a fourth via hole 264 in the first insulating layer 25 and the second insulating layer 26. The first sub-line s1 in the second to-be-detected line 2112 is connected to the driver circuit. One end, distal from the first sub-line s1, of the second sub-line s2 is exposed out of the edge of the display panel, and the exposed portion is easy to corrode.

[0089] In this way, the first sub-line s1 and the second sub-line s2 in the second to-be-detected line 2112 are electrically connected through the first conductive line 2121. The first conductive line 2121 can prevent corrosion caused by the second sub-line s2 exposed out of the edge of the display panel from extending to the first sub-line s1, and thus can further prevent corrosion from extending to the driver circuit. In addition, the first conductive line 2121 can prevent static electricity attracted by the second sub-line s2 exposed out of the edge of the display panel from extending to the first sub-line s1, and can further prevent the static electricity from extending to the driver circuit.

[0090] Optionally, as shown in FIG. 7, FIG. 7 is a partial cross-sectional schematic structural diagram of another display panel according to some embodiments of the present disclosure. The first line 211 further includes a first transfer line 2113 and a second transfer line 2114 arranged separately from each other, and the first transfer line 2113 is disposed between the first insulating layer 25 and the second insulating layer 26, for example, the first transfer line 2113 and the source-drain metal pattern are located at the same layer. The first transfer line 2113 is electrically connected to the first sub-line s1 in the second to-be-detected line 2112 through a fifth via hole 265 in the second insulating layer 26. The first sub-line s1 in the second to-be-detected line 2112 is connected to the driver circuit.

[0091] In addition, the first transfer line 2113 is electrically connected to the first sub-line s1 in the second to-be-detected line 2112 through two or more via holes in the second insulating layer 26, so as to increase the stability of the electrical connection.

[0092] The first transfer line 2113 is electrically connected to the first conductive line 2121 through a sixth via hole 256 in the first insulating layer 25. A plurality of insulating layers are provided between the first conductive line 2121 and the second to-be-detected line 2112, and the first transfer line 2113 is arranged to connect the first conductive line 2121 to the first sub-line s1 of the second to-be-detected line 2112, such that unstable electrical connection caused by overlong via holes can be avoided.

[0093] In addition, the first transfer line 2113 is also electrically connected to the first conductive line 2121 through two or more via holes in the first insulating layer 25. On the one hand, the stability of the electrical connection can be increased, and on the other hand, the resistance of the first conductive line 2121 in a direction parallel to the base substrate 24 can be reduced.

[0094] The to-be-detected line 211 further includes a second transfer line 2114, the second transfer line 2114 is electrically connected to the second sub-line s2 in the second to-be-detected line 2112 through a seventh via hole 267 in the second insulating layer 26, and the second transfer line 2114 is electrically connected to the first conductive line 2121 through an eighth via hole 258 in the first insulating layer 25. One end, distal from the first sub-line s1, of the second sub-line s2 is exposed out of the edge of the display panel, and the exposed portion is easy to corrode.

[0095] The first transfer line 2113 and the second transfer line 2114 are arranged separately from each other, that is, the first transfer line 2113 and the second transfer line 2114 are disconnected from each other, and a third disconnection hole K3 is provided therebetween.

[0096] In this way, the first sub-line s1 and the second sub-line s2 in the second to-be-detected line 2112 are electrically connected through the first transfer line 2113, the first conductive line 2121, and the second transfer line 2114. The first conductive line 2121 can prevent corrosion caused by the second sub-line s2 exposed out of the edge of the display panel from extending to the first sub-line s1, and can further prevent corrosion from extending to the driver circuit. In addition, the first conductive line 2121 can prevent static electricity attracted by the second sub-line s2 exposed out of the edge of the display panel from extending to the first sub-line s1, and can further prevent the static electricity from extending to the driver circuit.

[0097] Optionally, as shown in FIG. 8, FIG. 8 is a partial cross-sectional schematic structural diagram of another display panel according to some embodiments of the present disclosure. The second line 212 further includes a second conductive line 2122, and the second conductive line 2122 is disposed on one side, distal from the base substrate 24, of the second insulating layer 26. The display panel further includes a third insulating layer 27, and the third insulating layer 27 is disposed on one side, distal from the base substrate 24, of the second conductive line 2122.

[0098] The second conductive line 2122 is electrically connected to the first sub-line b1 of the second to-be-detected line 2112 through a ninth via hole 269 in the second insulating layer 26, and is also electrically connected to the second sub-line b2 of the second to-be-detected line 2112 through a tenth via hole 2610 in the second insulating layer 26. The first sub-line b1 and the second sub-line b2 in the second to-be-detected line 2112 are disconnected from each other, and a second disconnection hole K2 is provided therebetween.

[0099] In this way, the first sub-line b1 and the second sub-line b2 in the second to-be-detected line 2112 are electrically connected through the second conductive line 2122. The second conductive line 2122 can prevent corrosion caused by the second sub-line b2 exposed out of the edge of the display panel from extending to the first sub-line b1, and thus can further prevent corrosion from extending to the driver circuit. In addition, the second conductive line 2122 can prevent static electricity attracted by the second sub-line s2 exposed out of the edge of the display panel from extending to the first sub-line s1, and thus can prevent the static electricity from extending to the driver circuit. In addition, the structure of the first sub-line c1 and the second sub-line c2 in the first to-be-detected line 2111 in FIG. 8 can be referred to the above embodiments, which will not be repeated in the embodiments of the present application.

[0100] Optionally, as shown in FIG. 5, the first conductive line 2121 is electrically connected to the first sub-line s1 of the first to-be-detected line 2111 through at least two first target via holes in the first insulating layer 25. Exemplarily, the at least two target via holes may include the first via hole 251 and a eleventh via hole 2511. It should be noted that FIG. 5 shows only a case where the first sub-line s1 of the first to-be-detected line 2111 and the first conductive line 2121 are electrically connected through the first via hole 251 and the eleventh via hole 2511 in the first insulating layer 25. The first conductive line 2121 is also electrically connected to the first sub-line s1 of the first to-be-detected line 2111 through more first target via holes in the first insulating layer 25. This is not limited in the embodiments of the present disclosure.

[0101] In this way, a contact area of the first conductive line 2121 and the first sub-line s1 of the first to-be-detected line 2111 can be increased. Therefore, on the one hand, the connection stability of the first conductive line 2121 and the first sub-line s1 of the first to-be-detected line 2111 can be enhanced. On the other hand, the horizontal resistance of the first conductive line 2121 in the direction parallel to the base substrate 11 can be reduced.

[0102] Similarly, as shown in FIG. 6, the first conductive line 2121 is electrically connected to the first sub-line s1 of the second to-be-detected line 2112 through at least two second target via holes in the first insulating layer 25 and the second insulating layer 26.

[0103] Exemplarily, the at least two second target via holes may include the third via hole 263 and a twelfth aperture 2631. It should be noted that FIG. 6 only illustrates that the first sub-line s1 of the second to-be-detected line 2112 and the first conductive line 2121 may be electrically connected through the third via hole 263 and the twelfth via hole 2631 in the first insulating layer 25 and the second insulating layer 26. The first conductive line 2121 may also be electrically connected to the first sub-line s1 of the second to-be-detected line 2112 through more second target via holes in the first insulating layer 25 and the second insulating layer 26. This is not limited in the embodiments of the present disclosure.

[0104] As shown in FIG. 7, the first conductive line 2121 is electrically connected to the first transfer line 2113 through at least two third target via holes in the first insulating layer 25. The at least two third target via holes include the sixth via hole 256.

[0105] As shown in FIG. 8, the second conductive line 2122 is electrically connected to the first sub-line s1 of the second to-be-detected line 2112 through at least two fourth target via holes in the second insulating layer 26. The at least two fourth target via holes include the fifth via hole 265.

[0106] Optionally, as shown in FIG. 8, a material of the first conductive line 2121 includes a transparent non-metallic conductive material, which is indium tin oxide (ITO). A material of the second conductive line 2122 is the same as the material of the first conductive line 2121.

[0107] Optionally, the display panel includes a pixel electrode, and the first conductive line and the pixel electrode are located at the same layer. Therefore, the first conductive line and the pixel electrode are formed through a one-time patterning process in the process of manufacturing the display panel, and manufacturing procedures can be saved.

[0108] FIG. 9 is a schematic structural diagram of a display panel motherboard according to some embodiments of the present disclosure. As shown in FIG. 10, the display panel motherboard 20 includes at least one display panel 21, and a redundant substrate 22 disposed outside the display panel 21. Herein ,the redundant substrate 22 is generally provided for subsequent cutting.

[0109] The display panel 21 is any display panel of the above embodiments. The display panel 21 includes a driver circuit (not shown in FIG. 2), at least one first line 211, and at least one second line 212 in one-to-one correspondence with the at least one first line 211. The display panel 21 is provided with an active area 214 and a peripheral region 213 surrounding the active area 214, and the driver circuit is disposed on the active area 214 and the peripheral region 213 of the display panel 21.

[0110] As shown in FIG. 3, a first line 211 among the at least one first line 211 includes a first sub-line s1 and a second sub-line s2 arranged separately from each other. The first sub-line s1 is electrically connected to the driver circuit 215 and a second line 212 corresponding to any first line 211 respectively. One end s21 of the second sub-line s2 is electrically connected to the corresponding second line 212.

[0111] As shown in FIG. 9, the redundant substrate 22 is provided with a peripheral circuit unit 221 and at least one extension line 222 electrically connected to the peripheral circuit unit 221, the at least one extension line 222 is in one-to-one correspondence with the at least one first line 211, and another end of the second sub-line is electrically connected to the extension line 222 corresponding to a first line 211. The peripheral circuit unit 221 is configured to perform defect detection on the display panel motherboard 20. Herein, the extension line 222 is generally a line used for detection.

[0112] The at least one extension line 222 and a source-drain metal pattern are located at the same layer, or the at least one extension line 222 and a gate metal pattern are located at the same layer.

[0113] In the subsequent steps of manufacturing the display panel 21, the redundant substrate 22 of the display panel motherboard 20 is cut off to acquire the display panel 21. Upon cutting of the display panel motherboard 20 along the edge of the display panel 21, as another end of the second sub-line is electrically connected to the extension line 222 corresponding to a first line 211, and the extension line 222 is cut off along with the redundant substrate 22, another end of the second sub-line is exposed out of the edge of the display panel 21.

[0114] The second line is not easy to corrode, such that corrosion caused by the second sub-line exposed out of the edge of the display panel can be prevented from extending to the inside of the display panel.

[0115] In summary, the display panel motherboard is provided in the embodiments of the present disclosure. The display panel motherboard includes the at least one display panel and the redundant substrate disposed outside the display panel. The display panel includes the driver circuit, the at least one first line, and the at least one second line in one-to-one correspondence with the at least one first line. A first line among the at least one first line, the first line includes the first sub-line and the second sub-line arranged separately from each other, and another end of the second sub-line is exposed out of the edge of the display panel. The second sub-line is configured to be electrically connected to the peripheral circuit unit outside the display panel prior to cutting of the display panel motherboard. Therefore, the display panel is electrically connected to the peripheral circuit unit outside the display panel through the second sub-line, such that defect detection is performed on the display panel, and the first sub-line and the second sub-line in the first line are electrically connected through the second line. The second line can prevent corrosion of the second sub-line exposed out of the edge of the display panel from extending to the inside of the display panel. The problem that display panels with faults are difficult to detect in the related art can be solved, and the detection effect of the display panel is improved.

[0116] Optionally, as shown in FIG. 10, FIG. 10 is a schematic structural diagram of another display panel motherboard according to some embodiments of the present disclosure. In the process of manufacturing the display panels 21, due to the requirement of a cutting process of the display panel motherboard 20, dummy bar regions 223 need to be arranged between the display panels 21, the dummy bar regions 223 are disposed in the redundant substrate 22, and a width of each dummy bar region 223 is 3 mm. A peripheral circuit unit 221 in the embodiments of the present disclosure is placed on the dummy bar regions, such that the space on the display panel motherboard 20 is prevented from being additionally occupied, and the utilization rate of the display panel motherboard 20 can be improved.

[0117] In an alternative implementation, as shown in FIG. 9, the at least one extension line 222 includes a first extension line 2221, the first extension line 2221 corresponds to the first to-be-detected line 2111, and the first to-be-detected line 2111 includes a first signal line. The first extension line 2221 and the source-drain metal pattern are located at the same layer.

[0118] The display panel motherboard 20 further includes a control unit 201 (switch), the first extension line 2221 is electrically connected to the control unit 201, and the control unit 201 is electrically connected to the peripheral circuit unit 221 through a plurality of signal lines. Herein, the control unit generally functions as a switch.

[0119] The at least one extension line 222 includes a second extension line 2222, the second extension line 2222 corresponds to a second to-be-detected line 2112, and the second to-be-detected line 2112 includes a second signal line. The second extension line 2222 is electrically connected to the peripheral circuit unit 221. The second extension line 2222 and the gate metal pattern are located at the same layer.

[0120] Exemplarily, as shown in FIG. 11, FIG. 11 is a schematic diagram of a control unit according to some embodiments of the present disclosure. In the case that colors of pixel units on the display panel include three colors of pixel units of red, green, and blue, the control unit 201 includes a Data Red (DR) 201R, a Data Green (DG) 201G, a Data Blue (DB) 201B, and a switch (SW) signal line 201SW. The control unit 201 includes a plurality of transistors 2011, and gates of the plurality of transistors 2011 are connected to the switch signal line 201SW to form a control terminal of the control unit 201. First electrodes of the plurality of transistors 2011 are connected to the Data Red 201R, the Data Green 201G, and the Data Blue 201B, so as to form input terminals of the control unit 201, and second electrodes of the plurality of transistors 2011 are connected to the first extension line 2221, so as to form output terminals of the control unit 201.

[0121] The input terminals of the control unit 201 are configured to receive data signals output by the peripheral circuit unit 221, and the output terminals of the control unit are configured to output the data signals to the first extension line 2221. In the case that the control terminal of the control unit receives an effective switch signal, the input terminals of the control unit are conducted with the output terminals of the control unit.

[0122] Optionally, as shown in FIG. 9, the control unit 201 is disposed in the redundant substrate 22. In the subsequent manufacturing process of the display panel motherboard, another end of the second sub-line in the first to-be-detected line is electrically connected to the first extension line 2221, and the first extension line 2221 and the control unit 201 are cut off together with the redundant substrate 22, such that another end of the second sub-line in the first to-be-detected line is exposed out of the edge of the display panel 21. The second line is not easy to corrode, such that corrosion caused by the second sub-line exposed out of the edge of the display panel can be prevented from extending to the inside of the display panel.

[0123] As shown in FIG. 12, FIG. 12 is a schematic structural diagram of a peripheral circuit unit according to some embodiments of the present disclosure. The peripheral circuit unit 221 includes a plurality of ET pads 2212. The ET pads 2212 are configured to receive detection signals and transmit the detection signals to the control unit through the Data Red 201R, the Data Green, the Data Blue 201B, and the switch signal line 201SW, and transmit the detection signals to a gate driver on array through a plurality of second signal lines 2211.

[0124] Optionally, as shown in FIG. 13, FIG. 13 is a schematic structural diagram of another display panel motherboard according to some embodiments of the present disclosure. The display panel 21 is provided with an active area 214 and a peripheral region 213 surrounding the active area 214, and a fanout region 2134 is provided in the peripheral region 213 between a first edge D1 of the active area 214 and a second edge D2 of the display panel 21. A control unit 201 and a peripheral circuit unit 221 are disposed in the redundant substrate 22 outside a third edge D3 of the display panel 21, and the third edge D3 is an edge opposite to the second edge D2. That is, the control unit 201 and the peripheral circuit unit 221 are disposed on one side where a data pad offside (DO) of the display panel is disposed. The control unit 201 is electrically connected to the peripheral circuit unit 221 through a plurality of signal lines 2012. The control unit 201 is connected to a first line in the display panel through a plurality of extension lines. The connection manner of the first line and the second line in the display panel in FIG. 13 is the same as the connection manner on the display panel shown in FIG. 2, which is not repeated in the embodiments of the present disclosure. Upon cutting of the redundant substrate, the corrosion caused by the exposure of another end of the second sub-line at the edge of the display panel can be prevented from extending to the inside of the display panel. In addition, the peripheral region 213 of the display panel is covered with a frame sealing adhesive in the subsequent manufacturing process of the display panel for packaging a frame of the display panel, and the second line is disposed under the frame sealing adhesive, such that corrosion caused by exposure of the via holes under the second line can be avoided.

[0125] Alternatively, as shown in FIG. 9, the control unit 201 and the peripheral circuit unit 221 are disposed in the redundant substrate 22 outside the second edge of the display panel 21. That is, the control unit 201 and the peripheral circuit unit 221 are disposed on one side where a data pad (DP) of the display panel is disposed. Therefore, the wiring length of the first line can be reduced, and the manufacturing process is saved.

[0126] Optionally, as shown in FIG. 14, FIG. 14 is a schematic structural diagram of another display panel motherboard according to some embodiments of the present disclosure. A control unit 201 is disposed in the peripheral region 213 outside a fourth edge D4 of the active area 214, and the fourth edge D4 is an edge opposite to the first edge D1. A peripheral circuit unit 221 is disposed in the redundant substrate 22 outside both ends of the third edge D3. Therefore, an area of the redundant substrate on the display panel motherboard can be saved, and the utilization rate of the display panel motherboard is improved. The peripheral circuit unit 221 is a miniaturized peripheral circuit unit. Exemplarily, the peripheral circuit unit is a flexible printed circuit type peripheral circuit unit. In the embodiments of the present disclosure, the control unit 201 is disposed on one side where a data pad offside of the display panel 21 is disposed, the display panel motherboard 20 is cut into a square panel in the case of detecting the display panel 21, and at this moment, the display panel motherboard includes the peripheral circuit unit, configured to perform defect detection on the display panel 21. Upon detection, the display panel motherboard is cut, the redundant substrate 22 is cut off, and the peripheral circuit unit 221 is cut off along with the redundant substrate 22. The control unit 201 is retained in the peripheral region 213 of the display panel 21, and the switch signal lines in the control unit 201 are configured to receive a v gate low (VGL) signal, such that the control unit 201 is in a closed state, and the control unit 201 is prevented from transmitting an electrical signal to the active area 214 of the display panel 21.

[0127] Optionally, as shown in FIG. 15, FIG. 15 is a schematic structural diagram of another display panel motherboard according to some embodiments of the present disclosure. The peripheral circuit unit 221 includes two peripheral circuit sub-units (221A and 221B), and the two peripheral circuit sub-units (221A and 221B) are respectively disposed in the redundant substrate 22 outside both ends of the second edge D2. Therefore, an area of the redundant substrate on the display panel motherboard can be saved, and the utilization rate of the display panel motherboard is improved.

[0128] In summary, the display panel motherboard is provided in the embodiments of the present disclosure. The display panel motherboard includes the at least one display panel and the redundant substrate disposed outside the display panel. The display panel includes the driver circuit, the at least one first line, and the at least one second line in one-to-one correspondence with the at least one first line. Each of the at least one first line, the first line includes the first sub-line and the second sub-line arranged separately from each other, and another end of the second sub-line is exposed out of the edge of the display panel. The second sub-line is configured to be electrically connected to the peripheral circuit unit outside the display panel prior to cutting of the display panel. Therefore, the display panel is electrically connected to the peripheral circuit unit outside the display panel through the second sub-line, such that defect detection is performed on the display panel, and the first sub-line and the second sub-line in the first line are electrically connected through the second line. The second line can prevent corrosion of the second sub-line exposed out of the edge of the display panel from extending to the inside of the display panel. The problem that display panels with faults are difficult to detect in the related art can be solved, and the detection effect of the display panel is improved.

[0129] It should be noted that, in the drawings, the sizes of the layers and regions may be exaggerated for clarity of illustration. Also, it can be understood that, in a case that an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or an intermediate layer may be present. In addition, it can be understood that, in a case that an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or one or more intermediate layers or elements may be present. In addition, it can also be understood that, in a case that a layer or element is referred to as being "between" two layers or elements, it may be the only layer between the two layers or elements, or one or more intermediate layers or elements may also be present. Like reference numerals refer to like elements throughout the present disclosure.

[0130] In the present disclosure, the terms "first", "second", "third", "fourth", "fifth", "sixth", "seventh", "eighth", "ninth", "tenth", and "eleventh" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The term "a plurality of" refers to two or more, unless otherwise explicitly defined.

[0131] Described above are merely optional embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalents, improvements, and the like, made within the spirit and principle of the present disclosure should fall within the protection scope of the present disclosure.