US 2026/0282761 A1Application
GaAs HALL SENSOR
Publication Date:2026-09-17
•18 Claims
•6 Drawing Sheets
Abstract
III-V Hall sensor with a GaAs semiconductor wafer, wherein a III-V insulation layer is formed on the substrate and a semiconductor layer comprising GaAs with an n-doping is arranged on the insulation layer and a shielding layer comprising n-doped GaAs is arranged in a material-tight manner on the semiconductor layer, wherein the doping of the shielding layer is higher than the doping of the semiconductor layer and a plurality of first regions and second regions are formed, wherein at least some of the first regions are completely enclosed by strip-shaped second regions and in the second regions, a vertical insulation layer is formed and metallic contacts are formed on at least some of the first areas in order to form the semiconductor layer in the first region as a Hall sensor.
Metadata
Assignee
- TDK-Micronas GmbH
Inventors
- Martin CORNILS
- Laurent OSBERGER
- Maria-Cristina VECCHI
- Anja FLECK
- Dag BEHAMMER
- Armin LANG
Application Information
Application Number:US 19/080,810
Filing Date:2025-03-15
Priority Date:2025-03-15
Classifications
IPC:
H10N52/00G01R33/07H10N52/85
Patent Drawings (6 sheets)
Description
BACKGROUND OF THE INVENTION
Field of the Invention
[0001] A vertical III-V Hall sensor is known from DE 10 2023 002 342 A1. Here, the vertical III-V Hall sensor on a GaAs substrate has an insulation layer and a GaAs semiconductor layer arranged on the insulation layer and a second insulation layer formed on the semiconductor layer interrupted by electrical contact regions. The second insulation layer is made of an InGaP compound, among other things. Furthermore, the vertical III-V Hall sensor has circumferential insulation, wherein the circumferential insulation is carried out with hydrogen implantation, among other things.
Description of the Background Art
[0002] Furthermore, different III-V Hall sensors for the measurement of the three components of a magnetic field are known from CN 102 520 376 A. For the measurement of magnetic fields running parallel to a substrate surface, a columnar Hall sensor structure arranged vertically on the substrate surface is disclosed. Here, the columnar structure is contacted at the two front sides, among other things.
[0003] Other generic III-V Hall sensors are known from EP 0 204 135 A1, CN 102 244 234 B, DE 10 2011 002580 A1 and CN 105 261 698 A.
[0004] Against this background, the object of the invention is to specify a III-V Hall sensor that advances the state of the art.
[0005] The object is achieved by a III-V Hall sensor having the features of claim 1. Advantageous embodiments of the invention are the subject of subclaims.
[0006] According to the subject-matter of the invention, a III-V Hall sensor is provided.
[0007] The III-V Hall sensor has a semiconductor wafer made of GaAs formed as a substrate with a top and a bottom and a first lattice constant and a first bandgap.
[0008] In further development, the semiconductor wafer has a diameter of 100 mm or a diameter of 150 mm or 200 mm and larger. In this case, the semiconductor wafer has a thickness of at least 100 μm.
[0009] On the top of the GaAs substrate, a III-V insulation layer is formed, which has the first lattice constant.
[0010] A GaAs semiconductor layer with the first lattice constant is formed on the insulation layer.
[0011] An n-doped GaAs shielding layer is arranged on the semiconductor layer and bonded to the semiconductor layer in a material-tight manner.
[0012] The doping of the shielding layer is higher than the doping of the semiconductor layer. Furthermore, the shielding layer is at least 10 times thicker than the semiconductor layer.
[0013] In addition, a plurality of first regions are formed, with the first regions being completely enclosed by strip-shaped second regions.
[0014] In the second regions, a vertical insulation layer is formed.
[0015] In at least some of the first regions, metallic contacts are formed in order to form a Hall sensor.
[0016] After the formation of the contacts in one region, the semiconductor layer has a flat top, wherein the region comprises at least two adjacent first regions electrically insulated from each other by the second region.
[0017] It should be noted that the terms contacts, terminal contacts, metallic contacts, and metal contacts are used synonymously below.
[0018] One advantage of the III-V Hall sensor is that the formation of a shielding layer surprisingly improves the electrical properties of the Hall sensors formed in the first regions. Since the shielding layer is very thin as compared to the semiconductor layer, an operating current imprinted by the contacts flows almost completely or exclusively through the semiconductor layer.
[0019] Another advantage is that the formation of a planar surface allows for the Hall sensors to be electrically contacted in a simple and reliable way even after insulation.
[0020] It is understood that epitaxial methods such as MOVPE methods or LPE methods or MBE methods are used for the formation of the III-V layers or the layers containing or consisting of GaAs. It is understood that the aforementioned III-V layers have grown monolithically.
[0021] Furthermore, it is understood that masking processes are used for forming the first regions and second regions, and in particular the first regions are covered with a mask at least temporarily during the formation of the second regions.
[0022] It should be noted that the MOVPE method using metal-organic precursors is currently predominantly used in the epitaxial production of GaAs layers.
[0023] It should also be noted that, in contrast to silicon technology, doping of the GaAs layers is already immanent in the production of the layers.
[0024] The implantation of dopants with subsequent activation by temperature steps such as RTA or furnace processes can only be carried out to a limited extent in GaAs, among other things due to the decomposition temperature from approx. 700° C.
[0025] Furthermore, passivation of GaAs by oxidation of the semiconductor material is also only feasible to a limited extent, in contrast to silicon technology.
[0026] In summary, it should be noted that the production of components in the field of GaAs is not compatible and is not comparable to the production of components in the field of silicon technology.
[0027] In another further development, the semiconductor layer has a doping in a range between 1·1014 1/cm3 and 5·1017 1/cm3 or in a range between 5·1014 1/cm3 and 1·1016 1/cm3 or in a range between 1·1015 1/cm3 and 5·1015 1/cm3.
[0028] It is understood that in order to achieve the highest possible mobility, the doping of the III-V semiconductor layer should be in a range below 1·1016 1/cm3 at least for a large part of the thickness.
[0029] In another further development, the semiconductor layer is homogeneously doped. In one embodiment, the semiconductor layer has a doping of 2·1015 1/cm3.
[0030] In one embodiment, the semiconductor layer has a thickness in a range between 0.5 μm and 15 μm, or a thickness in a range between 1.0 μm and 8 μm, or a thickness in a range between 2.0 μm and 5 μm.
[0031] In a further development, the semiconductor layer consists of GaAs. In another further development, the shielding layer and/or the insulation layer consists of GaAs.
[0032] In a further development, the shielding layer has the first lattice constant and the first bandgap.
[0033] In one embodiment, the shielding layer has a doping that is 10 times higher than the semiconductor layer, or a doping in a range between 5·1016 1/cm3 and 1·1018 1/cm3 or doping in a range between 1·1017 1/cm3 and 5·1017 1/cm3.
[0034] In another embodiment, the shielding layer has a thickness in a range between 20 nm and 200 nm, or a thickness in a range between 50 nm and 100 nm, or a thickness in a range between 65 nm and 75 nm.
[0035] In another further development, a III-V cover layer is designed to be material-tight on the shielding layer. The III-V cover layer has the first lattice constant. The III-V cover layer has a material with a higher bandgap than the semiconductor layer.
[0036] In one embodiment, the cover layer has a thickness in a range between 3 nm and 50 nm or a thickness in a range between 5 nm and 15 nm.
[0037] In another embodiment, the cover layer has an n-doping in a range between 5·1017 1/cm3 and 5·1019 1/cm3 or in a range between 1·1018 1/cm3 and 1·1019 1/cm3.
[0038] In a further development, the cover layer includes an InGaP compound or consists of an InGaP compound.
[0039] In a further development, the thickness of the cover layer in the regions between the metal contacts is lower than in the regions below the metal contacts.
[0040] In another development, the cover layer has a bottom formed on the shielding layer and a top opposite the bottom, wherein a delta doping is formed on the bottom and/or on the top for a reduction of contact barriers.
[0041] One advantage of delta doping is that the conductivity at the contact layer is metallic, i.e., very low-impedance. In other words, the Fermi level is in the conduction band.
[0042] In another further development, delta doping with Si is carried out during the growth of the layers during epitaxy.
[0043] For example, in a MOVPE system for the formation of a Si delta doping, a corresponding precursor is switched on and off again for a short time.
[0044] In another further development, a mask formed in the first regions is made of several layers with different materials.
[0045] In one embodiment, an organic photoresist is applied to the surface of the semiconductor wafer, i.e., to the surface of the last epitaxially applied semiconductor layer, when the masking process is carried out.
[0046] In another embodiment, a SiN layer is formed before the application of the organic paint, preferably by means of a PECVD or PVD process to protect the surface from contamination by the photoresist.
[0047] In a subsequent process step, the photoresist is then formed over the entire surface and either immediately structured or coated with a metal layer before structuring and then structured.
[0048] It should be noted that the second regions do not have a mask to form the vertical insulation layer.
[0049] In a further development, the vertical insulation layer in the second regions is formed up to the insulation layer. In other words, the vertical insulation layer is formed as a circumferential full-surface vertical layer from the semiconductor surface up to the first insulation layer.
[0050] In connection with the insulation layer, the enclosed neighboring first regions are completely electrically insulated from each other. It is understood that the first regions are also insulated from the substrate by means of the insulation layer.
[0051] In a further development, the second regions have a width between 1.0 μm and 50 μm or a width between 2 μm and 5 μm.
[0052] In another further development, the vertical insulation layer is formed from the top of the semiconductor layer or the semiconductor top beyond the insulation layer, i.e., into the substrate. This creates particularly reliable electrical insulation between neighboring first regions.
[0053] In one embodiment, the vertical insulation layer is created by means of hydrogen implantation or by a trench process.
[0054] In each case, after the formation of the vertical insulation layer in a region comprising at least several of the first regions and at least one or more of the second regions, there is a planar surface.
[0055] In another embodiment, the insulation layer comprises two sublayers with a p/n junction and/or the insulation layer consists of a III-V material with a second bandgap, wherein the second bandgap is larger than the first bandgap.
[0056] In a further development, the insulation layer has a GaAs comprising p-doped sublayer and a GaAs encompassing n-doped sublayer, wherein the p-doped sublayer is bonded to the substrate and the n-doped sublayer is material-tight to the semiconductor layer.
[0057] In another further development, the two sublayers have the first lattice constant, wherein the n-doped sublayer has a higher doping than the semiconductor layer.
[0058] In another further development, the p-doped sublayer has doping in a range between 1·1014 1/cm3 and 1·1016 1/cm3 or doping in a range between 1·1015 1/cm3 and 8·1015 1/cm3 and the n-doped sublayer has doping in a range between 1·1015 1/cm3 and 1·1017 1/cm3 or doping in a range between 8·1015 1/cm3 and 5·1017 1/cm3.
[0059] In one embodiment, the p-doped sublayer has a thickness in a range between 50 nm and 2.0 μm or a thickness in a range between 100 nm and 800 nm, and the n-doped sublayer has a thickness between 10 nm and 300 nm or a thickness in a range between 30 nm and 100 nm.
[0060] In another embodiment, at least one n-doped III-V contact layer is formed on the cover layer in order to form a low-impedance electrical connection with the cover layer after a formation of metallic terminal contacts.
[0061] In a further development, the contact layer is removed in the areas not covered by metallic terminal contacts, so that the contact layer is formed exclusively between the cover layer and the terminal contacts.
[0062] In another further development, the contact layer has the first lattice constant and/or the contact layer has the same bandgap as the semiconductor layer.
[0063] In one embodiment, the contact layer has an n-doped GaAs layer and/or an n-doped InGaAs layer, or the contact layer consists of an n-doped GaAs layer and/or an n-doped InGaAs layer.
[0064] In a further development, the contact layer has a first GaAs sublayer and a second InGaAs sublayer. In this case, the two sub-layers are connected to each other in a material-tight manner. The first sublayer is also bonded to the shielding layer or to the cover layer.
[0065] The second sub-layer is bonded to the metal contact. It is understood that the two sublayers are formed exclusively below the metal contacts in order to avoid a shunt of the semiconductor layer.
[0066] In one embodiment, the contact layer has a total thickness in a range between 10 nm and 150 nm or in a range between 30 nm and 100 nm.
[0067] In another embodiment, the doping of the contact layer is above 1·1018 1/cm3 or above 5·1018 1/cm3 or above 1·1019 1/cm3.
[0068] In a further development, the first regions comprise at least a first geometric embodiment and a second geometric embodiment, wherein the two embodiments of the first regions are electrically insulated from each other by means of a second region.
[0069] In another further development, the first embodiment in a plan view of the semiconductor surface has a rectangular or a square or a cross-shaped or an octagonal surface for the formation of a lateral Hall sensor. The second embodiment has a rectangular or a double-axe-shaped or a butterfly-shaped design for the formation of a vertical Hall sensor.
[0070] In a further development, exactly four or exactly eight terminal contacts are formed in the first embodiment and exactly three terminal contacts or exactly four or exactly five or exactly six or exactly seven terminal contacts are formed in the second embodiment.
[0071] In another further development, several first regions of the second embodiment are directly adjacent to each other, with the first regions each insulated from each other by a second region.
[0072] In one embodiment, a first region with the second embodiment is formed on two sides of the first embodiment, wherein the first two regions of the second embodiment are arranged orthogonally to each other to form a 3D Hall sensor in the form of a pixel cell.
[0073] Here, the first embodiment can detect a Z component of a magnetic field, and the first two regions of the second embodiment can detect an X component and a Y component of the magnetic field.
[0074] It should be noted that a magnetic field component formed orthogonally on the semiconductor surface is called a Z component, and two orthogonal components running along the plane of the semiconductor surface are called X and Y components, respectively.
[0075] In a further development, first regions of the second embodiment are formed around a central first region of the first embodiment on at least two sides or circumferentially on all sides in order to form a 3D Hall sensor as a so-called pixel cell.
[0076] In another further development, at least some of the second regions are formed as guard rings. It is understood that trenches are created by means of a trench process, for example, and that after the formation of a sidewall insulation by filling with a conductive material and forming electrical contacts, the trenches are electrically connected.
[0077] Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
BRIEF DESCRIPTION OF THE DRAWINGS
[0078] The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitive of the present invention, and wherein:
[0079] FIGS. 1a to 1c show cross-sectional views of manufacturing stages for the formation of a first embodiment of a Hall sensor,
[0080] FIG. 2 shows a cross-sectional view of a second embodiment of a Hall sensor,
[0081] FIG. 3 shows a top view of a semiconductor wafer with lateral Hall sensors,
[0082] FIGS. 4a to 4c show top views of different embodiments of lateral Hall sensors,
[0083] FIGS. 5a to 5d show top views of different embodiments of vertical Hall sensors,
[0084] FIGS. 6a to 6c show top views of different embodiments of pixel cells,
[0085] FIG. 7 shows a cross-sectional view of a pixel cell of an embodiment of FIG. 6d .
DETAILED DESCRIPTION
[0086] The illustrations of FIGS. 1a-c show, cross-sectional views of the manufacturing stages for the formation of a first embodiment of a GaAs Hall sensor. For reasons of clarity, a Cartesian coordinate system is drawn. According to this, the cross-sections are formed in an X-Z plane.
[0087] According to FIG. 1a , a III-V insulation layer IS is produced on a semiconductor wafer formed as a GaAs substrate SUB by means of an epitaxy process with a top OS and a bottom US in a process step on the top OS of the GaAs substrate SUB.
[0088] The substrate SUB has a first lattice constant and a first bandgap. The III-V insulation layer IS is grown on the substrate with the first lattice constant. The substrate is designed as a semi-isolated GaAs semiconductor wafer.
[0089] In a further process step, an n-doped GaAs semiconductor layer HLS with the first lattice constant is grown on the insulation layer IS using an epitaxy process.
[0090] In a subsequent process step, an n-doped GaAs shielding layer ABS is epitaxially formed on the semiconductor layer HLS, wherein the doping of the shielding layer ABS is greater than the doping of the semiconductor layer HLS.
[0091] The shielding layer ABS has the same lattice constant as the semiconductor layer HLS and a layer thickness that is at least 10 times lower than the semiconductor layer HLS.
[0092] According to the illustration of FIG. 1b , a plurality of masked first regions G1 and second mask-free regions G2 are generated in a subsequent process step by means of a masking process.
[0093] The first regions G1 are completely enclosed by the strip-shaped mask-free second regions G2.
[0094] In subsequent process steps, a vertical insulation layer VIS is created in the second regions.
[0095] In a process step not shown, the mask is removed in the first regions G1. In other words, in a non-depicted top view, the top of the semiconductor wafer is free of paint and flat.
[0096] According to the illustration of FIG. 1c , several metal contacts LK are formed in the first region G1 to form the semiconductor layer HLS in the first region G1 as a Hall sensor.
[0097] The semiconductor wafer is designed to be flat at the top of the shielding layer ABS according to the formation of the contacts LK. In other words, a region comprising first regions G1, which are formed as Hall sensor regions, and second regions G2, which are formed as vertical insulation regions, have no steps at the top of the shielding layer ABS.
[0098] FIG. 2 shows a cross-sectional view of a second embodiment of a Hall sensor. In the following, only the differences to the first embodiment, shown in connection with the illustration of FIG. 1c , are explained.
[0099] On the top of the shielding layer ABS, a thin InGaP cover layer ADS is formed, wherein the cover layer ADS has a first lattice constant. The vertical insulation layer VIS also penetrates the InGaP cover layer ABS.
[0100] Below the contacts LK, a first contact layer KS1 consisting of n-doped GaAs is formed on the top of the cover layer ADS. The first contact layer KS1 has a doping of more than 1·1017 1/cm3. Between the first contact layer KS1 and the bottom of the contacts LK, a second n-doped contact layer KS2 with the first lattice constant is formed. Preferably, the second contact layer KS2 has a doping above 5·1018 1/cm3 and is formed of InGaAs.
[0101] The insulation layer IS has a p-doped GaAs sublayer IST1 and an n-doped GaAs sublayer IST2. As a result, the two sublayers form a p/n transition, and the semiconductor layer HLS is electrically insulated from the substrate.
[0102] The p-doped GaAs sublayer IST1 is formed between the substrate SUB and the n-doped sublayer IST2. The n-doped sublayer IST2 is formed between the p-doped sublayer IST1 and the semiconductor layer HLS.
[0103] In a non-shown embodiment, the vertical insulation layer VIS penetrates the two sublayers IST1 and IST2 and extends into the substrate SUB.
[0104] FIG. 3 shows a top view of a semiconductor wafer formed in the X-Y plane with a plurality of Hall sensors. In the following, only the differences to the embodiments, shown in connection with the illustration of FIG. 1c or FIG. 2 , are explained.
[0105] The Hall sensors formed in the first regions G1 are designed as lateral Hall sensors LH, in the form of so-called Hall plates. The individual lateral Hall sensors LH have a square geometry. Metal contacts LK are formed at the respective edges in the corners.
[0106] Each of the lateral Hall sensors LH is completely enclosed by a second region G2.
[0107] For reasons of clarity, conductor paths for connecting the metal contacts are not marked.
[0108] FIGS. 4a-c show top views of different embodiments of individual lateral Hall sensors LH formed in the X-Y plane. In the following, only the differences to the embodiments, shown in connection with the illustration of FIG. 3 , are explained.
[0109] FIG. 4a shows a detailed representation of the square embodiment of the lateral Hall sensor LH of FIG. 3 . For reasons of clarity, a representation of the second regions is not shown.
[0110] The four metal contacts LK are symmetrically designed at the four corners of the Hall plate. It is understood that the Hall plate can be used to detect a magnetic field component formed in the Z direction.
[0111] FIG. 4b shows a cross-shaped formation of a lateral Hall sensor LH. The respective metal contacts LK are formed at the cross-shaped ends. It is understood that the individual branches of the cross-shaped design are symmetrical to each other.
[0112] FIG. 4c shows an octagonal formation of a lateral Hall sensor LH. The respective metal contacts LK are formed at the octagonal ends. It is understood that the individual branches of the octagonal version are symmetrical to each other.
[0113] In an embodiment not shown here, FIGS. 4 a and 4 b are rotated by 45° in the x-y plane around the z-axis.
[0114] FIG. 5a-d shows top views of different embodiments of individual vertical Hall sensors VH formed in the X-Y plane. In the embodiments shown, the vertical Hall sensors VH can be used to detect a magnetic field formed in the Y direction. In the following, only the differences to the previous embodiments are explained.
[0115] FIG. 5a shows a top view of a rectangular embodiment of a vertical Hall sensor VH. For reasons of clarity, a representation of the second regions is not shown.
[0116] The vertical Hall sensor VH has three metal contacts VK of equal length in the Y-direction. The middle metal contact VK is spaced from the two outer metal contacts VK in the X direction by a distance a1.
[0117] In an embodiment not shown, the two outer contacts VK are formed to the edge of the first region G1 or beyond.
[0118] FIG. 5b shows another double-axe-shaped embodiment of a vertical Hall sensor VH. In the following, only the differences to the embodiment shown in FIG. 5a are explained.
[0119] The two outer metal contacts VK are the same width in the Y-direction and much wider than the middle metal contact VK. All three metal contacts VK have a rectangular extension in the top view shown.
[0120] The first region G1 shows a mirror symmetry with respect to a mirror axis running in the Y-direction through a center of the middle metal contact VK.
[0121] FIG. 5c shows a butterfly-shaped extension with two wings, with a mirror axis formed in the Y direction running through the middle of the middle metal contact VK.
[0122] The two wings are each crescent-shaped. In other words, the outer edge of region G1 has no straight lines but instead is formed by arc-shaped segments.
[0123] In contrast to the middle metal contact VK, the two outer metal contacts VK are not rectangular, but are designed as circular segments.
[0124] FIG. 5d shows another embodiment of a vertical Hall sensor VH. In the following, only the differences to the embodiment shown in FIG. 5a are explained.
[0125] There are four first regions G1 lined up in the X direction, wherein a vertical partial Hall sensor VHT with three metal contacts VK is formed in each of the first regions G1. The first four regions are separated from each other by second regions G2 and are also completely enclosed by the second regions G2.
[0126] By connecting the outer metal contacts VK of adjacent vertical Hall sensors, the entire structure forms a vertical Hall sensor VH, consisting of four partial Hall sensors VHT, with four middle metal contacts VK.
[0127] FIG. 6a-d shows top views of different embodiments of pixel cells PZ. It is understood that the term pixel cell refers to an extremely compact arrangement of Hall sensors with which different components, at least two, of a magnetic field can be detected at almost the same location. In the following, only differences to the previous embodiments are explained.
[0128] FIG. 6a shows a 2D pixel cell PZ, having a lateral Hall sensor LH in a square formation with a vertical Hall sensor VH on one side of the square.
[0129] It is understood that the two Hall sensors LH and VH are each arranged in a first region. With the embodiment shown, the Z component and the X component of a magnetic field can be detected.
[0130] FIG. 6b shows a 3D pixel cell PZ, having a lateral Hall sensor LH in a square formation with vertical Hall sensors VH arranged on two adjacent sides of the square. With the embodiment shown, the Z component and the X and Y components of a magnetic field can be detected.
[0131] FIG. 6c shows a 3D pixel cell PZ, having a lateral Hall sensor LH in a square formation in the middle with vertical Hall sensors VH arranged on all sides of the square.
[0132] FIG. 6d shows a 3D pixel cell PZ, having a lateral Hall sensor LH in a cross-shaped formation in the middle with vertical Hall sensors VH arranged on all side branches. A cutting line A-A′ is drawn.
[0133] FIG. 7 shows a cross-sectional view along the cutting line A-A′ of the 3D pixel cell PZ of the embodiment of FIG. 6d , wherein reference is made to the structure shown in FIG. 2 .
[0134] It can be seen that in the first regions G1 either a vertical Hall sensor VH or a lateral Hall sensor LH is formed.
[0135] The LH lateral Hall sensor is surrounded at both ends by the vertical Hall sensors VH.
[0136] The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims.
Claims
What is claimed is:
1. The III-V Hall sensor, comprising:
a semiconductor wafer made of GaAs formed as a substrate with a top and a bottom and a first lattice constant and a first bandgap;
a III-V insulation layer formed on the top of the GaAs substrate and having the first lattice constant;
a GaAs semiconductor layer arranged on the insulation layer with the first lattice constant and an n-doping;
an n-doped GaAs shielding layer formed on the semiconductor layer, wherein the doping of the shielding layer is higher than the doping of the semiconductor layer and the shielding layer has a thickness at least 10 times lower than the semiconductor layer;
a plurality of first regions formed, wherein the first regions are completely enclosed by strip-shaped second regions and a vertical insulation layer is formed in the second regions; and
metallic contacts formed in at least some of the first regions in order to form a Hall sensor,
wherein the semiconductor layer, after the formation of the contacts, has a flat top in one region, and
wherein the region comprises at least two adjacent first regions electrically insulated from each other by the second region.
2. The III-V Hall sensor according to claim 1, wherein the semiconductor layer and/or the shielding layer and/or the insulation layer is composed of GaAs.
3. The III-V Hall sensor according to claim 1, wherein a III-V cover layer with the first lattice constant is epitaxially formed on the shielding layer, wherein the cover layer (ADS) consists of a different material with a higher bandgap than the
4. The III-V Hall sensor according to claim 3, wherein the cover layer has a bottom formed on the shielding layer and a top opposite the bottom and a delta doping is formed on the bottom and/or on the top for a reduction of contact barriers.
5. The III-V Hall sensor according to claim 1, wherein the shielding layer is formed with the first lattice constant and the bandgap of the semiconductor layer.
6. The III-V Hall sensor according to claim 1, wherein the vertical insulation layer is formed in the second regions up to the insulation layer.
7. The III-V Hall sensor according to claim 1, wherein the vertical insulation layer is created by means of hydrogen implantation and/or the vertical insulation layer comprises a trench, wherein after the formation of the vertical insulation layer, a planar surface is formed.
8. The III-V Hall sensor according to claim 1, wherein the insulation layer comprises two sublayers with a p/n junction and/or the insulation layer consists of a III-V material with a second bandgap, wherein the second bandgap is greater than the first bandgap.
9. The III-V Hall sensor according to claim 8, wherein the two sublayers are lattice-matched to the lattice constant of the substrate, wherein the n-doped sublayer has a higher doping than the semiconductor layer.
10. The III-V Hall sensor according to claim 1, wherein at least one n-doped III-V contact layer is formed on the cover layer in order to form a low-impedance electrical connection with the cover layer after the formation of metallic terminal contacts.
11. The III-V Hall sensor according to claim 10, wherein after the formation of the metallic terminal contacts, the contact layer is formed exclusively between the cover layer and the terminal contacts.
12. The III-V Hall sensor according to claim 1, wherein the first regions comprise at least a first geometric embodiment and a second geometric embodiment and the first regions are each electrically insulated from each other by means of a second region.
13. The III-V Hall sensor according to claim 12, wherein the first embodiment for the formation of a lateral Hall sensor in a plan view of the semiconductor surface comprises a rectangular or a square or a cross-shaped or an octagonal surface and the second embodiment for the formation of a vertical Hall sensor comprises a rectangular or a double axe-shaped or a butterfly-shaped design.
14. The III-V Hall sensor according to claim 12, wherein exactly four or exactly eight terminal contacts are formed in the first embodiment and exactly three terminal contacts or exactly four or exactly five or exactly six or exactly seven terminal contacts are formed in the second embodiment.
15. The III-V Hall sensor according to claim 12, wherein several first regions of the second embodiment are directly adjacent to each other, the first regions each being isolated from each other by means of a second region.
16. The III-V Hall sensor according to claim 12, wherein on two sides of a first region of the first embodiment in each case a region with the second embodiment is formed, wherein the two first regions of the second embodiment are arranged orthogonally to each other to form a 3D Hall sensor in the form of a pixel cell in order to detect a Z-component of a magnetic field with the first region of the first embodiment and to detect an X component and a Y component of the magnetic field with the two first regions of the
17. The III-V Hall sensor according to claim 12, wherein around a central first region of the first embodiment on the sides, first regions of the second embodiment are formed circumferentially in order to form a 3D Hall sensor.
18. The III-V Hall sensor according to claim 1, wherein at least some of the second regions are formed as guard rings.